Quick compiler: Single .so for all targets
With this CL, all targets can be built into a single .so (but
we're not yet doing so - the compiler driver needs to be reworked).
A new Codgen class is introduced (see compiler/codegen/codegen.h),
along with target-specific sub-classes ArmCodegen, MipsCodegens and
X86Codegen (see compiler/codegen/*/codegen_[Arm|Mips|X86].h).
Additional minor code, comment and format refactoring. Some source
files combined, temporary header files deleted and a few file
renames to better identify their function.
Next up is combining the Quick and Portable .so files.
Note: building all targets into libdvm-compiler.so increases its
size by 140K bytes. I'm inclined to not bother introducing conditional
compilation to limit code to the specific target - the added build and
testing complexity doesn't doesn't seem worth such a modest size savings.
Change-Id: Id9c5b4502ad6b77cdb31f71d3126f51a4f2e9dfe
diff --git a/src/compiler/codegen/arm/fp_arm.cc b/src/compiler/codegen/arm/fp_arm.cc
index 46695b9..a9ea916 100644
--- a/src/compiler/codegen/arm/fp_arm.cc
+++ b/src/compiler/codegen/arm/fp_arm.cc
@@ -15,13 +15,14 @@
*/
#include "arm_lir.h"
+#include "codegen_arm.h"
#include "../codegen_util.h"
#include "../ralloc_util.h"
namespace art {
-bool GenArithOpFloat(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
- RegLocation rl_src1, RegLocation rl_src2)
+bool ArmCodegen::GenArithOpFloat(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+ RegLocation rl_src1, RegLocation rl_src2)
{
int op = kThumbBkpt;
RegLocation rl_result;
@@ -63,8 +64,8 @@
return false;
}
-bool GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
- RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
+bool ArmCodegen::GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
+ RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
{
int op = kThumbBkpt;
RegLocation rl_result;
@@ -108,8 +109,8 @@
return false;
}
-bool GenConversion(CompilationUnit* cu, Instruction::Code opcode,
- RegLocation rl_dest, RegLocation rl_src)
+bool ArmCodegen::GenConversion(CompilationUnit* cu, Instruction::Code opcode,
+ RegLocation rl_dest, RegLocation rl_src)
{
int op = kThumbBkpt;
int src_reg;
@@ -161,8 +162,8 @@
return false;
}
-void GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir,
- bool gt_bias, bool is_double)
+void ArmCodegen::GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir, bool gt_bias,
+ bool is_double)
{
LIR* label_list = cu->block_label_list;
LIR* target = &label_list[bb->taken->id];
@@ -215,8 +216,8 @@
}
-bool GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
- RegLocation rl_src1, RegLocation rl_src2)
+bool ArmCodegen::GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+ RegLocation rl_src1, RegLocation rl_src2)
{
bool is_double;
int default_result;
@@ -261,12 +262,12 @@
DCHECK(!ARM_FPREG(rl_result.low_reg));
NewLIR0(cu, kThumb2Fmstat);
- OpIT(cu, (default_result == -1) ? kArmCondGt : kArmCondMi, "");
+ OpIT(cu, (default_result == -1) ? kCondGt : kCondMi, "");
NewLIR2(cu, kThumb2MovImmShift, rl_result.low_reg,
ModifiedImmediate(-default_result)); // Must not alter ccodes
GenBarrier(cu);
- OpIT(cu, kArmCondEq, "");
+ OpIT(cu, kCondEq, "");
LoadConstant(cu, rl_result.low_reg, 0);
GenBarrier(cu);
@@ -274,7 +275,7 @@
return false;
}
-void GenNegFloat(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
+void ArmCodegen::GenNegFloat(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
{
RegLocation rl_result;
rl_src = LoadValue(cu, rl_src, kFPReg);
@@ -283,7 +284,7 @@
StoreValue(cu, rl_dest, rl_result);
}
-void GenNegDouble(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
+void ArmCodegen::GenNegDouble(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
{
RegLocation rl_result;
rl_src = LoadValueWide(cu, rl_src, kFPReg);
@@ -293,7 +294,7 @@
StoreValueWide(cu, rl_dest, rl_result);
}
-bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info) {
+bool ArmCodegen::GenInlinedSqrt(CompilationUnit* cu, CallInfo* info) {
DCHECK_EQ(cu->instruction_set, kThumb2);
LIR *branch;
RegLocation rl_src = info->args[0];