commit 12051ea86ec27703b07b3d5c2cd4604b20f71810
author jeffhao <jeffhao@google.com> Thu Jan 10 11:24:31 2013 -0800
committer jeffhao <jeffhao@google.com> Thu Jan 10 12:01:07 2013 -0800
tree 6e3b17648656e8b13ee65dfcd8b04c7b7f0523f4
parent 16848f6c5c4d8394d491e887d7d805beddf173ad

Added MIPS instrumentation support.

Traceview works on MIPS, but deoptimization is untested.

Change-Id: I8b8afc8003f02965be8b3e0beca57416142c5725

src/compiler/codegen/gen_invoke.cc

diff --git a/src/compiler/codegen/gen_invoke.cc b/src/compiler/codegen/gen_invoke.cc
index a153719..fe60aff 100644
--- a/src/compiler/codegen/gen_invoke.cc
+++ b/src/compiler/codegen/gen_invoke.cc
@@ -1113,7 +1113,7 @@
   RegLocation rl_dest = InlineTarget(cu, info);
   RegLocation rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
   int offset = Thread::PeerOffset().Int32Value();
-  if (cu->instruction_set == kThumb2) {
+  if (cu->instruction_set == kThumb2 || cu->instruction_set == kMips) {
     LoadWordDisp(cu, TargetReg(kSelf), offset, rl_result.low_reg);
   } else {
     CHECK(cu->instruction_set == kX86);