commit 239c4e72b5a69754e1d6879be5ba1f85150655c1
author buzbee <buzbee@google.com> Fri Mar 16 08:42:29 2012 -0700
committer buzbee <buzbee@google.com> Sat Mar 17 16:52:32 2012 -0700
tree 45404157d7a684a739d218dc5a9ee3c0a6cdab19
parent 8ed14528fb70a9ba7cc5e471317d08dc629cbc23

Loop detection, improved reg allocation

Detect loops and loop nesting depth, and use the latter to
weight register uses (which are then used to determine which
registers to promote).

Also:

   o Fixed typo that prevented squashing of useless fp reg copies

   o Rescheduled array access checks to hide latency of limit load.

   o Add basic-block optimization pass to remove duplicate range
     checks.

   o Fixed bug that prevented recognition of redundant null
     checks following iput-wide and aput-wide.

Change-Id: Icfbae39e89b1d14b8703ad6bbb0b29c0635fed1e

src/compiler/codegen/mips/Mips32/Gen.cc

diff --git a/src/compiler/codegen/mips/Mips32/Gen.cc b/src/compiler/codegen/mips/Mips32/Gen.cc
index e86a942..dc98508 100644
--- a/src/compiler/codegen/mips/Mips32/Gen.cc
+++ b/src/compiler/codegen/mips/Mips32/Gen.cc
@@ -450,7 +450,7 @@
 #endif
     LIR* res = rawLIR(cUnit, cUnit->currentDalvikOffset, kMipsMove,
                       rDest, rSrc);
-    if (!(cUnit->disableOpt && (1 << kSafeOptimizations)) && rDest == rSrc) {
+    if (!(cUnit->disableOpt & (1 << kSafeOptimizations)) && rDest == rSrc) {
         res->flags.isNop = true;
     }
     return res;