Continuing register cleanup
Ready for review.
Continue the process of using RegStorage rather than
ints to hold register value in the top layers of codegen.
Given the huge number of changes in this CL, I've attempted
to minimize the number of actual logic changes. With this
CL, the use of ints for registers has largely been eliminated
except in the lowest utility levels. "Wide" utility routines
have been updated to take a single RegStorage rather than
a pair of ints representing low and high registers.
Upcoming CLs will be smaller and more targeted. My expectations:
o Allocate float double registers as a single double rather than
a pair of float single registers.
o Refactor to push code which assumes long and double Dalvik
values are held in a pair of register to the target dependent
layer.
o Clean-up of the xxx_mir.h files to reduce the amount of #defines
for registers. May also do a register renumbering to bring all
of our targets' register naming more consistent. Possibly
introduce a target-independent float/non-float test at the
RegStorage level.
Change-Id: I646de7392bdec94595dd2c6f76e0f1c4331096ff
diff --git a/compiler/dex/quick/x86/call_x86.cc b/compiler/dex/quick/x86/call_x86.cc
index 68e2b6d..d97cf4d 100644
--- a/compiler/dex/quick/x86/call_x86.cc
+++ b/compiler/dex/quick/x86/call_x86.cc
@@ -40,8 +40,7 @@
int key = keys[i];
BasicBlock* case_block =
mir_graph_->FindBlock(current_dalvik_offset_ + targets[i]);
- OpCmpImmBranch(kCondEq, rl_src.reg.GetReg(), key,
- &block_label_list_[case_block->id]);
+ OpCmpImmBranch(kCondEq, rl_src.reg, key, &block_label_list_[case_block->id]);
}
}
@@ -82,37 +81,37 @@
// NewLIR0(kX86Bkpt);
// Materialize a pointer to the switch table
- int start_of_method_reg;
+ RegStorage start_of_method_reg;
if (base_of_code_ != nullptr) {
// We can use the saved value.
RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low);
rl_method = LoadValue(rl_method, kCoreReg);
- start_of_method_reg = rl_method.reg.GetReg();
+ start_of_method_reg = rl_method.reg;
store_method_addr_used_ = true;
} else {
start_of_method_reg = AllocTemp();
- NewLIR1(kX86StartOfMethod, start_of_method_reg);
+ NewLIR1(kX86StartOfMethod, start_of_method_reg.GetReg());
}
int low_key = s4FromSwitchData(&table[2]);
- int keyReg;
+ RegStorage keyReg;
// Remove the bias, if necessary
if (low_key == 0) {
- keyReg = rl_src.reg.GetReg();
+ keyReg = rl_src.reg;
} else {
keyReg = AllocTemp();
- OpRegRegImm(kOpSub, keyReg, rl_src.reg.GetReg(), low_key);
+ OpRegRegImm(kOpSub, keyReg, rl_src.reg, low_key);
}
// Bounds check - if < 0 or >= size continue following switch
OpRegImm(kOpCmp, keyReg, size-1);
LIR* branch_over = OpCondBranch(kCondHi, NULL);
// Load the displacement from the switch table
- int disp_reg = AllocTemp();
- NewLIR5(kX86PcRelLoadRA, disp_reg, start_of_method_reg, keyReg, 2, WrapPointer(tab_rec));
+ RegStorage disp_reg = AllocTemp();
+ NewLIR5(kX86PcRelLoadRA, disp_reg.GetReg(), start_of_method_reg.GetReg(), keyReg.GetReg(), 2, WrapPointer(tab_rec));
// Add displacement to start of method
OpRegReg(kOpAdd, start_of_method_reg, disp_reg);
// ..and go!
- LIR* switch_branch = NewLIR1(kX86JmpR, start_of_method_reg);
+ LIR* switch_branch = NewLIR1(kX86JmpR, start_of_method_reg.GetReg());
tab_rec->anchor = switch_branch;
/* branch_over target here */
@@ -145,20 +144,20 @@
// Making a call - use explicit registers
FlushAllRegs(); /* Everything to home location */
- LoadValueDirectFixed(rl_src, rX86_ARG0);
+ LoadValueDirectFixed(rl_src, rs_rX86_ARG0);
// Materialize a pointer to the fill data image
if (base_of_code_ != nullptr) {
// We can use the saved value.
RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low);
- LoadValueDirect(rl_method, rX86_ARG2);
+ LoadValueDirect(rl_method, rs_rX86_ARG2);
store_method_addr_used_ = true;
} else {
NewLIR1(kX86StartOfMethod, rX86_ARG2);
}
NewLIR2(kX86PcRelAdr, rX86_ARG1, WrapPointer(tab_rec));
NewLIR2(kX86Add32RR, rX86_ARG1, rX86_ARG2);
- CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pHandleFillArrayData), rX86_ARG0,
- rX86_ARG1, true);
+ CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pHandleFillArrayData), rs_rX86_ARG0,
+ rs_rX86_ARG1, true);
}
void X86Mir2Lir::GenMoveException(RegLocation rl_dest) {
@@ -172,14 +171,13 @@
/*
* Mark garbage collection card. Skip if the value we're storing is null.
*/
-void X86Mir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg) {
- int reg_card_base = AllocTemp();
- int reg_card_no = AllocTemp();
+void X86Mir2Lir::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) {
+ RegStorage reg_card_base = AllocTemp();
+ RegStorage reg_card_no = AllocTemp();
LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL);
- NewLIR2(kX86Mov32RT, reg_card_base, Thread::CardTableOffset().Int32Value());
+ NewLIR2(kX86Mov32RT, reg_card_base.GetReg(), Thread::CardTableOffset().Int32Value());
OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift);
- StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0,
- kUnsignedByte);
+ StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0, kUnsignedByte);
LIR* target = NewLIR0(kPseudoTargetLabel);
branch_over->target = target;
FreeTemp(reg_card_base);
@@ -199,7 +197,7 @@
/* Build frame, return address already on stack */
// TODO: 64 bit.
- stack_decrement_ = OpRegImm(kOpSub, rX86_SP, frame_size_ - 4);
+ stack_decrement_ = OpRegImm(kOpSub, rs_rX86_SP, frame_size_ - 4);
/*
* We can safely skip the stack overflow check if we're
@@ -222,11 +220,12 @@
m2l_->ResetRegPool();
m2l_->ResetDefTracking();
GenerateTargetLabel();
- m2l_->OpRegImm(kOpAdd, kX86RegSP, sp_displace_);
+ m2l_->OpRegImm(kOpAdd, rs_rX86_SP, sp_displace_);
m2l_->ClobberCallerSave();
ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowStackOverflow);
// Assumes codegen and target are in thumb2 mode.
- m2l_->CallHelper(0, func_offset, false /* MarkSafepointPC */, false /* UseLink */);
+ m2l_->CallHelper(RegStorage::InvalidReg(), func_offset, false /* MarkSafepointPC */,
+ false /* UseLink */);
}
private:
@@ -252,7 +251,7 @@
// We have been asked to save the address of the method start for later use.
setup_method_address_[0] = NewLIR1(kX86StartOfMethod, rX86_ARG0);
int displacement = SRegOffset(base_of_code_->s_reg_low);
- setup_method_address_[1] = StoreBaseDisp(rX86_SP, displacement, rX86_ARG0, kWord);
+ setup_method_address_[1] = StoreBaseDisp(rs_rX86_SP, displacement, rs_rX86_ARG0, kWord);
}
FreeTemp(rX86_ARG0);
@@ -271,7 +270,7 @@
NewLIR0(kPseudoMethodExit);
UnSpillCoreRegs();
/* Remove frame except for return address */
- stack_increment_ = OpRegImm(kOpAdd, rX86_SP, frame_size_ - 4);
+ stack_increment_ = OpRegImm(kOpAdd, rs_rX86_SP, frame_size_ - 4);
NewLIR0(kX86Ret);
}
diff --git a/compiler/dex/quick/x86/codegen_x86.h b/compiler/dex/quick/x86/codegen_x86.h
index f2654b9..6d427e7 100644
--- a/compiler/dex/quick/x86/codegen_x86.h
+++ b/compiler/dex/quick/x86/codegen_x86.h
@@ -28,33 +28,37 @@
// Required for target - codegen helpers.
bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
- RegLocation rl_dest, int lit);
- int LoadHelper(ThreadOffset offset);
+ RegLocation rl_dest, int lit);
LIR* CheckSuspendUsingLoad() OVERRIDE;
- LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
- LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
- int s_reg);
- LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
- LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
- int r_dest, int r_dest_hi, OpSize size, int s_reg);
- LIR* LoadConstantNoClobber(int r_dest, int value);
- LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value);
- LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
- LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
- LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
- LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
- int r_src, int r_src_hi, OpSize size, int s_reg);
- void MarkGCCard(int val_reg, int tgt_addr_reg);
+ RegStorage LoadHelper(ThreadOffset offset);
+ LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,
+ int s_reg);
+ LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, int s_reg);
+ LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
+ OpSize size);
+ // TODO: collapse r_dest, r_dest_hi
+ LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
+ RegStorage r_dest, RegStorage r_dest_hi, OpSize size, int s_reg);
+ LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
+ LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
+ LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size);
+ LIR* StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src);
+ LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
+ OpSize size);
+ // TODO: collapse r_src, r_src_hi
+ LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
+ RegStorage r_src, RegStorage r_src_hi, OpSize size, int s_reg);
+ void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg);
// Required for target - register utilities.
bool IsFpReg(int reg);
+ bool IsFpReg(RegStorage reg);
bool SameRegType(int reg1, int reg2);
- // TODO: for consistency, make this return a RegStorage as well?
- int AllocTypedTemp(bool fp_hint, int reg_class);
+ RegStorage AllocTypedTemp(bool fp_hint, int reg_class);
RegStorage AllocTypedTempWide(bool fp_hint, int reg_class);
int S2d(int low_reg, int high_reg);
- int TargetReg(SpecialTargetRegister reg);
- int GetArgMappingToPhysicalReg(int arg_num);
+ RegStorage TargetReg(SpecialTargetRegister reg);
+ RegStorage GetArgMappingToPhysicalReg(int arg_num);
RegLocation GetReturnAlt();
RegLocation GetReturnWideAlt();
RegLocation LocCReturn();
@@ -65,8 +69,8 @@
uint64_t GetRegMaskCommon(int reg);
void AdjustSpillMask();
void ClobberCallerSave();
- void FlushReg(int reg);
- void FlushRegWide(int reg1, int reg2);
+ void FlushReg(RegStorage reg);
+ void FlushRegWide(RegStorage reg);
void FreeCallTemps();
void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free);
void LockCallTemps();
@@ -89,23 +93,26 @@
bool IsUnconditionalBranch(LIR* lir);
// Required for target - Dalvik-level generators.
- void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
- RegLocation rl_src1, RegLocation rl_src2);
- void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
- RegLocation rl_index, RegLocation rl_dest, int scale);
+ void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
+ RegLocation rl_src2);
+ void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
+ RegLocation rl_dest, int scale);
void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark);
void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src1, RegLocation rl_shift);
- void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
- void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
- void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
- void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
- RegLocation rl_src1, RegLocation rl_src2);
- void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
- RegLocation rl_src1, RegLocation rl_src2);
- void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
+ void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
+ RegLocation rl_src2);
+ void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
+ RegLocation rl_src2);
+ void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
+ RegLocation rl_src2);
+ void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
+ void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
+ RegLocation rl_src2);
+ void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
+ RegLocation rl_src2);
void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object);
bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);
@@ -113,17 +120,21 @@
bool GenInlinedPeek(CallInfo* info, OpSize size);
bool GenInlinedPoke(CallInfo* info, OpSize size);
void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
- void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
- void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
- void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
- LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
- ThrowKind kind);
- LIR* GenMemImmedCheck(ConditionCode c_code, int base, int offset, int check_value,
+ void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
+ RegLocation rl_src2);
+ void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
+ RegLocation rl_src2);
+ void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
+ RegLocation rl_src2);
+ LIR* GenRegMemCheck(ConditionCode c_code, RegStorage reg1, RegStorage base, int offset,
+ ThrowKind kind);
+ LIR* GenMemImmedCheck(ConditionCode c_code, RegStorage base, int offset, int check_value,
ThrowKind kind);
- RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, bool is_div);
- RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, bool is_div);
+ // TODO: collapse reg_lo, reg_hi
+ RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div);
+ RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div);
void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
- void GenDivZeroCheck(int reg_lo, int reg_hi);
+ void GenDivZeroCheck(RegStorage reg);
void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
void GenExitSequence();
void GenSpecialExitSequence();
@@ -133,8 +144,8 @@
void GenSelect(BasicBlock* bb, MIR* mir);
void GenMemBarrier(MemBarrierKind barrier_kind);
void GenMoveException(RegLocation rl_dest);
- void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result,
- int lit, int first_bit, int second_bit);
+ void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
+ int first_bit, int second_bit);
void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
@@ -154,8 +165,8 @@
* @param rl_src2 constant source operand
* @param op Opcode to be generated
*/
- void GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2, Instruction::Code op);
+ void GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,
+ Instruction::Code op);
/**
* @brief Generate a long arithmetic operation.
@@ -165,8 +176,8 @@
* @param op The DEX opcode for the operation.
* @param is_commutative The sources can be swapped if needed.
*/
- void GenLongArith(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2, Instruction::Code op, bool is_commutative);
+ void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,
+ Instruction::Code op, bool is_commutative);
/**
* @brief Generate a two operand long arithmetic operation.
@@ -191,8 +202,8 @@
* @param rl_dest Result to be set to 0 or 1.
* @param rl_src Object to be tested.
*/
- void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx,
- RegLocation rl_dest, RegLocation rl_src);
+ void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest,
+ RegLocation rl_src);
/*
*
* @brief Implement Set up instanceof a class with x86 specific code.
@@ -208,38 +219,37 @@
void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final,
bool type_known_abstract, bool use_declaring_class,
bool can_assume_type_is_in_dex_cache,
- uint32_t type_idx, RegLocation rl_dest,
- RegLocation rl_src);
+ uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src);
// Single operation generators.
LIR* OpUnconditionalBranch(LIR* target);
- LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target);
- LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target);
+ LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
+ LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
LIR* OpCondBranch(ConditionCode cc, LIR* target);
- LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target);
- LIR* OpFpRegCopy(int r_dest, int r_src);
+ LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
+ LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
LIR* OpIT(ConditionCode cond, const char* guide);
- LIR* OpMem(OpKind op, int rBase, int disp);
- LIR* OpPcRelLoad(int reg, LIR* target);
- LIR* OpReg(OpKind op, int r_dest_src);
- LIR* OpRegCopy(int r_dest, int r_src);
- LIR* OpRegCopyNoInsert(int r_dest, int r_src);
- LIR* OpRegImm(OpKind op, int r_dest_src1, int value);
- LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset);
+ LIR* OpMem(OpKind op, RegStorage r_base, int disp);
+ LIR* OpPcRelLoad(RegStorage reg, LIR* target);
+ LIR* OpReg(OpKind op, RegStorage r_dest_src);
+ LIR* OpRegCopy(RegStorage r_dest, RegStorage r_src);
+ LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
+ LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
+ LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset);
+ LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value);
LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value);
- LIR* OpRegMem(OpKind op, int r_dest, RegLocation value);
- LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2);
- LIR* OpMovRegMem(int r_dest, int r_base, int offset, MoveType move_type);
- LIR* OpMovMemReg(int r_base, int offset, int r_src, MoveType move_type);
- LIR* OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src);
- LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value);
- LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2);
+ LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
+ LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
+ LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
+ LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
+ LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
+ LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
LIR* OpTestSuspend(LIR* target);
LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset);
- LIR* OpVldm(int rBase, int count);
- LIR* OpVstm(int rBase, int count);
- void OpLea(int rBase, int reg1, int reg2, int scale, int offset);
- void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi);
+ LIR* OpVldm(RegStorage r_base, int count);
+ LIR* OpVstm(RegStorage r_base, int count);
+ void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset);
+ void OpRegCopyWide(RegStorage dest, RegStorage src);
void OpTlsCmp(ThreadOffset offset, int val);
void OpRegThreadMem(OpKind op, int r_dest, ThreadOffset thread_offset);
@@ -254,7 +264,7 @@
RegLocation UpdateLocWide(RegLocation loc);
RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update);
RegLocation EvalLoc(RegLocation loc, int reg_class, bool update);
- int AllocTempDouble();
+ RegStorage AllocTempDouble();
void ResetDefLocWide(RegLocation rl);
/*
@@ -264,8 +274,8 @@
* @param rl_lhs Left hand operand.
* @param rl_rhs Right hand operand.
*/
- void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest,
- RegLocation rl_lhs, RegLocation rl_rhs);
+ void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs,
+ RegLocation rl_rhs);
/*
* @brief Dump a RegLocation using printf
@@ -327,8 +337,7 @@
void EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg);
void EmitOpReg(const X86EncodingMap* entry, uint8_t reg);
void EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp);
- void EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index,
- int scale, int disp);
+ void EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp);
void EmitMemReg(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg);
void EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm);
void EmitRegMem(const X86EncodingMap* entry, uint8_t reg, uint8_t base, int disp);
@@ -340,7 +349,8 @@
void EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2);
void EmitRegRegImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm);
void EmitRegRegImmRev(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm);
- void EmitRegMemImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t base, int disp, int32_t imm);
+ void EmitRegMemImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t base, int disp,
+ int32_t imm);
void EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
void EmitThreadImm(const X86EncodingMap* entry, int disp, int imm);
void EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
@@ -429,8 +439,8 @@
* @param is_div 'true' if this is a division, 'false' for a remainder.
* @param check_zero 'true' if an exception should be generated if the divisor is 0.
*/
- RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2, bool is_div, bool check_zero);
+ RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,
+ bool is_div, bool check_zero);
/*
* @brief Generate an integer div or rem operation by a literal.
@@ -457,7 +467,7 @@
* @param src Source Register.
* @param val Constant multiplier.
*/
- void GenImulRegImm(int dest, int src, int val);
+ void GenImulRegImm(RegStorage dest, RegStorage src, int val);
/*
* Generate an imul of a memory location by a constant or a better sequence.
@@ -466,7 +476,7 @@
* @param displacement Displacement on stack of Symbolic Register.
* @param val Constant multiplier.
*/
- void GenImulMemImm(int dest, int sreg, int displacement, int val);
+ void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val);
/*
* @brief Compare memory to immediate, and branch if condition true.
@@ -477,7 +487,7 @@
* @param offset The offset from the base.
* @param check_value The immediate to compare to.
*/
- LIR* OpCmpMemImmBranch(ConditionCode cond, int temp_reg, int base_reg,
+ LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
int offset, int check_value, LIR* target);
/*
diff --git a/compiler/dex/quick/x86/fp_x86.cc b/compiler/dex/quick/x86/fp_x86.cc
index b745207..ec4d9db 100644
--- a/compiler/dex/quick/x86/fp_x86.cc
+++ b/compiler/dex/quick/x86/fp_x86.cc
@@ -63,15 +63,15 @@
rl_src1 = LoadValue(rl_src1, kFPReg);
rl_src2 = LoadValue(rl_src2, kFPReg);
rl_result = EvalLoc(rl_dest, kFPReg, true);
- int r_dest = rl_result.reg.GetReg();
- int r_src1 = rl_src1.reg.GetReg();
- int r_src2 = rl_src2.reg.GetReg();
+ RegStorage r_dest = rl_result.reg;
+ RegStorage r_src1 = rl_src1.reg;
+ RegStorage r_src2 = rl_src2.reg;
if (r_dest == r_src2) {
r_src2 = AllocTempFloat();
OpRegCopy(r_src2, r_dest);
}
OpRegCopy(r_dest, r_src1);
- NewLIR2(op, r_dest, r_src2);
+ NewLIR2(op, r_dest.GetReg(), r_src2.GetReg());
StoreValue(rl_dest, rl_result);
}
@@ -118,14 +118,15 @@
rl_result = EvalLoc(rl_dest, kFPReg, true);
DCHECK(rl_dest.wide);
DCHECK(rl_result.wide);
- int r_dest = S2d(rl_result.reg.GetReg(), rl_result.reg.GetHighReg());
- int r_src1 = S2d(rl_src1.reg.GetReg(), rl_src1.reg.GetHighReg());
- int r_src2 = S2d(rl_src2.reg.GetReg(), rl_src2.reg.GetHighReg());
+ // TODO: update with direct 64-bit reg.
+ int r_dest = S2d(rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg());
+ int r_src1 = S2d(rl_src1.reg.GetLowReg(), rl_src1.reg.GetHighReg());
+ int r_src2 = S2d(rl_src2.reg.GetLowReg(), rl_src2.reg.GetHighReg());
if (r_dest == r_src2) {
- r_src2 = AllocTempDouble() | X86_FP_DOUBLE;
- OpRegCopy(r_src2, r_dest);
+ r_src2 = AllocTempDouble().GetLowReg() | X86_FP_DOUBLE;
+ OpRegCopy(RegStorage::Solo64(r_src2), RegStorage::Solo64(r_dest));
}
- OpRegCopy(r_dest, r_src1);
+ OpRegCopy(RegStorage::Solo64(r_dest), RegStorage::Solo64(r_src1));
NewLIR2(op, r_dest, r_src2);
StoreValueWide(rl_dest, rl_result);
}
@@ -140,7 +141,7 @@
// If the source is in physical register, then put it in its location on stack.
if (rl_src.location == kLocPhysReg) {
- RegisterInfo* lo_info = GetRegInfo(rl_src.reg.GetReg());
+ RegisterInfo* lo_info = GetRegInfo(rl_src.reg.GetLowReg());
if (lo_info != nullptr && lo_info->is_temp) {
// Calling FlushSpecificReg because it will only write back VR if it is dirty.
@@ -148,19 +149,19 @@
} else {
// It must have been register promoted if it is not a temp but is still in physical
// register. Since we need it to be in memory to convert, we place it there now.
- StoreBaseDispWide(TargetReg(kSp), src_v_reg_offset, rl_src.reg.GetReg(), rl_src.reg.GetHighReg());
+ StoreBaseDispWide(TargetReg(kSp), src_v_reg_offset, rl_src.reg);
}
}
// Push the source virtual register onto the x87 stack.
- LIR *fild64 = NewLIR2NoDest(kX86Fild64M, TargetReg(kSp), src_v_reg_offset + LOWORD_OFFSET);
+ LIR *fild64 = NewLIR2NoDest(kX86Fild64M, TargetReg(kSp).GetReg(), src_v_reg_offset + LOWORD_OFFSET);
AnnotateDalvikRegAccess(fild64, (src_v_reg_offset + LOWORD_OFFSET) >> 2,
true /* is_load */, true /* is64bit */);
// Now pop off x87 stack and store it in the destination VR's stack location.
int opcode = is_double ? kX86Fstp64M : kX86Fstp32M;
int displacement = is_double ? dest_v_reg_offset + LOWORD_OFFSET : dest_v_reg_offset;
- LIR *fstp = NewLIR2NoDest(opcode, TargetReg(kSp), displacement);
+ LIR *fstp = NewLIR2NoDest(opcode, TargetReg(kSp).GetReg(), displacement);
AnnotateDalvikRegAccess(fstp, displacement >> 2, false /* is_load */, is_double);
/*
@@ -181,13 +182,13 @@
if (is_double) {
rl_result = EvalLocWide(rl_dest, kFPReg, true);
- LoadBaseDispWide(TargetReg(kSp), dest_v_reg_offset, rl_result.reg.GetReg(), rl_result.reg.GetHighReg(), INVALID_SREG);
+ LoadBaseDispWide(TargetReg(kSp), dest_v_reg_offset, rl_result.reg, INVALID_SREG);
StoreFinalValueWide(rl_dest, rl_result);
} else {
rl_result = EvalLoc(rl_dest, kFPReg, true);
- LoadWordDisp(TargetReg(kSp), dest_v_reg_offset, rl_result.reg.GetReg());
+ LoadWordDisp(TargetReg(kSp), dest_v_reg_offset, rl_result.reg);
StoreFinalValue(rl_dest, rl_result);
}
@@ -223,9 +224,9 @@
// In case result vreg is also src vreg, break association to avoid useless copy by EvalLoc()
ClobberSReg(rl_dest.s_reg_low);
rl_result = EvalLoc(rl_dest, kCoreReg, true);
- int temp_reg = AllocTempFloat();
+ int temp_reg = AllocTempFloat().GetReg();
- LoadConstant(rl_result.reg.GetReg(), 0x7fffffff);
+ LoadConstant(rl_result.reg, 0x7fffffff);
NewLIR2(kX86Cvtsi2ssRR, temp_reg, rl_result.reg.GetReg());
NewLIR2(kX86ComissRR, src_reg, temp_reg);
LIR* branch_pos_overflow = NewLIR2(kX86Jcc8, 0, kX86CondA);
@@ -241,13 +242,13 @@
}
case Instruction::DOUBLE_TO_INT: {
rl_src = LoadValueWide(rl_src, kFPReg);
- src_reg = rl_src.reg.GetReg();
+ src_reg = rl_src.reg.GetLowReg();
// In case result vreg is also src vreg, break association to avoid useless copy by EvalLoc()
ClobberSReg(rl_dest.s_reg_low);
rl_result = EvalLoc(rl_dest, kCoreReg, true);
- int temp_reg = AllocTempDouble() | X86_FP_DOUBLE;
+ int temp_reg = AllocTempDouble().GetLowReg() | X86_FP_DOUBLE;
- LoadConstant(rl_result.reg.GetReg(), 0x7fffffff);
+ LoadConstant(rl_result.reg, 0x7fffffff);
NewLIR2(kX86Cvtsi2sdRR, temp_reg, rl_result.reg.GetReg());
NewLIR2(kX86ComisdRR, src_reg, temp_reg);
LIR* branch_pos_overflow = NewLIR2(kX86Jcc8, 0, kX86CondA);
@@ -278,14 +279,14 @@
}
if (rl_src.wide) {
rl_src = LoadValueWide(rl_src, rcSrc);
- src_reg = S2d(rl_src.reg.GetReg(), rl_src.reg.GetHighReg());
+ src_reg = S2d(rl_src.reg.GetLowReg(), rl_src.reg.GetHighReg());
} else {
rl_src = LoadValue(rl_src, rcSrc);
src_reg = rl_src.reg.GetReg();
}
if (rl_dest.wide) {
rl_result = EvalLoc(rl_dest, kFPReg, true);
- NewLIR2(op, S2d(rl_result.reg.GetReg(), rl_result.reg.GetHighReg()), src_reg);
+ NewLIR2(op, S2d(rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg()), src_reg);
StoreValueWide(rl_dest, rl_result);
} else {
rl_result = EvalLoc(rl_dest, kFPReg, true);
@@ -307,14 +308,14 @@
src_reg2 = rl_src2.reg.GetReg();
} else {
rl_src1 = LoadValueWide(rl_src1, kFPReg);
- src_reg1 = S2d(rl_src1.reg.GetReg(), rl_src1.reg.GetHighReg());
+ src_reg1 = S2d(rl_src1.reg.GetLowReg(), rl_src1.reg.GetHighReg());
rl_src2 = LoadValueWide(rl_src2, kFPReg);
- src_reg2 = S2d(rl_src2.reg.GetReg(), rl_src2.reg.GetHighReg());
+ src_reg2 = S2d(rl_src2.reg.GetLowReg(), rl_src2.reg.GetHighReg());
}
// In case result vreg is also src vreg, break association to avoid useless copy by EvalLoc()
ClobberSReg(rl_dest.s_reg_low);
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
- LoadConstantNoClobber(rl_result.reg.GetReg(), unordered_gt ? 1 : 0);
+ LoadConstantNoClobber(rl_result.reg, unordered_gt ? 1 : 0);
if (single) {
NewLIR2(kX86UcomissRR, src_reg1, src_reg2);
} else {
@@ -357,8 +358,8 @@
rl_src2 = mir_graph_->GetSrcWide(mir, 2);
rl_src1 = LoadValueWide(rl_src1, kFPReg);
rl_src2 = LoadValueWide(rl_src2, kFPReg);
- NewLIR2(kX86UcomisdRR, S2d(rl_src1.reg.GetReg(), rl_src1.reg.GetHighReg()),
- S2d(rl_src2.reg.GetReg(), rl_src2.reg.GetHighReg()));
+ NewLIR2(kX86UcomisdRR, S2d(rl_src1.reg.GetLowReg(), rl_src1.reg.GetHighReg()),
+ S2d(rl_src2.reg.GetLowReg(), rl_src2.reg.GetHighReg()));
} else {
rl_src1 = mir_graph_->GetSrc(mir, 0);
rl_src2 = mir_graph_->GetSrc(mir, 1);
@@ -418,7 +419,7 @@
RegLocation rl_result;
rl_src = LoadValue(rl_src, kCoreReg);
rl_result = EvalLoc(rl_dest, kCoreReg, true);
- OpRegRegImm(kOpAdd, rl_result.reg.GetReg(), rl_src.reg.GetReg(), 0x80000000);
+ OpRegRegImm(kOpAdd, rl_result.reg, rl_src.reg, 0x80000000);
StoreValue(rl_dest, rl_result);
}
@@ -426,8 +427,8 @@
RegLocation rl_result;
rl_src = LoadValueWide(rl_src, kCoreReg);
rl_result = EvalLoc(rl_dest, kCoreReg, true);
- OpRegRegImm(kOpAdd, rl_result.reg.GetHighReg(), rl_src.reg.GetHighReg(), 0x80000000);
- OpRegCopy(rl_result.reg.GetReg(), rl_src.reg.GetReg());
+ OpRegRegImm(kOpAdd, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), 0x80000000);
+ OpRegCopy(rl_result.reg, rl_src.reg);
StoreValueWide(rl_dest, rl_result);
}
@@ -436,8 +437,8 @@
RegLocation rl_dest = InlineTargetWide(info); // double place for result
rl_src = LoadValueWide(rl_src, kFPReg);
RegLocation rl_result = EvalLoc(rl_dest, kFPReg, true);
- NewLIR2(kX86SqrtsdRR, S2d(rl_result.reg.GetReg(), rl_result.reg.GetHighReg()),
- S2d(rl_src.reg.GetReg(), rl_src.reg.GetHighReg()));
+ NewLIR2(kX86SqrtsdRR, S2d(rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg()),
+ S2d(rl_src.reg.GetLowReg(), rl_src.reg.GetHighReg()));
StoreValueWide(rl_dest, rl_result);
return true;
}
diff --git a/compiler/dex/quick/x86/int_x86.cc b/compiler/dex/quick/x86/int_x86.cc
index 14278a4..37b2b37 100644
--- a/compiler/dex/quick/x86/int_x86.cc
+++ b/compiler/dex/quick/x86/int_x86.cc
@@ -26,10 +26,10 @@
/*
* Perform register memory operation.
*/
-LIR* X86Mir2Lir::GenRegMemCheck(ConditionCode c_code,
- int reg1, int base, int offset, ThrowKind kind) {
+LIR* X86Mir2Lir::GenRegMemCheck(ConditionCode c_code, RegStorage reg1, RegStorage base,
+ int offset, ThrowKind kind) {
LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind,
- current_dalvik_offset_, reg1, base, offset);
+ current_dalvik_offset_, reg1.GetReg(), base.GetReg(), offset);
OpRegMem(kOpCmp, reg1, base, offset);
LIR* branch = OpCondBranch(c_code, tgt);
// Remember branch target - will process later
@@ -40,11 +40,11 @@
/*
* Perform a compare of memory to immediate value
*/
-LIR* X86Mir2Lir::GenMemImmedCheck(ConditionCode c_code,
- int base, int offset, int check_value, ThrowKind kind) {
+LIR* X86Mir2Lir::GenMemImmedCheck(ConditionCode c_code, RegStorage base, int offset,
+ int check_value, ThrowKind kind) {
LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind,
- current_dalvik_offset_, base, check_value, 0);
- NewLIR3(IS_SIMM8(check_value) ? kX86Cmp32MI8 : kX86Cmp32MI, base, offset, check_value);
+ current_dalvik_offset_, base.GetReg(), check_value, 0);
+ NewLIR3(IS_SIMM8(check_value) ? kX86Cmp32MI8 : kX86Cmp32MI, base.GetReg(), offset, check_value);
LIR* branch = OpCondBranch(c_code, tgt);
// Remember branch target - will process later
throw_launchpads_.Insert(tgt);
@@ -61,18 +61,20 @@
RegLocation rl_src2) {
FlushAllRegs();
LockCallTemps(); // Prepare for explicit register usage
- LoadValueDirectWideFixed(rl_src1, r0, r1);
- LoadValueDirectWideFixed(rl_src2, r2, r3);
+ RegStorage r_tmp1(RegStorage::k64BitPair, r0, r1);
+ RegStorage r_tmp2(RegStorage::k64BitPair, r2, r3);
+ LoadValueDirectWideFixed(rl_src1, r_tmp1);
+ LoadValueDirectWideFixed(rl_src2, r_tmp2);
// Compute (r1:r0) = (r1:r0) - (r3:r2)
- OpRegReg(kOpSub, r0, r2); // r0 = r0 - r2
- OpRegReg(kOpSbc, r1, r3); // r1 = r1 - r3 - CF
+ OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2
+ OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF
NewLIR2(kX86Set8R, r2, kX86CondL); // r2 = (r1:r0) < (r3:r2) ? 1 : 0
NewLIR2(kX86Movzx8RR, r2, r2);
- OpReg(kOpNeg, r2); // r2 = -r2
- OpRegReg(kOpOr, r0, r1); // r0 = high | low - sets ZF
+ OpReg(kOpNeg, rs_r2); // r2 = -r2
+ OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = high | low - sets ZF
NewLIR2(kX86Set8R, r0, kX86CondNz); // r0 = (r1:r0) != (r3:r2) ? 1 : 0
NewLIR2(kX86Movzx8RR, r0, r0);
- OpRegReg(kOpOr, r0, r2); // r0 = r0 | r2
+ OpRegReg(kOpOr, rs_r0, rs_r2); // r0 = r0 | r2
RegLocation rl_result = LocCReturn();
StoreValue(rl_dest, rl_result);
}
@@ -101,9 +103,8 @@
return kX86CondO;
}
-LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, int src1, int src2,
- LIR* target) {
- NewLIR2(kX86Cmp32RR, src1, src2);
+LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) {
+ NewLIR2(kX86Cmp32RR, src1.GetReg(), src2.GetReg());
X86ConditionCode cc = X86ConditionEncoding(cond);
LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ ,
cc);
@@ -111,13 +112,13 @@
return branch;
}
-LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, int reg,
+LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg,
int check_value, LIR* target) {
if ((check_value == 0) && (cond == kCondEq || cond == kCondNe)) {
// TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode
- NewLIR2(kX86Test32RR, reg, reg);
+ NewLIR2(kX86Test32RR, reg.GetReg(), reg.GetReg());
} else {
- NewLIR2(IS_SIMM8(check_value) ? kX86Cmp32RI8 : kX86Cmp32RI, reg, check_value);
+ NewLIR2(IS_SIMM8(check_value) ? kX86Cmp32RI8 : kX86Cmp32RI, reg.GetReg(), check_value);
}
X86ConditionCode cc = X86ConditionEncoding(cond);
LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc);
@@ -125,61 +126,70 @@
return branch;
}
-LIR* X86Mir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) {
- if (X86_FPREG(r_dest) || X86_FPREG(r_src))
+LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) {
+ // If src or dest is a pair, we'll be using low reg.
+ if (r_dest.IsPair()) {
+ r_dest = r_dest.GetLow();
+ }
+ if (r_src.IsPair()) {
+ r_src = r_src.GetLow();
+ }
+ if (X86_FPREG(r_dest.GetReg()) || X86_FPREG(r_src.GetReg()))
return OpFpRegCopy(r_dest, r_src);
LIR* res = RawLIR(current_dalvik_offset_, kX86Mov32RR,
- r_dest, r_src);
+ r_dest.GetReg(), r_src.GetReg());
if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
res->flags.is_nop = true;
}
return res;
}
-LIR* X86Mir2Lir::OpRegCopy(int r_dest, int r_src) {
+LIR* X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) {
LIR *res = OpRegCopyNoInsert(r_dest, r_src);
AppendLIR(res);
return res;
}
-void X86Mir2Lir::OpRegCopyWide(int dest_lo, int dest_hi,
- int src_lo, int src_hi) {
- bool dest_fp = X86_FPREG(dest_lo) && X86_FPREG(dest_hi);
- bool src_fp = X86_FPREG(src_lo) && X86_FPREG(src_hi);
- assert(X86_FPREG(src_lo) == X86_FPREG(src_hi));
- assert(X86_FPREG(dest_lo) == X86_FPREG(dest_hi));
+void X86Mir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) {
+ // FIXME: handle k64BitSolo when we start using them.
+ DCHECK(r_dest.IsPair());
+ DCHECK(r_src.IsPair());
+ bool dest_fp = X86_FPREG(r_dest.GetLowReg());
+ bool src_fp = X86_FPREG(r_src.GetLowReg());
if (dest_fp) {
if (src_fp) {
- OpRegCopy(S2d(dest_lo, dest_hi), S2d(src_lo, src_hi));
+ // TODO: we ought to handle this case here - reserve OpRegCopy for 32-bit copies.
+ OpRegCopy(RegStorage::Solo64(S2d(r_dest.GetLowReg(), r_dest.GetHighReg())),
+ RegStorage::Solo64(S2d(r_src.GetLowReg(), r_src.GetHighReg())));
} else {
// TODO: Prevent this from happening in the code. The result is often
// unused or could have been loaded more easily from memory.
- NewLIR2(kX86MovdxrRR, dest_lo, src_lo);
- dest_hi = AllocTempDouble();
- NewLIR2(kX86MovdxrRR, dest_hi, src_hi);
- NewLIR2(kX86PunpckldqRR, dest_lo, dest_hi);
- FreeTemp(dest_hi);
+ NewLIR2(kX86MovdxrRR, r_dest.GetLowReg(), r_src.GetLowReg());
+ RegStorage r_tmp = AllocTempDouble();
+ NewLIR2(kX86MovdxrRR, r_tmp.GetLowReg(), r_src.GetHighReg());
+ NewLIR2(kX86PunpckldqRR, r_dest.GetLowReg(), r_tmp.GetLowReg());
+ FreeTemp(r_tmp);
}
} else {
if (src_fp) {
- NewLIR2(kX86MovdrxRR, dest_lo, src_lo);
- NewLIR2(kX86PsrlqRI, src_lo, 32);
- NewLIR2(kX86MovdrxRR, dest_hi, src_lo);
+ NewLIR2(kX86MovdrxRR, r_dest.GetLowReg(), r_src.GetLowReg());
+ NewLIR2(kX86PsrlqRI, r_src.GetLowReg(), 32);
+ NewLIR2(kX86MovdrxRR, r_dest.GetHighReg(), r_src.GetLowReg());
} else {
// Handle overlap
- if (src_hi == dest_lo && src_lo == dest_hi) {
+ if (r_src.GetHighReg() == r_dest.GetLowReg() && r_src.GetLowReg() == r_dest.GetHighReg()) {
// Deal with cycles.
- int temp_reg = AllocTemp();
- OpRegCopy(temp_reg, dest_hi);
- OpRegCopy(dest_hi, dest_lo);
- OpRegCopy(dest_lo, temp_reg);
+ RegStorage temp_reg = AllocTemp();
+ OpRegCopy(temp_reg, r_dest.GetHigh());
+ OpRegCopy(r_dest.GetHigh(), r_dest.GetLow());
+ OpRegCopy(r_dest.GetLow(), temp_reg);
FreeTemp(temp_reg);
- } else if (src_hi == dest_lo) {
- OpRegCopy(dest_hi, src_hi);
- OpRegCopy(dest_lo, src_lo);
+ } else if (r_src.GetHighReg() == r_dest.GetLowReg()) {
+ OpRegCopy(r_dest.GetHigh(), r_src.GetHigh());
+ OpRegCopy(r_dest.GetLow(), r_src.GetLow());
} else {
- OpRegCopy(dest_lo, src_lo);
- OpRegCopy(dest_hi, src_hi);
+ OpRegCopy(r_dest.GetLow(), r_src.GetLow());
+ OpRegCopy(r_dest.GetHigh(), r_src.GetHigh());
}
}
}
@@ -219,30 +229,31 @@
* mov t1, $true_case
* cmovz result_reg, t1
*/
- const bool result_reg_same_as_src = (rl_src.location == kLocPhysReg && rl_src.reg.GetReg() == rl_result.reg.GetReg());
+ const bool result_reg_same_as_src =
+ (rl_src.location == kLocPhysReg && rl_src.reg.GetReg() == rl_result.reg.GetReg());
const bool true_zero_case = (true_val == 0 && false_val != 0 && !result_reg_same_as_src);
const bool false_zero_case = (false_val == 0 && true_val != 0 && !result_reg_same_as_src);
const bool catch_all_case = !(true_zero_case || false_zero_case);
if (true_zero_case || false_zero_case) {
- OpRegReg(kOpXor, rl_result.reg.GetReg(), rl_result.reg.GetReg());
+ OpRegReg(kOpXor, rl_result.reg, rl_result.reg);
}
if (true_zero_case || false_zero_case || catch_all_case) {
- OpRegImm(kOpCmp, rl_src.reg.GetReg(), 0);
+ OpRegImm(kOpCmp, rl_src.reg, 0);
}
if (catch_all_case) {
- OpRegImm(kOpMov, rl_result.reg.GetReg(), false_val);
+ OpRegImm(kOpMov, rl_result.reg, false_val);
}
if (true_zero_case || false_zero_case || catch_all_case) {
ConditionCode cc = true_zero_case ? NegateComparison(ccode) : ccode;
int immediateForTemp = true_zero_case ? false_val : true_val;
- int temp1_reg = AllocTemp();
+ RegStorage temp1_reg = AllocTemp();
OpRegImm(kOpMov, temp1_reg, immediateForTemp);
- OpCondRegReg(kOpCmov, cc, rl_result.reg.GetReg(), temp1_reg);
+ OpCondRegReg(kOpCmov, cc, rl_result.reg, temp1_reg);
FreeTemp(temp1_reg);
}
@@ -269,15 +280,15 @@
*/
// kMirOpSelect is generated just for conditional cases when comparison is done with zero.
- OpRegImm(kOpCmp, rl_src.reg.GetReg(), 0);
+ OpRegImm(kOpCmp, rl_src.reg, 0);
if (rl_result.reg.GetReg() == rl_true.reg.GetReg()) {
- OpCondRegReg(kOpCmov, NegateComparison(ccode), rl_result.reg.GetReg(), rl_false.reg.GetReg());
+ OpCondRegReg(kOpCmov, NegateComparison(ccode), rl_result.reg, rl_false.reg);
} else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) {
- OpCondRegReg(kOpCmov, ccode, rl_result.reg.GetReg(), rl_true.reg.GetReg());
+ OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg);
} else {
- OpRegCopy(rl_result.reg.GetReg(), rl_false.reg.GetReg());
- OpCondRegReg(kOpCmov, ccode, rl_result.reg.GetReg(), rl_true.reg.GetReg());
+ OpRegCopy(rl_result.reg, rl_false.reg);
+ OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg);
}
}
@@ -303,22 +314,24 @@
FlushAllRegs();
LockCallTemps(); // Prepare for explicit register usage
- LoadValueDirectWideFixed(rl_src1, r0, r1);
- LoadValueDirectWideFixed(rl_src2, r2, r3);
+ RegStorage r_tmp1(RegStorage::k64BitPair, r0, r1);
+ RegStorage r_tmp2(RegStorage::k64BitPair, r2, r3);
+ LoadValueDirectWideFixed(rl_src1, r_tmp1);
+ LoadValueDirectWideFixed(rl_src2, r_tmp2);
// Swap operands and condition code to prevent use of zero flag.
if (ccode == kCondLe || ccode == kCondGt) {
// Compute (r3:r2) = (r3:r2) - (r1:r0)
- OpRegReg(kOpSub, r2, r0); // r2 = r2 - r0
- OpRegReg(kOpSbc, r3, r1); // r3 = r3 - r1 - CF
+ OpRegReg(kOpSub, rs_r2, rs_r0); // r2 = r2 - r0
+ OpRegReg(kOpSbc, rs_r3, rs_r1); // r3 = r3 - r1 - CF
} else {
// Compute (r1:r0) = (r1:r0) - (r3:r2)
- OpRegReg(kOpSub, r0, r2); // r0 = r0 - r2
- OpRegReg(kOpSbc, r1, r3); // r1 = r1 - r3 - CF
+ OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2
+ OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF
}
switch (ccode) {
case kCondEq:
case kCondNe:
- OpRegReg(kOpOr, r0, r1); // r0 = r0 | r1
+ OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = r0 | r1
break;
case kCondLe:
ccode = kCondGe;
@@ -342,11 +355,11 @@
LIR* taken = &block_label_list_[bb->taken];
LIR* not_taken = &block_label_list_[bb->fall_through];
rl_src1 = LoadValueWide(rl_src1, kCoreReg);
- int32_t low_reg = rl_src1.reg.GetReg();
- int32_t high_reg = rl_src1.reg.GetHighReg();
+ RegStorage low_reg = rl_src1.reg.GetLow();
+ RegStorage high_reg = rl_src1.reg.GetHigh();
if (val == 0 && (ccode == kCondEq || ccode == kCondNe)) {
- int t_reg = AllocTemp();
+ RegStorage t_reg = AllocTemp();
OpRegRegReg(kOpOr, t_reg, low_reg, high_reg);
FreeTemp(t_reg);
OpCondBranch(ccode, taken);
@@ -450,8 +463,7 @@
shift = p - 32;
}
-RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, int reg_lo,
- int lit, bool is_div) {
+RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) {
LOG(FATAL) << "Unexpected use of GenDivRemLit for x86";
return rl_dest;
}
@@ -465,8 +477,8 @@
LockCallTemps(); // Prepare for explicit register usage.
// Assume that the result will be in EDX.
- RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, kVectorNotUsed,
- RegStorage(RegStorage::k32BitSolo, r2), INVALID_SREG, INVALID_SREG};
+ RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, kVectorNotUsed, rs_r2,
+ INVALID_SREG, INVALID_SREG};
// handle div/rem by 1 special case.
if (imm == 1) {
@@ -475,15 +487,15 @@
StoreValue(rl_result, rl_src);
} else {
// x % 1 == 0.
- LoadConstantNoClobber(r0, 0);
+ LoadConstantNoClobber(rs_r0, 0);
// For this case, return the result in EAX.
rl_result.reg.SetReg(r0);
}
} else if (imm == -1) { // handle 0x80000000 / -1 special case.
if (is_div) {
LIR *minint_branch = 0;
- LoadValueDirectFixed(rl_src, r0);
- OpRegImm(kOpCmp, r0, 0x80000000);
+ LoadValueDirectFixed(rl_src, rs_r0);
+ OpRegImm(kOpCmp, rs_r0, 0x80000000);
minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondEq);
// for x != MIN_INT, x / -1 == -x.
@@ -496,7 +508,7 @@
branch_around->target = NewLIR0(kPseudoTargetLabel);
} else {
// x % -1 == 0.
- LoadConstantNoClobber(r0, 0);
+ LoadConstantNoClobber(rs_r0, 0);
}
// For this case, return the result in EAX.
rl_result.reg.SetReg(r0);
@@ -524,36 +536,36 @@
*/
// Numerator into EAX.
- int numerator_reg = -1;
+ RegStorage numerator_reg;
if (!is_div || (imm > 0 && magic < 0) || (imm < 0 && magic > 0)) {
// We will need the value later.
if (rl_src.location == kLocPhysReg) {
// We can use it directly.
DCHECK(rl_src.reg.GetReg() != r0 && rl_src.reg.GetReg() != r2);
- numerator_reg = rl_src.reg.GetReg();
+ numerator_reg = rl_src.reg;
} else {
- LoadValueDirectFixed(rl_src, r1);
- numerator_reg = r1;
+ numerator_reg = rs_r1;
+ LoadValueDirectFixed(rl_src, numerator_reg);
}
- OpRegCopy(r0, numerator_reg);
+ OpRegCopy(rs_r0, numerator_reg);
} else {
// Only need this once. Just put it into EAX.
- LoadValueDirectFixed(rl_src, r0);
+ LoadValueDirectFixed(rl_src, rs_r0);
}
// EDX = magic.
- LoadConstantNoClobber(r2, magic);
+ LoadConstantNoClobber(rs_r2, magic);
// EDX:EAX = magic & dividend.
NewLIR1(kX86Imul32DaR, r2);
if (imm > 0 && magic < 0) {
// Add numerator to EDX.
- DCHECK_NE(numerator_reg, -1);
- NewLIR2(kX86Add32RR, r2, numerator_reg);
+ DCHECK(numerator_reg.Valid());
+ NewLIR2(kX86Add32RR, r2, numerator_reg.GetReg());
} else if (imm < 0 && magic > 0) {
- DCHECK_NE(numerator_reg, -1);
- NewLIR2(kX86Sub32RR, r2, numerator_reg);
+ DCHECK(numerator_reg.Valid());
+ NewLIR2(kX86Sub32RR, r2, numerator_reg.GetReg());
}
// Do we need the shift?
@@ -565,7 +577,7 @@
// Add 1 to EDX if EDX < 0.
// Move EDX to EAX.
- OpRegCopy(r0, r2);
+ OpRegCopy(rs_r0, rs_r2);
// Move sign bit to bit 0, zeroing the rest.
NewLIR2(kX86Shr32RI, r2, 31);
@@ -577,11 +589,11 @@
if (!is_div) {
// We need to compute the remainder.
// Remainder is divisor - (quotient * imm).
- DCHECK_NE(numerator_reg, -1);
- OpRegCopy(r0, numerator_reg);
+ DCHECK(numerator_reg.Valid());
+ OpRegCopy(rs_r0, numerator_reg);
// EAX = numerator * imm.
- OpRegRegImm(kOpMul, r2, r2, imm);
+ OpRegRegImm(kOpMul, rs_r2, rs_r2, imm);
// EDX -= EAX.
NewLIR2(kX86Sub32RR, r0, r2);
@@ -594,8 +606,8 @@
return rl_result;
}
-RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, int reg_lo,
- int reg_hi, bool is_div) {
+RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi,
+ bool is_div) {
LOG(FATAL) << "Unexpected use of GenDivRem for x86";
return rl_dest;
}
@@ -607,31 +619,31 @@
LockCallTemps(); // Prepare for explicit register usage.
// Load LHS into EAX.
- LoadValueDirectFixed(rl_src1, r0);
+ LoadValueDirectFixed(rl_src1, rs_r0);
// Load RHS into EBX.
- LoadValueDirectFixed(rl_src2, r1);
+ LoadValueDirectFixed(rl_src2, rs_r1);
// Copy LHS sign bit into EDX.
NewLIR0(kx86Cdq32Da);
if (check_zero) {
// Handle division by zero case.
- GenImmedCheck(kCondEq, r1, 0, kThrowDivZero);
+ GenImmedCheck(kCondEq, rs_r1, 0, kThrowDivZero);
}
// Have to catch 0x80000000/-1 case, or we will get an exception!
- OpRegImm(kOpCmp, r1, -1);
+ OpRegImm(kOpCmp, rs_r1, -1);
LIR *minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe);
// RHS is -1.
- OpRegImm(kOpCmp, r0, 0x80000000);
+ OpRegImm(kOpCmp, rs_r0, 0x80000000);
LIR * minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe);
// In 0x80000000/-1 case.
if (!is_div) {
// For DIV, EAX is already right. For REM, we need EDX 0.
- LoadConstantNoClobber(r2, 0);
+ LoadConstantNoClobber(rs_r2, 0);
}
LIR* done = NewLIR1(kX86Jmp8, 0);
@@ -642,8 +654,8 @@
done->target = NewLIR0(kPseudoTargetLabel);
// Result is in EAX for div and EDX for rem.
- RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, kVectorNotUsed,
- RegStorage(RegStorage::k32BitSolo, r0), INVALID_SREG, INVALID_SREG};
+ RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, kVectorNotUsed, rs_r0,
+ INVALID_SREG, INVALID_SREG};
if (!is_div) {
rl_result.reg.SetReg(r2);
}
@@ -672,17 +684,17 @@
}
// Pick the first integer as min/max.
- OpRegCopy(rl_result.reg.GetReg(), rl_src1.reg.GetReg());
+ OpRegCopy(rl_result.reg, rl_src1.reg);
// If the integers are both in the same register, then there is nothing else to do
// because they are equal and we have already moved one into the result.
if (rl_src1.reg.GetReg() != rl_src2.reg.GetReg()) {
// It is possible we didn't pick correctly so do the actual comparison now.
- OpRegReg(kOpCmp, rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
+ OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
// Conditionally move the other integer into the destination register.
ConditionCode condition_code = is_min ? kCondGt : kCondLt;
- OpCondRegReg(kOpCmov, condition_code, rl_result.reg.GetReg(), rl_src2.reg.GetReg());
+ OpCondRegReg(kOpCmov, condition_code, rl_result.reg, rl_src2.reg);
}
StoreValue(rl_dest, rl_result);
@@ -691,18 +703,18 @@
bool X86Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) {
RegLocation rl_src_address = info->args[0]; // long address
- rl_src_address.wide = 0; // ignore high half in info->args[1]
+ rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1]
RegLocation rl_dest = size == kLong ? InlineTargetWide(info) : InlineTarget(info);
RegLocation rl_address = LoadValue(rl_src_address, kCoreReg);
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
if (size == kLong) {
// Unaligned access is allowed on x86.
- LoadBaseDispWide(rl_address.reg.GetReg(), 0, rl_result.reg.GetReg(), rl_result.reg.GetHighReg(), INVALID_SREG);
+ LoadBaseDispWide(rl_address.reg, 0, rl_result.reg, INVALID_SREG);
StoreValueWide(rl_dest, rl_result);
} else {
DCHECK(size == kSignedByte || size == kSignedHalf || size == kWord);
// Unaligned access is allowed on x86.
- LoadBaseDisp(rl_address.reg.GetReg(), 0, rl_result.reg.GetReg(), size, INVALID_SREG);
+ LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size, INVALID_SREG);
StoreValue(rl_dest, rl_result);
}
return true;
@@ -710,32 +722,32 @@
bool X86Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) {
RegLocation rl_src_address = info->args[0]; // long address
- rl_src_address.wide = 0; // ignore high half in info->args[1]
+ rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1]
RegLocation rl_src_value = info->args[2]; // [size] value
RegLocation rl_address = LoadValue(rl_src_address, kCoreReg);
if (size == kLong) {
// Unaligned access is allowed on x86.
RegLocation rl_value = LoadValueWide(rl_src_value, kCoreReg);
- StoreBaseDispWide(rl_address.reg.GetReg(), 0, rl_value.reg.GetReg(), rl_value.reg.GetHighReg());
+ StoreBaseDispWide(rl_address.reg, 0, rl_value.reg);
} else {
DCHECK(size == kSignedByte || size == kSignedHalf || size == kWord);
// Unaligned access is allowed on x86.
RegLocation rl_value = LoadValue(rl_src_value, kCoreReg);
- StoreBaseDisp(rl_address.reg.GetReg(), 0, rl_value.reg.GetReg(), size);
+ StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size);
}
return true;
}
-void X86Mir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) {
- NewLIR5(kX86Lea32RA, rBase, reg1, reg2, scale, offset);
+void X86Mir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) {
+ NewLIR5(kX86Lea32RA, r_base.GetReg(), reg1.GetReg(), reg2.GetReg(), scale, offset);
}
void X86Mir2Lir::OpTlsCmp(ThreadOffset offset, int val) {
NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val);
}
-static bool IsInReg(X86Mir2Lir *pMir2Lir, const RegLocation &rl, int reg) {
- return !rl.reg.IsInvalid() && rl.reg.GetReg() == reg && (pMir2Lir->IsLive(reg) || rl.home);
+static bool IsInReg(X86Mir2Lir *pMir2Lir, const RegLocation &rl, RegStorage reg) {
+ return rl.reg.Valid() && rl.reg.GetReg() == reg.GetReg() && (pMir2Lir->IsLive(reg) || rl.home);
}
bool X86Mir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) {
@@ -743,7 +755,7 @@
// Unused - RegLocation rl_src_unsafe = info->args[0];
RegLocation rl_src_obj = info->args[1]; // Object - known non-null
RegLocation rl_src_offset = info->args[2]; // long low
- rl_src_offset.wide = 0; // ignore high half in info->args[3]
+ rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3]
RegLocation rl_src_expected = info->args[4]; // int, long or Object
// If is_long, high half is in info->args[5]
RegLocation rl_src_new_value = info->args[is_long ? 6 : 5]; // int, long or Object
@@ -754,8 +766,10 @@
// TODO: CFI support.
FlushAllRegs();
LockCallTemps();
- LoadValueDirectWideFixed(rl_src_expected, rAX, rDX);
- LoadValueDirectWideFixed(rl_src_new_value, rBX, rCX);
+ RegStorage r_tmp1(RegStorage::k64BitPair, rAX, rDX);
+ RegStorage r_tmp2(RegStorage::k64BitPair, rBX, rCX);
+ LoadValueDirectWideFixed(rl_src_expected, r_tmp1);
+ LoadValueDirectWideFixed(rl_src_new_value, r_tmp2);
NewLIR1(kX86Push32R, rDI);
MarkTemp(rDI);
LockTemp(rDI);
@@ -763,14 +777,14 @@
MarkTemp(rSI);
LockTemp(rSI);
const int push_offset = 4 /* push edi */ + 4 /* push esi */;
- int srcObjSp = IsInReg(this, rl_src_obj, rSI) ? 0
- : (IsInReg(this, rl_src_obj, rDI) ? 4
+ int srcObjSp = IsInReg(this, rl_src_obj, rs_rSI) ? 0
+ : (IsInReg(this, rl_src_obj, rs_rDI) ? 4
: (SRegOffset(rl_src_obj.s_reg_low) + push_offset));
- LoadWordDisp(TargetReg(kSp), srcObjSp, rDI);
- int srcOffsetSp = IsInReg(this, rl_src_offset, rSI) ? 0
- : (IsInReg(this, rl_src_offset, rDI) ? 4
+ LoadWordDisp(TargetReg(kSp), srcObjSp, rs_rDI);
+ int srcOffsetSp = IsInReg(this, rl_src_offset, rs_rSI) ? 0
+ : (IsInReg(this, rl_src_offset, rs_rDI) ? 4
: (SRegOffset(rl_src_offset.s_reg_low) + push_offset));
- LoadWordDisp(TargetReg(kSp), srcOffsetSp, rSI);
+ LoadWordDisp(TargetReg(kSp), srcOffsetSp, rs_rSI);
NewLIR4(kX86LockCmpxchg8bA, rDI, rSI, 0, 0);
// After a store we need to insert barrier in case of potential load. Since the
@@ -786,8 +800,8 @@
FreeCallTemps();
} else {
// EAX must hold expected for CMPXCHG. Neither rl_new_value, nor r_ptr may be in EAX.
- FlushReg(r0);
- LockTemp(r0);
+ FlushReg(rs_r0);
+ LockTemp(rs_r0);
RegLocation rl_object = LoadValue(rl_src_obj, kCoreReg);
RegLocation rl_new_value = LoadValue(rl_src_new_value, kCoreReg);
@@ -795,12 +809,12 @@
if (is_object && !mir_graph_->IsConstantNullRef(rl_new_value)) {
// Mark card for object assuming new value is stored.
FreeTemp(r0); // Temporarily release EAX for MarkGCCard().
- MarkGCCard(rl_new_value.reg.GetReg(), rl_object.reg.GetReg());
+ MarkGCCard(rl_new_value.reg, rl_object.reg);
LockTemp(r0);
}
RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg);
- LoadValueDirect(rl_src_expected, r0);
+ LoadValueDirect(rl_src_expected, rs_r0);
NewLIR5(kX86LockCmpxchgAR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0, rl_new_value.reg.GetReg());
// After a store we need to insert barrier in case of potential load. Since the
@@ -819,7 +833,7 @@
return true;
}
-LIR* X86Mir2Lir::OpPcRelLoad(int reg, LIR* target) {
+LIR* X86Mir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) {
CHECK(base_of_code_ != nullptr);
// Address the start of the method
@@ -831,7 +845,8 @@
// We don't know the proper offset for the value, so pick one that will force
// 4 byte offset. We will fix this up in the assembler later to have the right
// value.
- LIR *res = RawLIR(current_dalvik_offset_, kX86Mov32RM, reg, reg, 256, 0, 0, target);
+ LIR *res = RawLIR(current_dalvik_offset_, kX86Mov32RM, reg.GetReg(), reg.GetReg(), 256,
+ 0, 0, target);
res->target = target;
res->flags.fixup = kFixupLoad;
SetMemRefType(res, true, kLiteral);
@@ -839,12 +854,12 @@
return res;
}
-LIR* X86Mir2Lir::OpVldm(int rBase, int count) {
+LIR* X86Mir2Lir::OpVldm(RegStorage r_base, int count) {
LOG(FATAL) << "Unexpected use of OpVldm for x86";
return NULL;
}
-LIR* X86Mir2Lir::OpVstm(int rBase, int count) {
+LIR* X86Mir2Lir::OpVstm(RegStorage r_base, int count) {
LOG(FATAL) << "Unexpected use of OpVstm for x86";
return NULL;
}
@@ -852,22 +867,22 @@
void X86Mir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src,
RegLocation rl_result, int lit,
int first_bit, int second_bit) {
- int t_reg = AllocTemp();
- OpRegRegImm(kOpLsl, t_reg, rl_src.reg.GetReg(), second_bit - first_bit);
- OpRegRegReg(kOpAdd, rl_result.reg.GetReg(), rl_src.reg.GetReg(), t_reg);
+ RegStorage t_reg = AllocTemp();
+ OpRegRegImm(kOpLsl, t_reg, rl_src.reg, second_bit - first_bit);
+ OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg);
FreeTemp(t_reg);
if (first_bit != 0) {
- OpRegRegImm(kOpLsl, rl_result.reg.GetReg(), rl_result.reg.GetReg(), first_bit);
+ OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit);
}
}
-void X86Mir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi) {
- // We are not supposed to clobber either of the provided registers, so allocate
- // a temporary to use for the check.
- int t_reg = AllocTemp();
+void X86Mir2Lir::GenDivZeroCheck(RegStorage reg) {
+ DCHECK(reg.IsPair()); // TODO: allow 64BitSolo.
+ // We are not supposed to clobber the incoming storage, so allocate a temporary.
+ RegStorage t_reg = AllocTemp();
// Doing an OR is a quick way to check if both registers are zero. This will set the flags.
- OpRegRegReg(kOpOr, t_reg, reg_lo, reg_hi);
+ OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh());
// In case of zero, throw ArithmeticException.
GenCheck(kCondEq, kThrowDivZero);
@@ -883,7 +898,7 @@
}
// Decrement register and branch on condition
-LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) {
+LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) {
OpRegImm(kOpSub, reg, 1);
return OpCondBranch(c_code, target);
}
@@ -899,10 +914,10 @@
return NULL;
}
-void X86Mir2Lir::GenImulRegImm(int dest, int src, int val) {
+void X86Mir2Lir::GenImulRegImm(RegStorage dest, RegStorage src, int val) {
switch (val) {
case 0:
- NewLIR2(kX86Xor32RR, dest, dest);
+ NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg());
break;
case 1:
OpRegCopy(dest, src);
@@ -913,17 +928,17 @@
}
}
-void X86Mir2Lir::GenImulMemImm(int dest, int sreg, int displacement, int val) {
+void X86Mir2Lir::GenImulMemImm(RegStorage dest, int sreg, int displacement, int val) {
LIR *m;
switch (val) {
case 0:
- NewLIR2(kX86Xor32RR, dest, dest);
+ NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg());
break;
case 1:
- LoadBaseDisp(rX86_SP, displacement, dest, kWord, sreg);
+ LoadBaseDisp(rs_rX86_SP, displacement, dest, kWord, sreg);
break;
default:
- m = NewLIR4(IS_SIMM8(val) ? kX86Imul32RMI8 : kX86Imul32RMI, dest, rX86_SP,
+ m = NewLIR4(IS_SIMM8(val) ? kX86Imul32RMI8 : kX86Imul32RMI, dest.GetReg(), rX86_SP,
displacement, val);
AnnotateDalvikRegAccess(m, displacement >> 2, true /* is_load */, true /* is_64bit */);
break;
@@ -941,8 +956,8 @@
int64_t val = mir_graph_->ConstantValueWide(rl_src2);
if (val == 0) {
RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true);
- OpRegReg(kOpXor, rl_result.reg.GetReg(), rl_result.reg.GetReg());
- OpRegReg(kOpXor, rl_result.reg.GetHighReg(), rl_result.reg.GetHighReg());
+ OpRegReg(kOpXor, rl_result.reg.GetLow(), rl_result.reg.GetLow());
+ OpRegReg(kOpXor, rl_result.reg.GetHigh(), rl_result.reg.GetHigh());
StoreValueWide(rl_dest, rl_result);
return;
} else if (val == 1) {
@@ -974,22 +989,22 @@
// ECX <- 1H * 2L
// EAX <- 1L * 2H
if (src1_in_reg) {
- GenImulRegImm(r1, rl_src1.reg.GetHighReg(), val_lo);
- GenImulRegImm(r0, rl_src1.reg.GetReg(), val_hi);
+ GenImulRegImm(rs_r1, rl_src1.reg.GetHigh(), val_lo);
+ GenImulRegImm(rs_r0, rl_src1.reg.GetLow(), val_hi);
} else {
- GenImulMemImm(r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo);
- GenImulMemImm(r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi);
+ GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo);
+ GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi);
}
// ECX <- ECX + EAX (2H * 1L) + (1H * 2L)
NewLIR2(kX86Add32RR, r1, r0);
// EAX <- 2L
- LoadConstantNoClobber(r0, val_lo);
+ LoadConstantNoClobber(rs_r0, val_lo);
// EDX:EAX <- 2L * 1L (double precision)
if (src1_in_reg) {
- NewLIR1(kX86Mul32DaR, rl_src1.reg.GetReg());
+ NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg());
} else {
LIR *m = NewLIR2(kX86Mul32DaM, rX86_SP, displacement + LOWORD_OFFSET);
AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2,
@@ -1001,7 +1016,7 @@
// Result is EDX:EAX
RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, kVectorNotUsed,
- RegStorage(RegStorage::k64BitPair, r0, r2),
+ RegStorage::MakeRegPair(rs_r0, rs_r2),
INVALID_SREG, INVALID_SREG};
StoreValueWide(rl_dest, rl_result);
return;
@@ -1025,7 +1040,7 @@
if (src1_in_reg) {
NewLIR2(kX86Mov32RR, r1, rl_src1.reg.GetHighReg());
} else {
- LoadBaseDisp(rX86_SP, SRegOffset(rl_src1.s_reg_low) + HIWORD_OFFSET, r1,
+ LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src1.s_reg_low) + HIWORD_OFFSET, rs_r1,
kWord, GetSRegHi(rl_src1.s_reg_low));
}
@@ -1033,7 +1048,7 @@
// Take advantage of the fact that the values are the same.
// ECX <- ECX * 2L (1H * 2L)
if (src2_in_reg) {
- NewLIR2(kX86Imul32RR, r1, rl_src2.reg.GetReg());
+ NewLIR2(kX86Imul32RR, r1, rl_src2.reg.GetLowReg());
} else {
int displacement = SRegOffset(rl_src2.s_reg_low);
LIR *m = NewLIR3(kX86Imul32RM, r1, rX86_SP, displacement + LOWORD_OFFSET);
@@ -1048,13 +1063,13 @@
if (src2_in_reg) {
NewLIR2(kX86Mov32RR, r0, rl_src2.reg.GetHighReg());
} else {
- LoadBaseDisp(rX86_SP, SRegOffset(rl_src2.s_reg_low) + HIWORD_OFFSET, r0,
+ LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + HIWORD_OFFSET, rs_r0,
kWord, GetSRegHi(rl_src2.s_reg_low));
}
// EAX <- EAX * 1L (2H * 1L)
if (src1_in_reg) {
- NewLIR2(kX86Imul32RR, r0, rl_src1.reg.GetReg());
+ NewLIR2(kX86Imul32RR, r0, rl_src1.reg.GetLowReg());
} else {
int displacement = SRegOffset(rl_src1.s_reg_low);
LIR *m = NewLIR3(kX86Imul32RM, r0, rX86_SP, displacement + LOWORD_OFFSET);
@@ -1064,7 +1079,7 @@
// ECX <- ECX * 2L (1H * 2L)
if (src2_in_reg) {
- NewLIR2(kX86Imul32RR, r1, rl_src2.reg.GetReg());
+ NewLIR2(kX86Imul32RR, r1, rl_src2.reg.GetLowReg());
} else {
int displacement = SRegOffset(rl_src2.s_reg_low);
LIR *m = NewLIR3(kX86Imul32RM, r1, rX86_SP, displacement + LOWORD_OFFSET);
@@ -1078,15 +1093,15 @@
// EAX <- 2L
if (src2_in_reg) {
- NewLIR2(kX86Mov32RR, r0, rl_src2.reg.GetReg());
+ NewLIR2(kX86Mov32RR, r0, rl_src2.reg.GetLowReg());
} else {
- LoadBaseDisp(rX86_SP, SRegOffset(rl_src2.s_reg_low) + LOWORD_OFFSET, r0,
+ LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + LOWORD_OFFSET, rs_r0,
kWord, rl_src2.s_reg_low);
}
// EDX:EAX <- 2L * 1L (double precision)
if (src1_in_reg) {
- NewLIR1(kX86Mul32DaR, rl_src1.reg.GetReg());
+ NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg());
} else {
int displacement = SRegOffset(rl_src1.s_reg_low);
LIR *m = NewLIR2(kX86Mul32DaM, rX86_SP, displacement + LOWORD_OFFSET);
@@ -1099,7 +1114,7 @@
// Result is EDX:EAX
RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, kVectorNotUsed,
- RegStorage(RegStorage::k64BitPair, r0, r2), INVALID_SREG, INVALID_SREG};
+ RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG};
StoreValueWide(rl_dest, rl_result);
}
@@ -1111,32 +1126,31 @@
// Both operands are in registers.
// But we must ensure that rl_src is in pair
rl_src = EvalLocWide(rl_src, kCoreReg, true);
- if (rl_dest.reg.GetReg() == rl_src.reg.GetHighReg()) {
+ if (rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()) {
// The registers are the same, so we would clobber it before the use.
- int temp_reg = AllocTemp();
- OpRegCopy(temp_reg, rl_dest.reg.GetReg());
- rl_src.reg.SetHighReg(temp_reg);
+ RegStorage temp_reg = AllocTemp();
+ OpRegCopy(temp_reg, rl_dest.reg);
+ rl_src.reg.SetHighReg(temp_reg.GetReg());
}
- NewLIR2(x86op, rl_dest.reg.GetReg(), rl_src.reg.GetReg());
+ NewLIR2(x86op, rl_dest.reg.GetLowReg(), rl_src.reg.GetLowReg());
x86op = GetOpcode(op, rl_dest, rl_src, true);
NewLIR2(x86op, rl_dest.reg.GetHighReg(), rl_src.reg.GetHighReg());
- FreeTemp(rl_src.reg.GetReg());
- FreeTemp(rl_src.reg.GetHighReg());
+ FreeTemp(rl_src.reg);
return;
}
// RHS is in memory.
DCHECK((rl_src.location == kLocDalvikFrame) ||
(rl_src.location == kLocCompilerTemp));
- int rBase = TargetReg(kSp);
+ int r_base = TargetReg(kSp).GetReg();
int displacement = SRegOffset(rl_src.s_reg_low);
- LIR *lir = NewLIR3(x86op, rl_dest.reg.GetReg(), rBase, displacement + LOWORD_OFFSET);
+ LIR *lir = NewLIR3(x86op, rl_dest.reg.GetLowReg(), r_base, displacement + LOWORD_OFFSET);
AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2,
true /* is_load */, true /* is64bit */);
x86op = GetOpcode(op, rl_dest, rl_src, true);
- lir = NewLIR3(x86op, rl_dest.reg.GetHighReg(), rBase, displacement + HIWORD_OFFSET);
+ lir = NewLIR3(x86op, rl_dest.reg.GetHighReg(), r_base, displacement + HIWORD_OFFSET);
AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2,
true /* is_load */, true /* is64bit */);
}
@@ -1160,18 +1174,17 @@
// Operate directly into memory.
X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false);
- int rBase = TargetReg(kSp);
+ int r_base = TargetReg(kSp).GetReg();
int displacement = SRegOffset(rl_dest.s_reg_low);
- LIR *lir = NewLIR3(x86op, rBase, displacement + LOWORD_OFFSET, rl_src.reg.GetReg());
+ LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, rl_src.reg.GetLowReg());
AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2,
false /* is_load */, true /* is64bit */);
x86op = GetOpcode(op, rl_dest, rl_src, true);
- lir = NewLIR3(x86op, rBase, displacement + HIWORD_OFFSET, rl_src.reg.GetHighReg());
+ lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, rl_src.reg.GetHighReg());
AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2,
false /* is_load */, true /* is64bit */);
- FreeTemp(rl_src.reg.GetReg());
- FreeTemp(rl_src.reg.GetHighReg());
+ FreeTemp(rl_src.reg);
}
void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src1,
@@ -1213,12 +1226,12 @@
// Get one of the source operands into temporary register.
rl_src1 = LoadValueWide(rl_src1, kCoreReg);
- if (IsTemp(rl_src1.reg.GetReg()) && IsTemp(rl_src1.reg.GetHighReg())) {
+ if (IsTemp(rl_src1.reg.GetLowReg()) && IsTemp(rl_src1.reg.GetHighReg())) {
GenLongRegOrMemOp(rl_src1, rl_src2, op);
} else if (is_commutative) {
rl_src2 = LoadValueWide(rl_src2, kCoreReg);
// We need at least one of them to be a temporary.
- if (!(IsTemp(rl_src2.reg.GetReg()) && IsTemp(rl_src2.reg.GetHighReg()))) {
+ if (!(IsTemp(rl_src2.reg.GetLowReg()) && IsTemp(rl_src2.reg.GetHighReg()))) {
rl_src1 = ForceTempWide(rl_src1);
GenLongRegOrMemOp(rl_src1, rl_src2, op);
} else {
@@ -1264,15 +1277,15 @@
rl_src = LoadValueWide(rl_src, kCoreReg);
RegLocation rl_result = ForceTempWide(rl_src);
if (((rl_dest.location == kLocPhysReg) && (rl_src.location == kLocPhysReg)) &&
- ((rl_dest.reg.GetReg() == rl_src.reg.GetHighReg()))) {
+ ((rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()))) {
// The registers are the same, so we would clobber it before the use.
- int temp_reg = AllocTemp();
- OpRegCopy(temp_reg, rl_result.reg.GetReg());
- rl_result.reg.SetHighReg(temp_reg);
+ RegStorage temp_reg = AllocTemp();
+ OpRegCopy(temp_reg, rl_result.reg);
+ rl_result.reg.SetHighReg(temp_reg.GetReg());
}
- OpRegReg(kOpNeg, rl_result.reg.GetReg(), rl_result.reg.GetReg()); // rLow = -rLow
- OpRegImm(kOpAdc, rl_result.reg.GetHighReg(), 0); // rHigh = rHigh + CF
- OpRegReg(kOpNeg, rl_result.reg.GetHighReg(), rl_result.reg.GetHighReg()); // rHigh = -rHigh
+ OpRegReg(kOpNeg, rl_result.reg.GetLow(), rl_result.reg.GetLow()); // rLow = -rLow
+ OpRegImm(kOpAdc, rl_result.reg.GetHigh(), 0); // rHigh = rHigh + CF
+ OpRegReg(kOpNeg, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); // rHigh = -rHigh
StoreValueWide(rl_dest, rl_result);
}
@@ -1314,30 +1327,28 @@
// If index is constant, just fold it into the data offset
data_offset += constant_index_value << scale;
// treat as non array below
- rl_index.reg = RegStorage(RegStorage::k32BitSolo, INVALID_REG);
+ rl_index.reg = RegStorage::InvalidReg();
}
/* null object? */
- GenNullCheck(rl_array.reg.GetReg(), opt_flags);
+ GenNullCheck(rl_array.reg, opt_flags);
if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) {
if (constant_index) {
- GenMemImmedCheck(kCondLs, rl_array.reg.GetReg(), len_offset,
+ GenMemImmedCheck(kCondLs, rl_array.reg, len_offset,
constant_index_value, kThrowConstantArrayBounds);
} else {
- GenRegMemCheck(kCondUge, rl_index.reg.GetReg(), rl_array.reg.GetReg(),
- len_offset, kThrowArrayBounds);
+ GenRegMemCheck(kCondUge, rl_index.reg, rl_array.reg, len_offset, kThrowArrayBounds);
}
}
rl_result = EvalLoc(rl_dest, reg_class, true);
if ((size == kLong) || (size == kDouble)) {
- LoadBaseIndexedDisp(rl_array.reg.GetReg(), rl_index.reg.GetReg(), scale, data_offset, rl_result.reg.GetReg(),
- rl_result.reg.GetHighReg(), size, INVALID_SREG);
+ LoadBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_result.reg.GetLow(),
+ rl_result.reg.GetHigh(), size, INVALID_SREG);
StoreValueWide(rl_dest, rl_result);
} else {
- LoadBaseIndexedDisp(rl_array.reg.GetReg(), rl_index.reg.GetReg(), scale,
- data_offset, rl_result.reg.GetReg(), INVALID_REG, size,
- INVALID_SREG);
+ LoadBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_result.reg,
+ RegStorage::InvalidReg(), size, INVALID_SREG);
StoreValue(rl_dest, rl_result);
}
}
@@ -1368,19 +1379,18 @@
constant_index_value = mir_graph_->ConstantValue(rl_index);
data_offset += constant_index_value << scale;
// treat as non array below
- rl_index.reg = RegStorage(RegStorage::k32BitSolo, INVALID_REG);
+ rl_index.reg = RegStorage::InvalidReg();
}
/* null object? */
- GenNullCheck(rl_array.reg.GetReg(), opt_flags);
+ GenNullCheck(rl_array.reg, opt_flags);
if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) {
if (constant_index) {
- GenMemImmedCheck(kCondLs, rl_array.reg.GetReg(), len_offset,
+ GenMemImmedCheck(kCondLs, rl_array.reg, len_offset,
constant_index_value, kThrowConstantArrayBounds);
} else {
- GenRegMemCheck(kCondUge, rl_index.reg.GetReg(), rl_array.reg.GetReg(),
- len_offset, kThrowArrayBounds);
+ GenRegMemCheck(kCondUge, rl_index.reg, rl_array.reg, len_offset, kThrowArrayBounds);
}
}
if ((size == kLong) || (size == kDouble)) {
@@ -1390,20 +1400,25 @@
}
// If the src reg can't be byte accessed, move it to a temp first.
if ((size == kSignedByte || size == kUnsignedByte) && rl_src.reg.GetReg() >= 4) {
- int temp = AllocTemp();
- OpRegCopy(temp, rl_src.reg.GetReg());
- StoreBaseIndexedDisp(rl_array.reg.GetReg(), rl_index.reg.GetReg(), scale, data_offset, temp,
- INVALID_REG, size, INVALID_SREG);
+ RegStorage temp = AllocTemp();
+ OpRegCopy(temp, rl_src.reg);
+ StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, temp,
+ RegStorage::InvalidReg(), size, INVALID_SREG);
} else {
- StoreBaseIndexedDisp(rl_array.reg.GetReg(), rl_index.reg.GetReg(), scale, data_offset, rl_src.reg.GetReg(),
- rl_src.wide ? rl_src.reg.GetHighReg() : INVALID_REG, size, INVALID_SREG);
+ if (rl_src.wide) {
+ StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_src.reg.GetLow(),
+ rl_src.reg.GetHigh(), size, INVALID_SREG);
+ } else {
+ StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_src.reg,
+ RegStorage::InvalidReg(), size, INVALID_SREG);
+ }
}
if (card_mark) {
// Free rl_index if its a temp. Ensures there are 2 free regs for card mark.
if (!constant_index) {
FreeTemp(rl_index.reg.GetReg());
}
- MarkGCCard(rl_src.reg.GetReg(), rl_array.reg.GetReg());
+ MarkGCCard(rl_src.reg, rl_array.reg);
}
}
@@ -1415,51 +1430,51 @@
case Instruction::SHL_LONG_2ADDR:
DCHECK_NE(shift_amount, 1); // Prevent a double store from happening.
if (shift_amount == 32) {
- OpRegCopy(rl_result.reg.GetHighReg(), rl_src.reg.GetReg());
- LoadConstant(rl_result.reg.GetReg(), 0);
+ OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow());
+ LoadConstant(rl_result.reg.GetLow(), 0);
} else if (shift_amount > 31) {
- OpRegCopy(rl_result.reg.GetHighReg(), rl_src.reg.GetReg());
+ OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow());
FreeTemp(rl_src.reg.GetHighReg());
NewLIR2(kX86Sal32RI, rl_result.reg.GetHighReg(), shift_amount - 32);
- LoadConstant(rl_result.reg.GetReg(), 0);
+ LoadConstant(rl_result.reg.GetLow(), 0);
} else {
- OpRegCopy(rl_result.reg.GetReg(), rl_src.reg.GetReg());
- OpRegCopy(rl_result.reg.GetHighReg(), rl_src.reg.GetHighReg());
- NewLIR3(kX86Shld32RRI, rl_result.reg.GetHighReg(), rl_result.reg.GetReg(), shift_amount);
- NewLIR2(kX86Sal32RI, rl_result.reg.GetReg(), shift_amount);
+ OpRegCopy(rl_result.reg, rl_src.reg);
+ OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh());
+ NewLIR3(kX86Shld32RRI, rl_result.reg.GetHighReg(), rl_result.reg.GetLowReg(), shift_amount);
+ NewLIR2(kX86Sal32RI, rl_result.reg.GetLowReg(), shift_amount);
}
break;
case Instruction::SHR_LONG:
case Instruction::SHR_LONG_2ADDR:
if (shift_amount == 32) {
- OpRegCopy(rl_result.reg.GetReg(), rl_src.reg.GetHighReg());
- OpRegCopy(rl_result.reg.GetHighReg(), rl_src.reg.GetHighReg());
+ OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh());
+ OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh());
NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31);
} else if (shift_amount > 31) {
- OpRegCopy(rl_result.reg.GetReg(), rl_src.reg.GetHighReg());
- OpRegCopy(rl_result.reg.GetHighReg(), rl_src.reg.GetHighReg());
- NewLIR2(kX86Sar32RI, rl_result.reg.GetReg(), shift_amount - 32);
+ OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh());
+ OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh());
+ NewLIR2(kX86Sar32RI, rl_result.reg.GetLowReg(), shift_amount - 32);
NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31);
} else {
- OpRegCopy(rl_result.reg.GetReg(), rl_src.reg.GetReg());
- OpRegCopy(rl_result.reg.GetHighReg(), rl_src.reg.GetHighReg());
- NewLIR3(kX86Shrd32RRI, rl_result.reg.GetReg(), rl_result.reg.GetHighReg(), shift_amount);
+ OpRegCopy(rl_result.reg, rl_src.reg);
+ OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh());
+ NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), shift_amount);
NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), shift_amount);
}
break;
case Instruction::USHR_LONG:
case Instruction::USHR_LONG_2ADDR:
if (shift_amount == 32) {
- OpRegCopy(rl_result.reg.GetReg(), rl_src.reg.GetHighReg());
- LoadConstant(rl_result.reg.GetHighReg(), 0);
+ OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh());
+ LoadConstant(rl_result.reg.GetHigh(), 0);
} else if (shift_amount > 31) {
- OpRegCopy(rl_result.reg.GetReg(), rl_src.reg.GetHighReg());
- NewLIR2(kX86Shr32RI, rl_result.reg.GetReg(), shift_amount - 32);
- LoadConstant(rl_result.reg.GetHighReg(), 0);
+ OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh());
+ NewLIR2(kX86Shr32RI, rl_result.reg.GetLowReg(), shift_amount - 32);
+ LoadConstant(rl_result.reg.GetHigh(), 0);
} else {
- OpRegCopy(rl_result.reg.GetReg(), rl_src.reg.GetReg());
- OpRegCopy(rl_result.reg.GetHighReg(), rl_src.reg.GetHighReg());
- NewLIR3(kX86Shrd32RRI, rl_result.reg.GetReg(), rl_result.reg.GetHighReg(), shift_amount);
+ OpRegCopy(rl_result.reg, rl_src.reg);
+ OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh());
+ NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), shift_amount);
NewLIR2(kX86Shr32RI, rl_result.reg.GetHighReg(), shift_amount);
}
break;
@@ -1597,7 +1612,7 @@
int32_t value) {
bool in_mem = loc.location != kLocPhysReg;
bool byte_imm = IS_SIMM8(value);
- DCHECK(in_mem || !IsFpReg(loc.reg.GetReg()));
+ DCHECK(in_mem || !IsFpReg(loc.reg));
switch (op) {
case Instruction::ADD_LONG:
case Instruction::ADD_LONG_2ADDR:
@@ -1657,18 +1672,18 @@
// Can we just do this into memory?
if ((rl_dest.location == kLocDalvikFrame) ||
(rl_dest.location == kLocCompilerTemp)) {
- int rBase = TargetReg(kSp);
+ int r_base = TargetReg(kSp).GetReg();
int displacement = SRegOffset(rl_dest.s_reg_low);
if (!IsNoOp(op, val_lo)) {
X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo);
- LIR *lir = NewLIR3(x86op, rBase, displacement + LOWORD_OFFSET, val_lo);
+ LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val_lo);
AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2,
false /* is_load */, true /* is64bit */);
}
if (!IsNoOp(op, val_hi)) {
X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi);
- LIR *lir = NewLIR3(x86op, rBase, displacement + HIWORD_OFFSET, val_hi);
+ LIR *lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, val_hi);
AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2,
false /* is_load */, true /* is64bit */);
}
@@ -1677,11 +1692,11 @@
RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true);
DCHECK_EQ(rl_result.location, kLocPhysReg);
- DCHECK(!IsFpReg(rl_result.reg.GetReg()));
+ DCHECK(!IsFpReg(rl_result.reg));
if (!IsNoOp(op, val_lo)) {
X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo);
- NewLIR2(x86op, rl_result.reg.GetReg(), val_lo);
+ NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo);
}
if (!IsNoOp(op, val_hi)) {
X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi);
@@ -1701,11 +1716,12 @@
// Can we do this directly into the destination registers?
if (rl_dest.location == kLocPhysReg && rl_src1.location == kLocPhysReg &&
- rl_dest.reg.GetReg() == rl_src1.reg.GetReg() && rl_dest.reg.GetHighReg() == rl_src1.reg.GetHighReg() &&
- !IsFpReg(rl_dest.reg.GetReg())) {
+ rl_dest.reg.GetLowReg() == rl_src1.reg.GetLowReg() &&
+ rl_dest.reg.GetHighReg() == rl_src1.reg.GetHighReg() &&
+ !IsFpReg(rl_dest.reg)) {
if (!IsNoOp(op, val_lo)) {
X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo);
- NewLIR2(x86op, rl_dest.reg.GetReg(), val_lo);
+ NewLIR2(x86op, rl_dest.reg.GetLowReg(), val_lo);
}
if (!IsNoOp(op, val_hi)) {
X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi);
@@ -1723,7 +1739,7 @@
RegLocation rl_result = ForceTempWide(rl_src1);
if (!IsNoOp(op, val_lo)) {
X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo);
- NewLIR2(x86op, rl_result.reg.GetReg(), val_lo);
+ NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo);
}
if (!IsNoOp(op, val_hi)) {
X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi);
@@ -1739,19 +1755,19 @@
RegLocation rl_dest, RegLocation rl_src) {
RegLocation object = LoadValue(rl_src, kCoreReg);
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
- int result_reg = rl_result.reg.GetReg();
+ RegStorage result_reg = rl_result.reg;
// SETcc only works with EAX..EDX.
- if (result_reg == object.reg.GetReg() || result_reg >= 4) {
+ if (result_reg == object.reg || result_reg.GetReg() >= 4) {
result_reg = AllocTypedTemp(false, kCoreReg);
- DCHECK_LT(result_reg, 4);
+ DCHECK_LT(result_reg.GetReg(), 4);
}
// Assume that there is no match.
LoadConstant(result_reg, 0);
- LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg.GetReg(), 0, NULL);
+ LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL);
- int check_class = AllocTypedTemp(false, kCoreReg);
+ RegStorage check_class = AllocTypedTemp(false, kCoreReg);
// If Method* is already in a register, we can save a copy.
RegLocation rl_method = mir_graph_->GetMethodLoc();
@@ -1760,24 +1776,20 @@
if (rl_method.location == kLocPhysReg) {
if (use_declaring_class) {
- LoadWordDisp(rl_method.reg.GetReg(),
- mirror::ArtMethod::DeclaringClassOffset().Int32Value(),
+ LoadWordDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(),
check_class);
} else {
- LoadWordDisp(rl_method.reg.GetReg(),
- mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(),
+ LoadWordDisp(rl_method.reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(),
check_class);
LoadWordDisp(check_class, offset_of_type, check_class);
}
} else {
LoadCurrMethodDirect(check_class);
if (use_declaring_class) {
- LoadWordDisp(check_class,
- mirror::ArtMethod::DeclaringClassOffset().Int32Value(),
+ LoadWordDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(),
check_class);
} else {
- LoadWordDisp(check_class,
- mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(),
+ LoadWordDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(),
check_class);
LoadWordDisp(check_class, offset_of_type, check_class);
}
@@ -1785,17 +1797,16 @@
// Compare the computed class to the class in the object.
DCHECK_EQ(object.location, kLocPhysReg);
- OpRegMem(kOpCmp, check_class, object.reg.GetReg(),
- mirror::Object::ClassOffset().Int32Value());
+ OpRegMem(kOpCmp, check_class, object.reg, mirror::Object::ClassOffset().Int32Value());
// Set the low byte of the result to 0 or 1 from the compare condition code.
- NewLIR2(kX86Set8R, result_reg, kX86CondEq);
+ NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondEq);
LIR* target = NewLIR0(kPseudoTargetLabel);
null_branchover->target = target;
FreeTemp(check_class);
if (IsTemp(result_reg)) {
- OpRegCopy(rl_result.reg.GetReg(), result_reg);
+ OpRegCopy(rl_result.reg, result_reg);
FreeTemp(result_reg);
}
StoreValue(rl_dest, rl_result);
@@ -1810,7 +1821,7 @@
// May generate a call - use explicit registers.
LockCallTemps();
LoadCurrMethodDirect(TargetReg(kArg1)); // kArg1 gets current Method*.
- int class_reg = TargetReg(kArg2); // kArg2 will hold the Class*.
+ RegStorage class_reg = TargetReg(kArg2); // kArg2 will hold the Class*.
// Reference must end up in kArg0.
if (needs_access_check) {
// Check we have access to type_idx and if not throw IllegalAccessError,
@@ -1821,13 +1832,13 @@
LoadValueDirectFixed(rl_src, TargetReg(kArg0));
} else if (use_declaring_class) {
LoadValueDirectFixed(rl_src, TargetReg(kArg0));
- LoadWordDisp(TargetReg(kArg1),
- mirror::ArtMethod::DeclaringClassOffset().Int32Value(), class_reg);
+ LoadWordDisp(TargetReg(kArg1), mirror::ArtMethod::DeclaringClassOffset().Int32Value(),
+ class_reg);
} else {
// Load dex cache entry into class_reg (kArg2).
LoadValueDirectFixed(rl_src, TargetReg(kArg0));
- LoadWordDisp(TargetReg(kArg1),
- mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), class_reg);
+ LoadWordDisp(TargetReg(kArg1), mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(),
+ class_reg);
int32_t offset_of_type =
mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + (sizeof(mirror::Class*)
* type_idx);
@@ -1860,13 +1871,13 @@
LIR* branchover = nullptr;
if (type_known_final) {
// Ensure top 3 bytes of result are 0.
- LoadConstant(rl_result.reg.GetReg(), 0);
+ LoadConstant(rl_result.reg, 0);
OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2));
// Set the low byte of the result to 0 or 1 from the compare condition code.
NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondEq);
} else {
if (!type_known_abstract) {
- LoadConstant(rl_result.reg.GetReg(), 1); // Assume result succeeds.
+ LoadConstant(rl_result.reg, 1); // Assume result succeeds.
branchover = OpCmpBranch(kCondEq, TargetReg(kArg1), TargetReg(kArg2), NULL);
}
OpRegCopy(TargetReg(kArg0), TargetReg(kArg2));
@@ -1994,11 +2005,11 @@
rl_lhs = LoadValue(rl_lhs, kCoreReg);
rl_result = UpdateLoc(rl_dest);
rl_result = EvalLoc(rl_dest, kCoreReg, true);
- OpRegReg(op, rl_result.reg.GetReg(), rl_lhs.reg.GetReg());
+ OpRegReg(op, rl_result.reg, rl_lhs.reg);
} else {
if (shift_op) {
// X86 doesn't require masking and must use ECX.
- int t_reg = TargetReg(kCount); // rCX
+ RegStorage t_reg = TargetReg(kCount); // rCX
LoadValueDirectFixed(rl_rhs, t_reg);
if (is_two_addr) {
// Can we do this directly into memory?
@@ -2006,12 +2017,12 @@
rl_rhs = LoadValue(rl_rhs, kCoreReg);
if (rl_result.location != kLocPhysReg) {
// Okay, we can do this into memory
- OpMemReg(op, rl_result, t_reg);
+ OpMemReg(op, rl_result, t_reg.GetReg());
FreeTemp(t_reg);
return;
} else if (!IsFpReg(rl_result.reg.GetReg())) {
// Can do this directly into the result register
- OpRegReg(op, rl_result.reg.GetReg(), t_reg);
+ OpRegReg(op, rl_result.reg, t_reg);
FreeTemp(t_reg);
StoreFinalValue(rl_dest, rl_result);
return;
@@ -2020,7 +2031,7 @@
// Three address form, or we can't do directly.
rl_lhs = LoadValue(rl_lhs, kCoreReg);
rl_result = EvalLoc(rl_dest, kCoreReg, true);
- OpRegRegReg(op, rl_result.reg.GetReg(), rl_lhs.reg.GetReg(), t_reg);
+ OpRegRegReg(op, rl_result.reg, rl_lhs.reg, t_reg);
FreeTemp(t_reg);
} else {
// Multiply is 3 operand only (sort of).
@@ -2031,11 +2042,11 @@
// Can we do this from memory directly?
rl_rhs = UpdateLoc(rl_rhs);
if (rl_rhs.location != kLocPhysReg) {
- OpRegMem(op, rl_result.reg.GetReg(), rl_rhs);
+ OpRegMem(op, rl_result.reg, rl_rhs);
StoreFinalValue(rl_dest, rl_result);
return;
- } else if (!IsFpReg(rl_rhs.reg.GetReg())) {
- OpRegReg(op, rl_result.reg.GetReg(), rl_rhs.reg.GetReg());
+ } else if (!IsFpReg(rl_rhs.reg)) {
+ OpRegReg(op, rl_result.reg, rl_rhs.reg);
StoreFinalValue(rl_dest, rl_result);
return;
}
@@ -2045,15 +2056,15 @@
// Okay, we can do this into memory.
OpMemReg(op, rl_result, rl_rhs.reg.GetReg());
return;
- } else if (!IsFpReg(rl_result.reg.GetReg())) {
+ } else if (!IsFpReg(rl_result.reg)) {
// Can do this directly into the result register.
- OpRegReg(op, rl_result.reg.GetReg(), rl_rhs.reg.GetReg());
+ OpRegReg(op, rl_result.reg, rl_rhs.reg);
StoreFinalValue(rl_dest, rl_result);
return;
} else {
rl_lhs = LoadValue(rl_lhs, kCoreReg);
rl_result = EvalLoc(rl_dest, kCoreReg, true);
- OpRegRegReg(op, rl_result.reg.GetReg(), rl_lhs.reg.GetReg(), rl_rhs.reg.GetReg());
+ OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg);
}
} else {
// Try to use reg/memory instructions.
@@ -2065,7 +2076,7 @@
rl_lhs = LoadValue(rl_lhs, kCoreReg);
rl_rhs = LoadValue(rl_rhs, kCoreReg);
rl_result = EvalLoc(rl_dest, kCoreReg, true);
- OpRegRegReg(op, rl_result.reg.GetReg(), rl_lhs.reg.GetReg(), rl_rhs.reg.GetReg());
+ OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg);
} else {
// We can optimize by moving to result and using memory operands.
if (rl_rhs.location != kLocPhysReg) {
@@ -2078,29 +2089,29 @@
rl_result = EvalLoc(rl_dest, kCoreReg, true);
} else {
rl_result = EvalLoc(rl_dest, kCoreReg, true);
- LoadValueDirect(rl_lhs, rl_result.reg.GetReg());
+ LoadValueDirect(rl_lhs, rl_result.reg);
}
- OpRegMem(op, rl_result.reg.GetReg(), rl_rhs);
+ OpRegMem(op, rl_result.reg, rl_rhs);
} else if (rl_lhs.location != kLocPhysReg) {
// RHS is in a register; LHS is in memory.
if (op != kOpSub) {
// Force RHS into result and operate on memory.
rl_result = EvalLoc(rl_dest, kCoreReg, true);
- OpRegCopy(rl_result.reg.GetReg(), rl_rhs.reg.GetReg());
- OpRegMem(op, rl_result.reg.GetReg(), rl_lhs);
+ OpRegCopy(rl_result.reg, rl_rhs.reg);
+ OpRegMem(op, rl_result.reg, rl_lhs);
} else {
// Subtraction isn't commutative.
rl_lhs = LoadValue(rl_lhs, kCoreReg);
rl_rhs = LoadValue(rl_rhs, kCoreReg);
rl_result = EvalLoc(rl_dest, kCoreReg, true);
- OpRegRegReg(op, rl_result.reg.GetReg(), rl_lhs.reg.GetReg(), rl_rhs.reg.GetReg());
+ OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg);
}
} else {
// Both are in registers.
rl_lhs = LoadValue(rl_lhs, kCoreReg);
rl_rhs = LoadValue(rl_rhs, kCoreReg);
rl_result = EvalLoc(rl_dest, kCoreReg, true);
- OpRegRegReg(op, rl_result.reg.GetReg(), rl_lhs.reg.GetReg(), rl_rhs.reg.GetReg());
+ OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg);
}
}
}
diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc
index 9588b17..da64250 100644
--- a/compiler/dex/quick/x86/target_x86.cc
+++ b/compiler/dex/quick/x86/target_x86.cc
@@ -65,44 +65,44 @@
}
// Return a target-dependent special register.
-int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) {
- int res = INVALID_REG;
+RegStorage X86Mir2Lir::TargetReg(SpecialTargetRegister reg) {
+ int res_reg = RegStorage::kInvalidRegVal;
switch (reg) {
- case kSelf: res = rX86_SELF; break;
- case kSuspend: res = rX86_SUSPEND; break;
- case kLr: res = rX86_LR; break;
- case kPc: res = rX86_PC; break;
- case kSp: res = rX86_SP; break;
- case kArg0: res = rX86_ARG0; break;
- case kArg1: res = rX86_ARG1; break;
- case kArg2: res = rX86_ARG2; break;
- case kArg3: res = rX86_ARG3; break;
- case kFArg0: res = rX86_FARG0; break;
- case kFArg1: res = rX86_FARG1; break;
- case kFArg2: res = rX86_FARG2; break;
- case kFArg3: res = rX86_FARG3; break;
- case kRet0: res = rX86_RET0; break;
- case kRet1: res = rX86_RET1; break;
- case kInvokeTgt: res = rX86_INVOKE_TGT; break;
- case kHiddenArg: res = rAX; break;
- case kHiddenFpArg: res = fr0; break;
- case kCount: res = rX86_COUNT; break;
+ case kSelf: res_reg = rX86_SELF; break;
+ case kSuspend: res_reg = rX86_SUSPEND; break;
+ case kLr: res_reg = rX86_LR; break;
+ case kPc: res_reg = rX86_PC; break;
+ case kSp: res_reg = rX86_SP; break;
+ case kArg0: res_reg = rX86_ARG0; break;
+ case kArg1: res_reg = rX86_ARG1; break;
+ case kArg2: res_reg = rX86_ARG2; break;
+ case kArg3: res_reg = rX86_ARG3; break;
+ case kFArg0: res_reg = rX86_FARG0; break;
+ case kFArg1: res_reg = rX86_FARG1; break;
+ case kFArg2: res_reg = rX86_FARG2; break;
+ case kFArg3: res_reg = rX86_FARG3; break;
+ case kRet0: res_reg = rX86_RET0; break;
+ case kRet1: res_reg = rX86_RET1; break;
+ case kInvokeTgt: res_reg = rX86_INVOKE_TGT; break;
+ case kHiddenArg: res_reg = rAX; break;
+ case kHiddenFpArg: res_reg = fr0; break;
+ case kCount: res_reg = rX86_COUNT; break;
}
- return res;
+ return RegStorage::Solo32(res_reg);
}
-int X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) {
+RegStorage X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) {
// For the 32-bit internal ABI, the first 3 arguments are passed in registers.
// TODO: This is not 64-bit compliant and depends on new internal ABI.
switch (arg_num) {
case 0:
- return rX86_ARG1;
+ return rs_rX86_ARG1;
case 1:
- return rX86_ARG2;
+ return rs_rX86_ARG2;
case 2:
- return rX86_ARG3;
+ return rs_rX86_ARG3;
default:
- return INVALID_REG;
+ return RegStorage::InvalidReg();
}
}
@@ -346,9 +346,9 @@
#endif
}
-void X86Mir2Lir::FlushRegWide(int reg1, int reg2) {
- RegisterInfo* info1 = GetRegInfo(reg1);
- RegisterInfo* info2 = GetRegInfo(reg2);
+void X86Mir2Lir::FlushRegWide(RegStorage reg) {
+ RegisterInfo* info1 = GetRegInfo(reg.GetLowReg());
+ RegisterInfo* info2 = GetRegInfo(reg.GetHighReg());
DCHECK(info1 && info2 && info1->pair && info2->pair &&
(info1->partner == info2->reg) &&
(info2->partner == info1->reg));
@@ -363,16 +363,18 @@
if (mir_graph_->SRegToVReg(info2->s_reg) < mir_graph_->SRegToVReg(info1->s_reg))
info1 = info2;
int v_reg = mir_graph_->SRegToVReg(info1->s_reg);
- StoreBaseDispWide(rX86_SP, VRegOffset(v_reg), info1->reg, info1->partner);
+ StoreBaseDispWide(rs_rX86_SP, VRegOffset(v_reg),
+ RegStorage(RegStorage::k64BitPair, info1->reg, info1->partner));
}
}
-void X86Mir2Lir::FlushReg(int reg) {
- RegisterInfo* info = GetRegInfo(reg);
+void X86Mir2Lir::FlushReg(RegStorage reg) {
+ DCHECK(!reg.IsPair());
+ RegisterInfo* info = GetRegInfo(reg.GetReg());
if (info->live && info->dirty) {
info->dirty = false;
int v_reg = mir_graph_->SRegToVReg(info->s_reg);
- StoreBaseDisp(rX86_SP, VRegOffset(v_reg), reg, kWord);
+ StoreBaseDisp(rs_rX86_SP, VRegOffset(v_reg), reg, kWord);
}
}
@@ -381,6 +383,10 @@
return X86_FPREG(reg);
}
+bool X86Mir2Lir::IsFpReg(RegStorage reg) {
+ return IsFpReg(reg.IsPair() ? reg.GetLowReg() : reg.GetReg());
+}
+
/* Clobber all regs that might be used by an external C call */
void X86Mir2Lir::ClobberCallerSave() {
Clobber(rAX);
@@ -391,13 +397,13 @@
RegLocation X86Mir2Lir::GetReturnWideAlt() {
RegLocation res = LocCReturnWide();
- CHECK(res.reg.GetReg() == rAX);
+ CHECK(res.reg.GetLowReg() == rAX);
CHECK(res.reg.GetHighReg() == rDX);
Clobber(rAX);
Clobber(rDX);
MarkInUse(rAX);
MarkInUse(rDX);
- MarkPair(res.reg.GetReg(), res.reg.GetHighReg());
+ MarkPair(res.reg.GetLowReg(), res.reg.GetHighReg());
return res;
}
@@ -478,21 +484,15 @@
// Alloc a pair of core registers, or a double.
RegStorage X86Mir2Lir::AllocTypedTempWide(bool fp_hint, int reg_class) {
- int high_reg;
- int low_reg;
-
if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
- low_reg = AllocTempDouble();
- high_reg = low_reg; // only one allocated!
- // TODO: take advantage of 64-bit notation.
- return RegStorage(RegStorage::k64BitPair, low_reg, high_reg);
+ return AllocTempDouble();
}
- low_reg = AllocTemp();
- high_reg = AllocTemp();
- return RegStorage(RegStorage::k64BitPair, low_reg, high_reg);
+ RegStorage low_reg = AllocTemp();
+ RegStorage high_reg = AllocTemp();
+ return RegStorage::MakeRegPair(low_reg, high_reg);
}
-int X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) {
+RegStorage X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) {
if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
return AllocTempFloat();
}
@@ -530,13 +530,18 @@
}
}
-void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep,
- RegLocation rl_free) {
- if ((rl_free.reg.GetReg() != rl_keep.reg.GetReg()) && (rl_free.reg.GetReg() != rl_keep.reg.GetHighReg()) &&
- (rl_free.reg.GetHighReg() != rl_keep.reg.GetReg()) && (rl_free.reg.GetHighReg() != rl_keep.reg.GetHighReg())) {
+void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) {
+ DCHECK(rl_keep.wide);
+ DCHECK(rl_free.wide);
+ int free_low = rl_free.reg.GetLowReg();
+ int free_high = rl_free.reg.GetHighReg();
+ int keep_low = rl_keep.reg.GetLowReg();
+ int keep_high = rl_keep.reg.GetHighReg();
+ if ((free_low != keep_low) && (free_low != keep_high) &&
+ (free_high != keep_low) && (free_high != keep_high)) {
// No overlap, free both
- FreeTemp(rl_free.reg.GetReg());
- FreeTemp(rl_free.reg.GetHighReg());
+ FreeTemp(free_low);
+ FreeTemp(free_high);
}
}
@@ -549,7 +554,7 @@
int offset = frame_size_ - (4 * num_core_spills_);
for (int reg = 0; mask; mask >>= 1, reg++) {
if (mask & 0x1) {
- StoreWordDisp(rX86_SP, offset, reg);
+ StoreWordDisp(rs_rX86_SP, offset, RegStorage::Solo32(reg));
offset += 4;
}
}
@@ -564,7 +569,7 @@
int offset = frame_size_ - (4 * num_core_spills_);
for (int reg = 0; mask; mask >>= 1, reg++) {
if (mask & 0x1) {
- LoadWordDisp(rX86_SP, offset, reg);
+ LoadWordDisp(rs_rX86_SP, offset, RegStorage::Solo32(reg));
offset += 4;
}
}
@@ -596,9 +601,9 @@
}
// Not used in x86
-int X86Mir2Lir::LoadHelper(ThreadOffset offset) {
+RegStorage X86Mir2Lir::LoadHelper(ThreadOffset offset) {
LOG(FATAL) << "Unexpected use of LoadHelper in x86";
- return INVALID_REG;
+ return RegStorage::InvalidReg();
}
LIR* X86Mir2Lir::CheckSuspendUsingLoad() {
@@ -650,7 +655,7 @@
loc.vec_len = kVectorLength8;
// TODO: use k64BitVector
loc.reg = RegStorage(RegStorage::k64BitPair, info_lo->reg, info_lo->reg);
- DCHECK(IsFpReg(loc.reg.GetReg()));
+ DCHECK(IsFpReg(loc.reg.GetLowReg()));
return loc;
}
// We can't easily reuse; clobber and free any overlaps.
@@ -682,8 +687,8 @@
// Can reuse - update the register usage info
loc.reg = RegStorage(RegStorage::k64BitPair, info_lo->reg, info_hi->reg);
loc.location = kLocPhysReg;
- MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg());
- DCHECK(!IsFpReg(loc.reg.GetReg()) || ((loc.reg.GetReg() & 0x1) == 0));
+ MarkPair(loc.reg.GetLowReg(), loc.reg.GetHighReg());
+ DCHECK(!IsFpReg(loc.reg.GetLowReg()) || ((loc.reg.GetLowReg() & 0x1) == 0));
return loc;
}
// Can't easily reuse - clobber and free any overlaps
@@ -707,44 +712,37 @@
// TODO: Reunify with common code after 'pair mess' has been fixed
RegLocation X86Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) {
DCHECK(loc.wide);
- int32_t low_reg;
- int32_t high_reg;
loc = UpdateLocWide(loc);
/* If it is already in a register, we can assume proper form. Is it the right reg class? */
if (loc.location == kLocPhysReg) {
- DCHECK_EQ(IsFpReg(loc.reg.GetReg()), loc.IsVectorScalar());
- if (!RegClassMatches(reg_class, loc.reg.GetReg())) {
+ DCHECK_EQ(IsFpReg(loc.reg.GetLowReg()), loc.IsVectorScalar());
+ if (!RegClassMatches(reg_class, loc.reg)) {
/* It is the wrong register class. Reallocate and copy. */
- if (!IsFpReg(loc.reg.GetReg())) {
+ if (!IsFpReg(loc.reg.GetLowReg())) {
// We want this in a FP reg, and it is in core registers.
DCHECK(reg_class != kCoreReg);
// Allocate this into any FP reg, and mark it with the right size.
- low_reg = AllocTypedTemp(true, reg_class);
- OpVectorRegCopyWide(low_reg, loc.reg.GetReg(), loc.reg.GetHighReg());
- CopyRegInfo(low_reg, loc.reg.GetReg());
- Clobber(loc.reg.GetReg());
- Clobber(loc.reg.GetHighReg());
+ int32_t low_reg = AllocTypedTemp(true, reg_class).GetReg();
+ OpVectorRegCopyWide(low_reg, loc.reg.GetLowReg(), loc.reg.GetHighReg());
+ CopyRegInfo(low_reg, loc.reg.GetLowReg());
+ Clobber(loc.reg);
loc.reg.SetReg(low_reg);
loc.reg.SetHighReg(low_reg); // Play nice with existing code.
loc.vec_len = kVectorLength8;
} else {
// The value is in a FP register, and we want it in a pair of core registers.
DCHECK_EQ(reg_class, kCoreReg);
- DCHECK_EQ(loc.reg.GetReg(), loc.reg.GetHighReg());
+ DCHECK_EQ(loc.reg.GetLowReg(), loc.reg.GetHighReg());
RegStorage new_regs = AllocTypedTempWide(false, kCoreReg); // Force to core registers.
- low_reg = new_regs.GetReg();
- high_reg = new_regs.GetHighReg();
- DCHECK_NE(low_reg, high_reg);
- OpRegCopyWide(low_reg, high_reg, loc.reg.GetReg(), loc.reg.GetHighReg());
- CopyRegInfo(low_reg, loc.reg.GetReg());
- CopyRegInfo(high_reg, loc.reg.GetHighReg());
- Clobber(loc.reg.GetReg());
- Clobber(loc.reg.GetHighReg());
+ OpRegCopyWide(new_regs, loc.reg);
+ CopyRegInfo(new_regs.GetLowReg(), loc.reg.GetLowReg());
+ CopyRegInfo(new_regs.GetHighReg(), loc.reg.GetHighReg());
+ Clobber(loc.reg);
loc.reg = new_regs;
- MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg());
- DCHECK(!IsFpReg(loc.reg.GetReg()) || ((loc.reg.GetReg() & 0x1) == 0));
+ MarkPair(loc.reg.GetLowReg(), loc.reg.GetHighReg());
+ DCHECK(!IsFpReg(loc.reg.GetLowReg()) || ((loc.reg.GetLowReg() & 0x1) == 0));
}
}
return loc;
@@ -756,17 +754,17 @@
loc.reg = AllocTypedTempWide(loc.fp, reg_class);
// FIXME: take advantage of RegStorage notation.
- if (loc.reg.GetReg() == loc.reg.GetHighReg()) {
- DCHECK(IsFpReg(loc.reg.GetReg()));
+ if (loc.reg.GetLowReg() == loc.reg.GetHighReg()) {
+ DCHECK(IsFpReg(loc.reg.GetLowReg()));
loc.vec_len = kVectorLength8;
} else {
- MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg());
+ MarkPair(loc.reg.GetLowReg(), loc.reg.GetHighReg());
}
if (update) {
loc.location = kLocPhysReg;
- MarkLive(loc.reg.GetReg(), loc.s_reg_low);
- if (loc.reg.GetReg() != loc.reg.GetHighReg()) {
- MarkLive(loc.reg.GetHighReg(), GetSRegHi(loc.s_reg_low));
+ MarkLive(loc.reg.GetLow(), loc.s_reg_low);
+ if (loc.reg.GetLowReg() != loc.reg.GetHighReg()) {
+ MarkLive(loc.reg.GetHigh(), GetSRegHi(loc.s_reg_low));
}
}
return loc;
@@ -774,21 +772,19 @@
// TODO: Reunify with common code after 'pair mess' has been fixed
RegLocation X86Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) {
- int new_reg;
-
if (loc.wide)
return EvalLocWide(loc, reg_class, update);
loc = UpdateLoc(loc);
if (loc.location == kLocPhysReg) {
- if (!RegClassMatches(reg_class, loc.reg.GetReg())) {
+ if (!RegClassMatches(reg_class, loc.reg)) {
/* Wrong register class. Realloc, copy and transfer ownership. */
- new_reg = AllocTypedTemp(loc.fp, reg_class);
- OpRegCopy(new_reg, loc.reg.GetReg());
- CopyRegInfo(new_reg, loc.reg.GetReg());
- Clobber(loc.reg.GetReg());
- loc.reg.SetReg(new_reg);
+ RegStorage new_reg = AllocTypedTemp(loc.fp, reg_class);
+ OpRegCopy(new_reg, loc.reg);
+ CopyRegInfo(new_reg, loc.reg);
+ Clobber(loc.reg);
+ loc.reg = new_reg;
if (IsFpReg(loc.reg.GetReg()) && reg_class != kCoreReg)
loc.vec_len = kVectorLength4;
}
@@ -797,32 +793,34 @@
DCHECK_NE(loc.s_reg_low, INVALID_SREG);
- loc.reg = RegStorage(RegStorage::k32BitSolo, AllocTypedTemp(loc.fp, reg_class));
+ loc.reg = AllocTypedTemp(loc.fp, reg_class);
if (IsFpReg(loc.reg.GetReg()) && reg_class != kCoreReg)
loc.vec_len = kVectorLength4;
if (update) {
loc.location = kLocPhysReg;
- MarkLive(loc.reg.GetReg(), loc.s_reg_low);
+ MarkLive(loc.reg, loc.s_reg_low);
}
return loc;
}
-int X86Mir2Lir::AllocTempDouble() {
+RegStorage X86Mir2Lir::AllocTempDouble() {
// We really don't need a pair of registers.
- return AllocTempFloat();
+ // FIXME - update to double
+ int reg = AllocTempFloat().GetReg();
+ return RegStorage(RegStorage::k64BitPair, reg, reg);
}
// TODO: Reunify with common code after 'pair mess' has been fixed
void X86Mir2Lir::ResetDefLocWide(RegLocation rl) {
DCHECK(rl.wide);
- RegisterInfo* p_low = IsTemp(rl.reg.GetReg());
- if (IsFpReg(rl.reg.GetReg())) {
+ RegisterInfo* p_low = IsTemp(rl.reg.GetLowReg());
+ if (IsFpReg(rl.reg.GetLowReg())) {
// We are using only the low register.
if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) {
NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low);
}
- ResetDef(rl.reg.GetReg());
+ ResetDef(rl.reg.GetLowReg());
} else {
RegisterInfo* p_high = IsTemp(rl.reg.GetHighReg());
if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) {
@@ -832,7 +830,7 @@
if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) {
DCHECK(p_high->pair);
}
- ResetDef(rl.reg.GetReg());
+ ResetDef(rl.reg.GetLowReg());
ResetDef(rl.reg.GetHighReg());
}
}
@@ -844,13 +842,13 @@
(rl_dest.location == kLocCompilerTemp)) {
int32_t val_lo = Low32Bits(value);
int32_t val_hi = High32Bits(value);
- int rBase = TargetReg(kSp);
+ int r_base = TargetReg(kSp).GetReg();
int displacement = SRegOffset(rl_dest.s_reg_low);
- LIR * store = NewLIR3(kX86Mov32MI, rBase, displacement + LOWORD_OFFSET, val_lo);
+ LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo);
AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2,
false /* is_load */, true /* is64bit */);
- store = NewLIR3(kX86Mov32MI, rBase, displacement + HIWORD_OFFSET, val_hi);
+ store = NewLIR3(kX86Mov32MI, r_base, displacement + HIWORD_OFFSET, val_hi);
AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2,
false /* is_load */, true /* is64bit */);
return;
@@ -872,7 +870,7 @@
<< (loc.high_word ? " h" : " ")
<< (loc.home ? " H" : " ")
<< " vec_len: " << loc.vec_len
- << ", low: " << static_cast<int>(loc.reg.GetReg())
+ << ", low: " << static_cast<int>(loc.reg.GetLowReg())
<< ", high: " << static_cast<int>(loc.reg.GetHighReg())
<< ", s_reg: " << loc.s_reg_low
<< ", orig: " << loc.orig_sreg;
@@ -899,7 +897,7 @@
uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id);
// Generate the move instruction with the unique pointer and save index, dex_file, and type.
- LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg),
+ LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg).GetReg(),
static_cast<int>(target_method_id_ptr), target_method_idx,
WrapPointer(const_cast<DexFile*>(target_dex_file)), type);
AppendLIR(move);
@@ -916,7 +914,7 @@
uintptr_t ptr = reinterpret_cast<uintptr_t>(&id);
// Generate the move instruction with the unique pointer and save index and type.
- LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg),
+ LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg).GetReg(),
static_cast<int>(ptr), type_idx);
AppendLIR(move);
class_type_address_insns_.Insert(move);
@@ -1028,19 +1026,19 @@
RegLocation rl_dest = InlineTarget(info);
// Is the string non-NULL?
- LoadValueDirectFixed(rl_obj, rDX);
- GenNullCheck(rDX, info->opt_flags);
+ LoadValueDirectFixed(rl_obj, rs_rDX);
+ GenNullCheck(rs_rDX, info->opt_flags);
info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked.
// Does the character fit in 16 bits?
LIR* launchpad_branch = nullptr;
if (rl_char.is_const) {
// We need the value in EAX.
- LoadConstantNoClobber(rAX, char_value);
+ LoadConstantNoClobber(rs_rAX, char_value);
} else {
// Character is not a constant; compare at runtime.
- LoadValueDirectFixed(rl_char, rAX);
- launchpad_branch = OpCmpImmBranch(kCondGt, rAX, 0xFFFF, nullptr);
+ LoadValueDirectFixed(rl_char, rs_rAX);
+ launchpad_branch = OpCmpImmBranch(kCondGt, rs_rAX, 0xFFFF, nullptr);
}
// From here down, we know that we are looking for a char that fits in 16 bits.
@@ -1061,7 +1059,7 @@
NewLIR1(kX86Push32R, rDI);
// Compute the number of words to search in to rCX.
- LoadWordDisp(rDX, count_offset, rCX);
+ LoadWordDisp(rs_rDX, count_offset, rs_rCX);
LIR *length_compare = nullptr;
int start_value = 0;
if (zero_based) {
@@ -1075,23 +1073,23 @@
start_value = std::max(start_value, 0);
// Is the start > count?
- length_compare = OpCmpImmBranch(kCondLe, rCX, start_value, nullptr);
+ length_compare = OpCmpImmBranch(kCondLe, rs_rCX, start_value, nullptr);
if (start_value != 0) {
- OpRegImm(kOpSub, rCX, start_value);
+ OpRegImm(kOpSub, rs_rCX, start_value);
}
} else {
// Runtime start index.
rl_start = UpdateLoc(rl_start);
if (rl_start.location == kLocPhysReg) {
- length_compare = OpCmpBranch(kCondLe, rCX, rl_start.reg.GetReg(), nullptr);
- OpRegReg(kOpSub, rCX, rl_start.reg.GetReg());
+ length_compare = OpCmpBranch(kCondLe, rs_rCX, rl_start.reg, nullptr);
+ OpRegReg(kOpSub, rs_rCX, rl_start.reg);
} else {
// Compare to memory to avoid a register load. Handle pushed EDI.
int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t);
- OpRegMem(kOpCmp, rCX, rX86_SP, displacement);
+ OpRegMem(kOpCmp, rs_rCX, rs_rX86_SP, displacement);
length_compare = NewLIR2(kX86Jcc8, 0, kX86CondLe);
- OpRegMem(kOpSub, rCX, rX86_SP, displacement);
+ OpRegMem(kOpSub, rs_rCX, rs_rX86_SP, displacement);
}
}
}
@@ -1101,14 +1099,14 @@
// Load the address of the string into EBX.
// The string starts at VALUE(String) + 2 * OFFSET(String) + DATA_OFFSET.
- LoadWordDisp(rDX, value_offset, rDI);
- LoadWordDisp(rDX, offset_offset, rBX);
- OpLea(rBX, rDI, rBX, 1, data_offset);
+ LoadWordDisp(rs_rDX, value_offset, rs_rDI);
+ LoadWordDisp(rs_rDX, offset_offset, rs_rBX);
+ OpLea(rs_rBX, rs_rDI, rs_rBX, 1, data_offset);
// Now compute into EDI where the search will start.
if (zero_based || rl_start.is_const) {
if (start_value == 0) {
- OpRegCopy(rDI, rBX);
+ OpRegCopy(rs_rDI, rs_rBX);
} else {
NewLIR3(kX86Lea32RM, rDI, rBX, 2 * start_value);
}
@@ -1117,17 +1115,17 @@
if (rl_start.reg.GetReg() == rDI) {
// We have a slight problem here. We are already using RDI!
// Grab the value from the stack.
- LoadWordDisp(rX86_SP, 0, rDX);
- OpLea(rDI, rBX, rDX, 1, 0);
+ LoadWordDisp(rs_rX86_SP, 0, rs_rDX);
+ OpLea(rs_rDI, rs_rBX, rs_rDX, 1, 0);
} else {
- OpLea(rDI, rBX, rl_start.reg.GetReg(), 1, 0);
+ OpLea(rs_rDI, rs_rBX, rl_start.reg, 1, 0);
}
} else {
- OpRegCopy(rDI, rBX);
+ OpRegCopy(rs_rDI, rs_rBX);
// Load the start index from stack, remembering that we pushed EDI.
int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t);
- LoadWordDisp(rX86_SP, displacement, rDX);
- OpLea(rDI, rBX, rDX, 1, 0);
+ LoadWordDisp(rs_rX86_SP, displacement, rs_rDX);
+ OpLea(rs_rDI, rs_rBX, rs_rDX, 1, 0);
}
}
@@ -1140,8 +1138,8 @@
// yes, we matched. Compute the index of the result.
// index = ((curr_ptr - orig_ptr) / 2) - 1.
- OpRegReg(kOpSub, rDI, rBX);
- OpRegImm(kOpAsr, rDI, 1);
+ OpRegReg(kOpSub, rs_rDI, rs_rBX);
+ OpRegImm(kOpAsr, rs_rDI, 1);
NewLIR3(kX86Lea32RM, rl_return.reg.GetReg(), rDI, -1);
LIR *all_done = NewLIR1(kX86Jmp8, 0);
@@ -1149,7 +1147,7 @@
LIR *not_found = NewLIR0(kPseudoTargetLabel);
length_compare->target = not_found;
failed_branch->target = not_found;
- LoadConstantNoClobber(rl_return.reg.GetReg(), -1);
+ LoadConstantNoClobber(rl_return.reg, -1);
// And join up at the end.
all_done->target = NewLIR0(kPseudoTargetLabel);
diff --git a/compiler/dex/quick/x86/utility_x86.cc b/compiler/dex/quick/x86/utility_x86.cc
index bd82bf6..013c40b 100644
--- a/compiler/dex/quick/x86/utility_x86.cc
+++ b/compiler/dex/quick/x86/utility_x86.cc
@@ -23,26 +23,26 @@
/* This file contains codegen for the X86 ISA */
-LIR* X86Mir2Lir::OpFpRegCopy(int r_dest, int r_src) {
+LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {
int opcode;
/* must be both DOUBLE or both not DOUBLE */
- DCHECK_EQ(X86_DOUBLEREG(r_dest), X86_DOUBLEREG(r_src));
- if (X86_DOUBLEREG(r_dest)) {
+ DCHECK_EQ(X86_DOUBLEREG(r_dest.GetReg()), X86_DOUBLEREG(r_src.GetReg()));
+ if (X86_DOUBLEREG(r_dest.GetReg())) {
opcode = kX86MovsdRR;
} else {
- if (X86_SINGLEREG(r_dest)) {
- if (X86_SINGLEREG(r_src)) {
+ if (X86_SINGLEREG(r_dest.GetReg())) {
+ if (X86_SINGLEREG(r_src.GetReg())) {
opcode = kX86MovssRR;
} else { // Fpr <- Gpr
opcode = kX86MovdxrRR;
}
} else { // Gpr <- Fpr
- DCHECK(X86_SINGLEREG(r_src));
+ DCHECK(X86_SINGLEREG(r_src.GetReg()));
opcode = kX86MovdrxRR;
}
}
DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL);
- LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest, r_src);
+ LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg());
if (r_dest == r_src) {
res->flags.is_nop = true;
}
@@ -74,26 +74,26 @@
* 1) r_dest is freshly returned from AllocTemp or
* 2) The codegen is under fixed register usage
*/
-LIR* X86Mir2Lir::LoadConstantNoClobber(int r_dest, int value) {
- int r_dest_save = r_dest;
- if (X86_FPREG(r_dest)) {
+LIR* X86Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
+ RegStorage r_dest_save = r_dest;
+ if (X86_FPREG(r_dest.GetReg())) {
if (value == 0) {
- return NewLIR2(kX86XorpsRR, r_dest, r_dest);
+ return NewLIR2(kX86XorpsRR, r_dest.GetReg(), r_dest.GetReg());
}
- DCHECK(X86_SINGLEREG(r_dest));
+ DCHECK(X86_SINGLEREG(r_dest.GetReg()));
r_dest = AllocTemp();
}
LIR *res;
if (value == 0) {
- res = NewLIR2(kX86Xor32RR, r_dest, r_dest);
+ res = NewLIR2(kX86Xor32RR, r_dest.GetReg(), r_dest.GetReg());
} else {
// Note, there is no byte immediate form of a 32 bit immediate move.
- res = NewLIR2(kX86Mov32RI, r_dest, value);
+ res = NewLIR2(kX86Mov32RI, r_dest.GetReg(), value);
}
- if (X86_FPREG(r_dest_save)) {
- NewLIR2(kX86MovdxrRR, r_dest_save, r_dest);
+ if (X86_FPREG(r_dest_save.GetReg())) {
+ NewLIR2(kX86MovdxrRR, r_dest_save.GetReg(), r_dest.GetReg());
FreeTemp(r_dest);
}
@@ -113,7 +113,7 @@
return branch;
}
-LIR* X86Mir2Lir::OpReg(OpKind op, int r_dest_src) {
+LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
X86OpCode opcode = kX86Bkpt;
switch (op) {
case kOpNeg: opcode = kX86Neg32R; break;
@@ -123,13 +123,13 @@
default:
LOG(FATAL) << "Bad case in OpReg " << op;
}
- return NewLIR1(opcode, r_dest_src);
+ return NewLIR1(opcode, r_dest_src.GetReg());
}
-LIR* X86Mir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value) {
+LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) {
X86OpCode opcode = kX86Bkpt;
bool byte_imm = IS_SIMM8(value);
- DCHECK(!X86_FPREG(r_dest_src1));
+ DCHECK(!X86_FPREG(r_dest_src1.GetReg()));
switch (op) {
case kOpLsl: opcode = kX86Sal32RI; break;
case kOpLsr: opcode = kX86Shr32RI; break;
@@ -152,14 +152,14 @@
break;
case kOpMul:
opcode = byte_imm ? kX86Imul32RRI8 : kX86Imul32RRI;
- return NewLIR3(opcode, r_dest_src1, r_dest_src1, value);
+ return NewLIR3(opcode, r_dest_src1.GetReg(), r_dest_src1.GetReg(), value);
default:
LOG(FATAL) << "Bad case in OpRegImm " << op;
}
- return NewLIR2(opcode, r_dest_src1, value);
+ return NewLIR2(opcode, r_dest_src1.GetReg(), value);
}
-LIR* X86Mir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2) {
+LIR* X86Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) {
X86OpCode opcode = kX86Nop;
bool src2_must_be_cx = false;
switch (op) {
@@ -192,10 +192,10 @@
case kOpXor: opcode = kX86Xor32RR; break;
case kOp2Byte:
// Use shifts instead of a byte operand if the source can't be byte accessed.
- if (r_src2 >= 4) {
- NewLIR2(kX86Mov32RR, r_dest_src1, r_src2);
- NewLIR2(kX86Sal32RI, r_dest_src1, 24);
- return NewLIR2(kX86Sar32RI, r_dest_src1, 24);
+ if (r_src2.GetReg() >= 4) {
+ NewLIR2(kX86Mov32RR, r_dest_src1.GetReg(), r_src2.GetReg());
+ NewLIR2(kX86Sal32RI, r_dest_src1.GetReg(), 24);
+ return NewLIR2(kX86Sar32RI, r_dest_src1.GetReg(), 24);
} else {
opcode = kX86Movsx8RR;
}
@@ -207,49 +207,49 @@
LOG(FATAL) << "Bad case in OpRegReg " << op;
break;
}
- CHECK(!src2_must_be_cx || r_src2 == rCX);
- return NewLIR2(opcode, r_dest_src1, r_src2);
+ CHECK(!src2_must_be_cx || r_src2.GetReg() == rCX);
+ return NewLIR2(opcode, r_dest_src1.GetReg(), r_src2.GetReg());
}
-LIR* X86Mir2Lir::OpMovRegMem(int r_dest, int r_base, int offset, MoveType move_type) {
- DCHECK(!(X86_FPREG(r_base)));
-
+LIR* X86Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) {
+ DCHECK(!(X86_FPREG(r_base.GetReg())));
X86OpCode opcode = kX86Nop;
+ int dest = r_dest.IsPair() ? r_dest.GetLowReg() : r_dest.GetReg();
switch (move_type) {
case kMov8GP:
- CHECK(!X86_FPREG(r_dest));
+ CHECK(!X86_FPREG(dest));
opcode = kX86Mov8RM;
break;
case kMov16GP:
- CHECK(!X86_FPREG(r_dest));
+ CHECK(!X86_FPREG(dest));
opcode = kX86Mov16RM;
break;
case kMov32GP:
- CHECK(!X86_FPREG(r_dest));
+ CHECK(!X86_FPREG(dest));
opcode = kX86Mov32RM;
break;
case kMov32FP:
- CHECK(X86_FPREG(r_dest));
+ CHECK(X86_FPREG(dest));
opcode = kX86MovssRM;
break;
case kMov64FP:
- CHECK(X86_FPREG(r_dest));
+ CHECK(X86_FPREG(dest));
opcode = kX86MovsdRM;
break;
case kMovU128FP:
- CHECK(X86_FPREG(r_dest));
+ CHECK(X86_FPREG(dest));
opcode = kX86MovupsRM;
break;
case kMovA128FP:
- CHECK(X86_FPREG(r_dest));
+ CHECK(X86_FPREG(dest));
opcode = kX86MovapsRM;
break;
case kMovLo128FP:
- CHECK(X86_FPREG(r_dest));
+ CHECK(X86_FPREG(dest));
opcode = kX86MovlpsRM;
break;
case kMovHi128FP:
- CHECK(X86_FPREG(r_dest));
+ CHECK(X86_FPREG(dest));
opcode = kX86MovhpsRM;
break;
case kMov64GP:
@@ -260,48 +260,49 @@
break;
}
- return NewLIR3(opcode, r_dest, r_base, offset);
+ return NewLIR3(opcode, dest, r_base.GetReg(), offset);
}
-LIR* X86Mir2Lir::OpMovMemReg(int r_base, int offset, int r_src, MoveType move_type) {
- DCHECK(!(X86_FPREG(r_base)));
+LIR* X86Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {
+ DCHECK(!(X86_FPREG(r_base.GetReg())));
+ int src = r_src.IsPair() ? r_src.GetLowReg() : r_src.GetReg();
X86OpCode opcode = kX86Nop;
switch (move_type) {
case kMov8GP:
- CHECK(!X86_FPREG(r_src));
+ CHECK(!X86_FPREG(src));
opcode = kX86Mov8MR;
break;
case kMov16GP:
- CHECK(!X86_FPREG(r_src));
+ CHECK(!X86_FPREG(src));
opcode = kX86Mov16MR;
break;
case kMov32GP:
- CHECK(!X86_FPREG(r_src));
+ CHECK(!X86_FPREG(src));
opcode = kX86Mov32MR;
break;
case kMov32FP:
- CHECK(X86_FPREG(r_src));
+ CHECK(X86_FPREG(src));
opcode = kX86MovssMR;
break;
case kMov64FP:
- CHECK(X86_FPREG(r_src));
+ CHECK(X86_FPREG(src));
opcode = kX86MovsdMR;
break;
case kMovU128FP:
- CHECK(X86_FPREG(r_src));
+ CHECK(X86_FPREG(src));
opcode = kX86MovupsMR;
break;
case kMovA128FP:
- CHECK(X86_FPREG(r_src));
+ CHECK(X86_FPREG(src));
opcode = kX86MovapsMR;
break;
case kMovLo128FP:
- CHECK(X86_FPREG(r_src));
+ CHECK(X86_FPREG(src));
opcode = kX86MovlpsMR;
break;
case kMovHi128FP:
- CHECK(X86_FPREG(r_src));
+ CHECK(X86_FPREG(src));
opcode = kX86MovhpsMR;
break;
case kMov64GP:
@@ -312,17 +313,16 @@
break;
}
- return NewLIR3(opcode, r_base, offset, r_src);
+ return NewLIR3(opcode, r_base.GetReg(), offset, src);
}
-LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src) {
+LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
// The only conditional reg to reg operation supported is Cmov
DCHECK_EQ(op, kOpCmov);
- return NewLIR3(kX86Cmov32RRC, r_dest, r_src, X86ConditionEncoding(cc));
+ return NewLIR3(kX86Cmov32RRC, r_dest.GetReg(), r_src.GetReg(), X86ConditionEncoding(cc));
}
-LIR* X86Mir2Lir::OpRegMem(OpKind op, int r_dest, int rBase,
- int offset) {
+LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) {
X86OpCode opcode = kX86Nop;
switch (op) {
// X86 binary opcodes
@@ -341,8 +341,8 @@
LOG(FATAL) << "Bad case in OpRegMem " << op;
break;
}
- LIR *l = NewLIR3(opcode, r_dest, rBase, offset);
- if (rBase == rX86_SP) {
+ LIR *l = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), offset);
+ if (r_base == rs_rX86_SP) {
AnnotateDalvikRegAccess(l, offset >> 2, true /* is_load */, false /* is_64bit */);
}
return l;
@@ -372,7 +372,7 @@
return l;
}
-LIR* X86Mir2Lir::OpRegMem(OpKind op, int r_dest, RegLocation rl_value) {
+LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegLocation rl_value) {
DCHECK_NE(rl_value.location, kLocPhysReg);
int displacement = SRegOffset(rl_value.s_reg_low);
X86OpCode opcode = kX86Nop;
@@ -389,24 +389,24 @@
LOG(FATAL) << "Bad case in OpRegMem " << op;
break;
}
- LIR *l = NewLIR3(opcode, r_dest, rX86_SP, displacement);
+ LIR *l = NewLIR3(opcode, r_dest.GetReg(), rX86_SP, displacement);
AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, false /* is_64bit */);
return l;
}
-LIR* X86Mir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1,
- int r_src2) {
+LIR* X86Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1,
+ RegStorage r_src2) {
if (r_dest != r_src1 && r_dest != r_src2) {
if (op == kOpAdd) { // lea special case, except can't encode rbp as base
if (r_src1 == r_src2) {
OpRegCopy(r_dest, r_src1);
return OpRegImm(kOpLsl, r_dest, 1);
- } else if (r_src1 != rBP) {
- return NewLIR5(kX86Lea32RA, r_dest, r_src1 /* base */,
- r_src2 /* index */, 0 /* scale */, 0 /* disp */);
+ } else if (r_src1 != rs_rBP) {
+ return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r_src1.GetReg() /* base */,
+ r_src2.GetReg() /* index */, 0 /* scale */, 0 /* disp */);
} else {
- return NewLIR5(kX86Lea32RA, r_dest, r_src2 /* base */,
- r_src1 /* index */, 0 /* scale */, 0 /* disp */);
+ return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r_src2.GetReg() /* base */,
+ r_src1.GetReg() /* index */, 0 /* scale */, 0 /* disp */);
}
} else {
OpRegCopy(r_dest, r_src1);
@@ -422,7 +422,7 @@
break;
case kOpSbc:
case kOpLsl: case kOpLsr: case kOpAsr: case kOpRor: {
- int t_reg = AllocTemp();
+ RegStorage t_reg = AllocTemp();
OpRegCopy(t_reg, r_src1);
OpRegReg(op, t_reg, r_src2);
LIR* res = OpRegCopy(r_dest, t_reg);
@@ -442,25 +442,24 @@
}
}
-LIR* X86Mir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src,
- int value) {
+LIR* X86Mir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src, int value) {
if (op == kOpMul) {
X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI;
- return NewLIR3(opcode, r_dest, r_src, value);
+ return NewLIR3(opcode, r_dest.GetReg(), r_src.GetReg(), value);
} else if (op == kOpAnd) {
- if (value == 0xFF && r_src < 4) {
- return NewLIR2(kX86Movzx8RR, r_dest, r_src);
+ if (value == 0xFF && r_src.GetReg() < 4) {
+ return NewLIR2(kX86Movzx8RR, r_dest.GetReg(), r_src.GetReg());
} else if (value == 0xFFFF) {
- return NewLIR2(kX86Movzx16RR, r_dest, r_src);
+ return NewLIR2(kX86Movzx16RR, r_dest.GetReg(), r_src.GetReg());
}
}
if (r_dest != r_src) {
if (false && op == kOpLsl && value >= 0 && value <= 3) { // lea shift special case
// TODO: fix bug in LEA encoding when disp == 0
- return NewLIR5(kX86Lea32RA, r_dest, r5sib_no_base /* base */,
- r_src /* index */, value /* scale */, 0 /* disp */);
+ return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r5sib_no_base /* base */,
+ r_src.GetReg() /* index */, value /* scale */, 0 /* disp */);
} else if (op == kOpAdd) { // lea add special case
- return NewLIR5(kX86Lea32RA, r_dest, r_src /* base */,
+ return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r_src.GetReg() /* base */,
r4sib_no_index /* index */, 0 /* scale */, value /* disp */);
}
OpRegCopy(r_dest, r_src);
@@ -480,7 +479,7 @@
return NewLIR1(opcode, thread_offset.Int32Value());
}
-LIR* X86Mir2Lir::OpMem(OpKind op, int rBase, int disp) {
+LIR* X86Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) {
X86OpCode opcode = kX86Bkpt;
switch (op) {
case kOpBlx: opcode = kX86CallM; break;
@@ -488,18 +487,19 @@
LOG(FATAL) << "Bad opcode: " << op;
break;
}
- return NewLIR2(opcode, rBase, disp);
+ return NewLIR2(opcode, r_base.GetReg(), disp);
}
-LIR* X86Mir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) {
+LIR* X86Mir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) {
int32_t val_lo = Low32Bits(value);
int32_t val_hi = High32Bits(value);
+ int32_t low_reg_val = r_dest.IsPair() ? r_dest.GetLowReg() : r_dest.GetReg();
LIR *res;
- if (X86_FPREG(r_dest_lo)) {
- DCHECK(X86_FPREG(r_dest_hi)); // ignore r_dest_hi
- DCHECK_EQ(r_dest_lo, r_dest_hi);
+ bool is_fp = X86_FPREG(low_reg_val);
+ // TODO: clean this up once we fully recognize 64-bit storage containers.
+ if (is_fp) {
if (value == 0) {
- return NewLIR2(kX86XorpsRR, r_dest_lo, r_dest_lo);
+ return NewLIR2(kX86XorpsRR, low_reg_val, low_reg_val);
} else if (base_of_code_ != nullptr) {
// We will load the value from the literal area.
LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi);
@@ -515,45 +515,49 @@
// We don't know the proper offset for the value, so pick one that will force
// 4 byte offset. We will fix this up in the assembler later to have the right
// value.
- res = LoadBaseDisp(rl_method.reg.GetReg(), 256 /* bogus */, r_dest_lo, kDouble, INVALID_SREG);
+ res = LoadBaseDisp(rl_method.reg, 256 /* bogus */, RegStorage::Solo64(low_reg_val),
+ kDouble, INVALID_SREG);
res->target = data_target;
res->flags.fixup = kFixupLoad;
SetMemRefType(res, true, kLiteral);
store_method_addr_used_ = true;
} else {
if (val_lo == 0) {
- res = NewLIR2(kX86XorpsRR, r_dest_lo, r_dest_lo);
+ res = NewLIR2(kX86XorpsRR, low_reg_val, low_reg_val);
} else {
- res = LoadConstantNoClobber(r_dest_lo, val_lo);
+ res = LoadConstantNoClobber(RegStorage::Solo32(low_reg_val), val_lo);
}
if (val_hi != 0) {
- r_dest_hi = AllocTempDouble();
- LoadConstantNoClobber(r_dest_hi, val_hi);
- NewLIR2(kX86PunpckldqRR, r_dest_lo, r_dest_hi);
+ // FIXME: clean up when AllocTempDouble no longer returns a pair.
+ RegStorage r_dest_hi = AllocTempDouble();
+ LoadConstantNoClobber(RegStorage::Solo32(r_dest_hi.GetLowReg()), val_hi);
+ NewLIR2(kX86PunpckldqRR, low_reg_val, r_dest_hi.GetLowReg());
FreeTemp(r_dest_hi);
}
}
} else {
- res = LoadConstantNoClobber(r_dest_lo, val_lo);
- LoadConstantNoClobber(r_dest_hi, val_hi);
+ res = LoadConstantNoClobber(r_dest.GetLow(), val_lo);
+ LoadConstantNoClobber(r_dest.GetHigh(), val_hi);
}
return res;
}
-LIR* X86Mir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale,
- int displacement, int r_dest, int r_dest_hi, OpSize size,
- int s_reg) {
+// FIXME: don't split r_dest into two storage units.
+LIR* X86Mir2Lir::LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale,
+ int displacement, RegStorage r_dest, RegStorage r_dest_hi,
+ OpSize size, int s_reg) {
LIR *load = NULL;
LIR *load2 = NULL;
- bool is_array = r_index != INVALID_REG;
+ bool is_array = r_index.Valid();
bool pair = false;
bool is64bit = false;
X86OpCode opcode = kX86Nop;
switch (size) {
case kLong:
case kDouble:
+ // TODO: use regstorage attributes here.
is64bit = true;
- if (X86_FPREG(r_dest)) {
+ if (X86_FPREG(r_dest.GetReg())) {
opcode = is_array ? kX86MovsdRA : kX86MovsdRM;
} else {
pair = true;
@@ -565,9 +569,9 @@
case kWord:
case kSingle:
opcode = is_array ? kX86Mov32RA : kX86Mov32RM;
- if (X86_FPREG(r_dest)) {
+ if (X86_FPREG(r_dest.GetReg())) {
opcode = is_array ? kX86MovssRA : kX86MovssRM;
- DCHECK(X86_SINGLEREG(r_dest));
+ DCHECK(X86_SINGLEREG(r_dest.GetReg()));
}
DCHECK_EQ((displacement & 0x3), 0);
break;
@@ -591,19 +595,19 @@
if (!is_array) {
if (!pair) {
- load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET);
+ load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), displacement + LOWORD_OFFSET);
} else {
- if (rBase == r_dest) {
- load2 = NewLIR3(opcode, r_dest_hi, rBase,
+ if (r_base == r_dest) {
+ load2 = NewLIR3(opcode, r_dest_hi.GetReg(), r_base.GetReg(),
displacement + HIWORD_OFFSET);
- load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET);
+ load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), displacement + LOWORD_OFFSET);
} else {
- load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET);
- load2 = NewLIR3(opcode, r_dest_hi, rBase,
+ load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), displacement + LOWORD_OFFSET);
+ load2 = NewLIR3(opcode, r_dest_hi.GetReg(), r_base.GetReg(),
displacement + HIWORD_OFFSET);
}
}
- if (rBase == rX86_SP) {
+ if (r_base == rs_rX86_SP) {
AnnotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2,
true /* is_load */, is64bit);
if (pair) {
@@ -613,39 +617,39 @@
}
} else {
if (!pair) {
- load = NewLIR5(opcode, r_dest, rBase, r_index, scale,
+ load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
displacement + LOWORD_OFFSET);
} else {
- if (rBase == r_dest) {
+ if (r_base == r_dest) {
if (r_dest_hi == r_index) {
// We can't use either register for the first load.
- int temp = AllocTemp();
- load2 = NewLIR5(opcode, temp, rBase, r_index, scale,
+ RegStorage temp = AllocTemp();
+ load2 = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
displacement + HIWORD_OFFSET);
- load = NewLIR5(opcode, r_dest, rBase, r_index, scale,
+ load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
displacement + LOWORD_OFFSET);
OpRegCopy(r_dest_hi, temp);
FreeTemp(temp);
} else {
- load2 = NewLIR5(opcode, r_dest_hi, rBase, r_index, scale,
+ load2 = NewLIR5(opcode, r_dest_hi.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
displacement + HIWORD_OFFSET);
- load = NewLIR5(opcode, r_dest, rBase, r_index, scale,
+ load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
displacement + LOWORD_OFFSET);
}
} else {
if (r_dest == r_index) {
// We can't use either register for the first load.
- int temp = AllocTemp();
- load = NewLIR5(opcode, temp, rBase, r_index, scale,
+ RegStorage temp = AllocTemp();
+ load = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
displacement + LOWORD_OFFSET);
- load2 = NewLIR5(opcode, r_dest_hi, rBase, r_index, scale,
+ load2 = NewLIR5(opcode, r_dest_hi.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
displacement + HIWORD_OFFSET);
OpRegCopy(r_dest, temp);
FreeTemp(temp);
} else {
- load = NewLIR5(opcode, r_dest, rBase, r_index, scale,
+ load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
displacement + LOWORD_OFFSET);
- load2 = NewLIR5(opcode, r_dest_hi, rBase, r_index, scale,
+ load2 = NewLIR5(opcode, r_dest_hi.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
displacement + HIWORD_OFFSET);
}
}
@@ -656,30 +660,31 @@
}
/* Load value from base + scaled index. */
-LIR* X86Mir2Lir::LoadBaseIndexed(int rBase,
- int r_index, int r_dest, int scale, OpSize size) {
- return LoadBaseIndexedDisp(rBase, r_index, scale, 0,
- r_dest, INVALID_REG, size, INVALID_SREG);
+LIR* X86Mir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest,
+ int scale, OpSize size) {
+ return LoadBaseIndexedDisp(r_base, r_index, scale, 0,
+ r_dest, RegStorage::InvalidReg(), size, INVALID_SREG);
}
-LIR* X86Mir2Lir::LoadBaseDisp(int rBase, int displacement,
- int r_dest, OpSize size, int s_reg) {
- return LoadBaseIndexedDisp(rBase, INVALID_REG, 0, displacement,
- r_dest, INVALID_REG, size, s_reg);
+LIR* X86Mir2Lir::LoadBaseDisp(RegStorage r_base, int displacement,
+ RegStorage r_dest, OpSize size, int s_reg) {
+ return LoadBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement,
+ r_dest, RegStorage::InvalidReg(), size, s_reg);
}
-LIR* X86Mir2Lir::LoadBaseDispWide(int rBase, int displacement,
- int r_dest_lo, int r_dest_hi, int s_reg) {
- return LoadBaseIndexedDisp(rBase, INVALID_REG, 0, displacement,
- r_dest_lo, r_dest_hi, kLong, s_reg);
+LIR* X86Mir2Lir::LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest,
+ int s_reg) {
+ return LoadBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement,
+ r_dest.GetLow(), r_dest.GetHigh(), kLong, s_reg);
}
-LIR* X86Mir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale,
- int displacement, int r_src, int r_src_hi, OpSize size,
- int s_reg) {
+LIR* X86Mir2Lir::StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale,
+ int displacement, RegStorage r_src, RegStorage r_src_hi,
+ OpSize size, int s_reg) {
LIR *store = NULL;
LIR *store2 = NULL;
- bool is_array = r_index != INVALID_REG;
+ bool is_array = r_index.Valid();
+ // FIXME: use regstorage attributes in place of these.
bool pair = false;
bool is64bit = false;
X86OpCode opcode = kX86Nop;
@@ -687,7 +692,7 @@
case kLong:
case kDouble:
is64bit = true;
- if (X86_FPREG(r_src)) {
+ if (X86_FPREG(r_src.GetReg())) {
opcode = is_array ? kX86MovsdAR : kX86MovsdMR;
} else {
pair = true;
@@ -699,9 +704,9 @@
case kWord:
case kSingle:
opcode = is_array ? kX86Mov32AR : kX86Mov32MR;
- if (X86_FPREG(r_src)) {
+ if (X86_FPREG(r_src.GetReg())) {
opcode = is_array ? kX86MovssAR : kX86MovssMR;
- DCHECK(X86_SINGLEREG(r_src));
+ DCHECK(X86_SINGLEREG(r_src.GetReg()));
}
DCHECK_EQ((displacement & 0x3), 0);
break;
@@ -720,12 +725,12 @@
if (!is_array) {
if (!pair) {
- store = NewLIR3(opcode, rBase, displacement + LOWORD_OFFSET, r_src);
+ store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetReg());
} else {
- store = NewLIR3(opcode, rBase, displacement + LOWORD_OFFSET, r_src);
- store2 = NewLIR3(opcode, rBase, displacement + HIWORD_OFFSET, r_src_hi);
+ store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetReg());
+ store2 = NewLIR3(opcode, r_base.GetReg(), displacement + HIWORD_OFFSET, r_src_hi.GetReg());
}
- if (rBase == rX86_SP) {
+ if (r_base == rs_rX86_SP) {
AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2,
false /* is_load */, is64bit);
if (pair) {
@@ -735,13 +740,13 @@
}
} else {
if (!pair) {
- store = NewLIR5(opcode, rBase, r_index, scale,
- displacement + LOWORD_OFFSET, r_src);
+ store = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale,
+ displacement + LOWORD_OFFSET, r_src.GetReg());
} else {
- store = NewLIR5(opcode, rBase, r_index, scale,
- displacement + LOWORD_OFFSET, r_src);
- store2 = NewLIR5(opcode, rBase, r_index, scale,
- displacement + HIWORD_OFFSET, r_src_hi);
+ store = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale,
+ displacement + LOWORD_OFFSET, r_src.GetReg());
+ store2 = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale,
+ displacement + HIWORD_OFFSET, r_src_hi.GetReg());
}
}
@@ -749,23 +754,21 @@
}
/* store value base base + scaled index. */
-LIR* X86Mir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src,
+LIR* X86Mir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src,
int scale, OpSize size) {
- return StoreBaseIndexedDisp(rBase, r_index, scale, 0,
- r_src, INVALID_REG, size, INVALID_SREG);
+ return StoreBaseIndexedDisp(r_base, r_index, scale, 0,
+ r_src, RegStorage::InvalidReg(), size, INVALID_SREG);
}
-LIR* X86Mir2Lir::StoreBaseDisp(int rBase, int displacement,
- int r_src, OpSize size) {
- return StoreBaseIndexedDisp(rBase, INVALID_REG, 0,
- displacement, r_src, INVALID_REG, size,
- INVALID_SREG);
+LIR* X86Mir2Lir::StoreBaseDisp(RegStorage r_base, int displacement,
+ RegStorage r_src, OpSize size) {
+ return StoreBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, r_src,
+ RegStorage::InvalidReg(), size, INVALID_SREG);
}
-LIR* X86Mir2Lir::StoreBaseDispWide(int rBase, int displacement,
- int r_src_lo, int r_src_hi) {
- return StoreBaseIndexedDisp(rBase, INVALID_REG, 0, displacement,
- r_src_lo, r_src_hi, kLong, INVALID_SREG);
+LIR* X86Mir2Lir::StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src) {
+ return StoreBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement,
+ r_src.GetLow(), r_src.GetHigh(), kLong, INVALID_SREG);
}
/*
@@ -774,15 +777,15 @@
*/
void X86Mir2Lir::OpVectorRegCopyWide(uint8_t fp_reg, uint8_t low_reg, uint8_t high_reg) {
NewLIR2(kX86MovdxrRR, fp_reg, low_reg);
- int tmp_reg = AllocTempDouble();
+ int tmp_reg = AllocTempDouble().GetLowReg();
NewLIR2(kX86MovdxrRR, tmp_reg, high_reg);
NewLIR2(kX86PunpckldqRR, fp_reg, tmp_reg);
FreeTemp(tmp_reg);
}
-LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, int temp_reg, int base_reg,
+LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
int offset, int check_value, LIR* target) {
- NewLIR3(IS_SIMM8(check_value) ? kX86Cmp32MI8 : kX86Cmp32MI, base_reg, offset,
+ NewLIR3(IS_SIMM8(check_value) ? kX86Cmp32MI8 : kX86Cmp32MI, base_reg.GetReg(), offset,
check_value);
LIR* branch = OpCondBranch(cond, target);
return branch;
diff --git a/compiler/dex/quick/x86/x86_lir.h b/compiler/dex/quick/x86/x86_lir.h
index b72e60d..797bc82 100644
--- a/compiler/dex/quick/x86/x86_lir.h
+++ b/compiler/dex/quick/x86/x86_lir.h
@@ -189,22 +189,52 @@
fr15 = 15 + X86_FP_REG_OFFSET,
};
+const RegStorage rs_r0(RegStorage::k32BitSolo, r0);
+const RegStorage rs_rAX = rs_r0;
+const RegStorage rs_r1(RegStorage::k32BitSolo, r1);
+const RegStorage rs_rCX = rs_r1;
+const RegStorage rs_r2(RegStorage::k32BitSolo, r2);
+const RegStorage rs_rDX = rs_r2;
+const RegStorage rs_r3(RegStorage::k32BitSolo, r3);
+const RegStorage rs_rBX = rs_r3;
+const RegStorage rs_r4sp(RegStorage::k32BitSolo, r4sp);
+const RegStorage rs_rX86_SP = rs_r4sp;
+const RegStorage rs_r5(RegStorage::k32BitSolo, r5);
+const RegStorage rs_rBP = rs_r5;
+const RegStorage rs_r6(RegStorage::k32BitSolo, r6);
+const RegStorage rs_rSI = rs_r6;
+const RegStorage rs_r7(RegStorage::k32BitSolo, r7);
+const RegStorage rs_rDI = rs_r7;
+
+// TODO: elminate these #defines?
#define rX86_ARG0 rAX
+#define rs_rX86_ARG0 rs_rAX
#define rX86_ARG1 rCX
+#define rs_rX86_ARG1 rs_rCX
#define rX86_ARG2 rDX
+#define rs_rX86_ARG2 rs_rDX
#define rX86_ARG3 rBX
+#define rs_rX86_ARG3 rs_rBX
#define rX86_FARG0 rAX
+#define rs_rX86_FARG0 rs_rAX
#define rX86_FARG1 rCX
+#define rs_rX86_FARG1 rs_rCX
#define rX86_FARG2 rDX
+#define rs_rX86_FARG2 rs_rDX
#define rX86_FARG3 rBX
+#define rs_rX86_FARG3 rs_rBX
#define rX86_RET0 rAX
+#define rs_rX86_RET0 rs_rAX
#define rX86_RET1 rDX
+#define rs_rX86_RET1 rs_rDX
#define rX86_INVOKE_TGT rAX
-#define rX86_LR INVALID_REG
-#define rX86_SUSPEND INVALID_REG
-#define rX86_SELF INVALID_REG
+#define rs_rX86_INVOKE_TGT rs_rAX
+#define rX86_LR RegStorage::kInvalidRegVal
+#define rX86_SUSPEND RegStorage::kInvalidRegVal
+#define rX86_SELF RegStorage::kInvalidRegVal
#define rX86_COUNT rCX
-#define rX86_PC INVALID_REG
+#define rs_rX86_COUNT rs_rCX
+#define rX86_PC RegStorage::kInvalidRegVal
// RegisterLocation templates return values (r_V0, or r_V0/r_V1).
const RegLocation x86_loc_c_return