commit 2a7a1d7808f003bea908023ebd11eb442d2fca39
author Roland Levillain <rpl@google.com> Wed Apr 29 11:12:33 2015 +0000
committer Roland Levillain <rpl@google.com> Wed Apr 29 11:12:33 2015 +0000
tree 9a74fcc5590e9f39c0019edff70cd89139fcd890
parent 9b95a057ee20e4b1ca2e9c663726482172dc9ba3

Revert "Revert "Revert "[optimizing] Improve x86 shifts"""

This reverts commit 9b95a057ee20e4b1ca2e9c663726482172dc9ba3.

Reverting this CL as it breaks libcore tests:

  org.apache.harmony.tests.java.lang.DoubleTest#test_compare
      junit.framework.AssertionFailedError: compare() -0.0 should be less 0.0
      	at junit.framework.Assert.assertTrue(Assert.java:140)
      	at org.apache.harmony.tests.java.lang.DoubleTest.test_compare(DoubleTest.java:258)
    org.apache.harmony.tests.java.lang.DoubleTest#test_compare FAIL (EXEC_FAILED)
  
  org.apache.harmony.tests.java.lang.DoubleTest#test_compareToLjava_lang_Double
      junit.framework.AssertionFailedError: Assert 2: compare() -0.0 should be less 0.0
      	at junit.framework.Assert.assertTrue(Assert.java:140)
      	at org.apache.harmony.tests.java.lang.DoubleTest.test_compareToLjava_lang_Double(DoubleTest.java:1320)
    org.apache.harmony.tests.java.lang.DoubleTest#test_compareToLjava_lang_Double FAIL (EXEC_FAILED)

Change-Id: I10f0ec8cc9495cc225fef1940b3f1a9fe87d996f

compiler/utils/x86/assembler_x86.cc

diff --git a/compiler/utils/x86/assembler_x86.cc b/compiler/utils/x86/assembler_x86.cc
index f2541a2..329698c 100644
--- a/compiler/utils/x86/assembler_x86.cc
+++ b/compiler/utils/x86/assembler_x86.cc
@@ -1292,62 +1292,32 @@
 
 
 void X86Assembler::shll(Register reg, const Immediate& imm) {
-  EmitGenericShift(4, Operand(reg), imm);
+  EmitGenericShift(4, reg, imm);
 }
 
 
 void X86Assembler::shll(Register operand, Register shifter) {
-  EmitGenericShift(4, Operand(operand), shifter);
-}
-
-
-void X86Assembler::shll(const Address& address, const Immediate& imm) {
-  EmitGenericShift(4, address, imm);
-}
-
-
-void X86Assembler::shll(const Address& address, Register shifter) {
-  EmitGenericShift(4, address, shifter);
+  EmitGenericShift(4, operand, shifter);
 }
 
 
 void X86Assembler::shrl(Register reg, const Immediate& imm) {
-  EmitGenericShift(5, Operand(reg), imm);
+  EmitGenericShift(5, reg, imm);
 }
 
 
 void X86Assembler::shrl(Register operand, Register shifter) {
-  EmitGenericShift(5, Operand(operand), shifter);
-}
-
-
-void X86Assembler::shrl(const Address& address, const Immediate& imm) {
-  EmitGenericShift(5, address, imm);
-}
-
-
-void X86Assembler::shrl(const Address& address, Register shifter) {
-  EmitGenericShift(5, address, shifter);
+  EmitGenericShift(5, operand, shifter);
 }
 
 
 void X86Assembler::sarl(Register reg, const Immediate& imm) {
-  EmitGenericShift(7, Operand(reg), imm);
+  EmitGenericShift(7, reg, imm);
 }
 
 
 void X86Assembler::sarl(Register operand, Register shifter) {
-  EmitGenericShift(7, Operand(operand), shifter);
-}
-
-
-void X86Assembler::sarl(const Address& address, const Immediate& imm) {
-  EmitGenericShift(7, address, imm);
-}
-
-
-void X86Assembler::sarl(const Address& address, Register shifter) {
-  EmitGenericShift(7, address, shifter);
+  EmitGenericShift(7, operand, shifter);
 }
 
 
@@ -1360,15 +1330,6 @@
 }
 
 
-void X86Assembler::shld(Register dst, Register src, const Immediate& imm) {
-  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(0x0F);
-  EmitUint8(0xA4);
-  EmitRegisterOperand(src, dst);
-  EmitUint8(imm.value() & 0xFF);
-}
-
-
 void X86Assembler::shrd(Register dst, Register src, Register shifter) {
   DCHECK_EQ(ECX, shifter);
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
@@ -1378,15 +1339,6 @@
 }
 
 
-void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) {
-  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(0x0F);
-  EmitUint8(0xAC);
-  EmitRegisterOperand(src, dst);
-  EmitUint8(imm.value() & 0xFF);
-}
-
-
 void X86Assembler::negl(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF7);
@@ -1670,28 +1622,28 @@
 
 
 void X86Assembler::EmitGenericShift(int reg_or_opcode,
-                                    const Operand& operand,
+                                    Register reg,
                                     const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   CHECK(imm.is_int8());
   if (imm.value() == 1) {
     EmitUint8(0xD1);
-    EmitOperand(reg_or_opcode, operand);
+    EmitOperand(reg_or_opcode, Operand(reg));
   } else {
     EmitUint8(0xC1);
-    EmitOperand(reg_or_opcode, operand);
+    EmitOperand(reg_or_opcode, Operand(reg));
     EmitUint8(imm.value() & 0xFF);
   }
 }
 
 
 void X86Assembler::EmitGenericShift(int reg_or_opcode,
-                                    const Operand& operand,
+                                    Register operand,
                                     Register shifter) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   CHECK_EQ(shifter, ECX);
   EmitUint8(0xD3);
-  EmitOperand(reg_or_opcode, operand);
+  EmitOperand(reg_or_opcode, Operand(operand));
 }
 
 static dwarf::Reg DWARFReg(Register reg) {