commit 2cebb24bfc3247d3e9be138a3350106737455918
author Mathieu Chartier <mathieuc@google.com> Tue Apr 21 16:50:40 2015 -0700
committer Mathieu Chartier <mathieuc@google.com> Wed Apr 22 12:44:27 2015 -0700
tree d04d27d21b3c7733d784e303f01f873bb99e7770
parent 1f02f1a7b3073b8fef07770a67fbf94afad317f0

Replace NULL with nullptr

Also fixed some lines that were too long, and a few other minor
details.

Change-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb

compiler/dex/quick/mips/utility_mips.cc

diff --git a/compiler/dex/quick/mips/utility_mips.cc b/compiler/dex/quick/mips/utility_mips.cc
index 8ab5422..95c61cd 100644
--- a/compiler/dex/quick/mips/utility_mips.cc
+++ b/compiler/dex/quick/mips/utility_mips.cc
@@ -566,7 +566,7 @@
 /* Load value from base + scaled index. */
 LIR* MipsMir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest,
                                   int scale, OpSize size) {
-  LIR *first = NULL;
+  LIR *first = nullptr;
   LIR *res;
   MipsOpCode opcode = kMipsNop;
   bool is64bit = cu_->target64 && r_dest.Is64Bit();
@@ -640,7 +640,7 @@
 // Store value base base + scaled index.
 LIR* MipsMir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src,
                                    int scale, OpSize size) {
-  LIR *first = NULL;
+  LIR *first = nullptr;
   MipsOpCode opcode = kMipsNop;
   RegStorage t_reg = AllocTemp();
 
@@ -696,8 +696,8 @@
  * rlp and then restore.
  */
   LIR *res;
-  LIR *load = NULL;
-  LIR *load2 = NULL;
+  LIR *load = nullptr;
+  LIR *load2 = nullptr;
   MipsOpCode opcode = kMipsNop;
   bool short_form = IS_SIMM16(displacement);
   bool is64bit = false;
@@ -857,8 +857,8 @@
 LIR* MipsMir2Lir::StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src,
                                     OpSize size) {
   LIR *res;
-  LIR *store = NULL;
-  LIR *store2 = NULL;
+  LIR *store = nullptr;
+  LIR *store2 = nullptr;
   MipsOpCode opcode = kMipsNop;
   bool short_form = IS_SIMM16(displacement);
   bool is64bit = false;