commit 2cfc639fc803bf67e3d2a961f2b637220c86d5f7
author buzbee <buzbee@google.com> Mon May 07 14:51:40 2012 -0700
committer buzbee <buzbee@google.com> Thu Jun 07 16:29:03 2012 -0700
tree dfb184dc35b3a534fcd54a420378f29f30011f3a
parent a9719eb4167b544438268d46692389761652fc5d

Foundation for Quick LLVM compiler

Ready for review - probably better get this cleaned up and
checked in even though much work remains.

Basic conversion from MIR to GreenlandIR and from GreenlandIR
back to LIR.  Support sufficient to run Fibonacci test.

Note some structural changes in MIR to support this work:
    o  retaining incoming label for phi nodes
    o  constant propagation
    o  include object reference detection in type inference pass

Change-Id: I8ba63c73e76d071aa40cae0f744e598b96f68699

src/compiler/codegen/x86/ArchFactory.cc

diff --git a/src/compiler/codegen/x86/ArchFactory.cc b/src/compiler/codegen/x86/ArchFactory.cc
index 9e6ef09..b3cebdc 100644
--- a/src/compiler/codegen/x86/ArchFactory.cc
+++ b/src/compiler/codegen/x86/ArchFactory.cc
@@ -34,7 +34,8 @@
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpAdd, r0, r2);  // r0 = r0 + r2
   opRegReg(cUnit, kOpAdc, r1, r3);  // r1 = r1 + r3 + CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1,
+                          INVALID_SREG, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -49,7 +50,8 @@
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpSub, r0, r2);  // r0 = r0 - r2
   opRegReg(cUnit, kOpSbc, r1, r3);  // r1 = r1 - r3 - CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1,
+                          INVALID_SREG, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -64,7 +66,8 @@
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpAnd, r0, r2);  // r0 = r0 - r2
   opRegReg(cUnit, kOpAnd, r1, r3);  // r1 = r1 - r3 - CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1,
+                          INVALID_SREG, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -79,7 +82,8 @@
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpOr, r0, r2);  // r0 = r0 - r2
   opRegReg(cUnit, kOpOr, r1, r3);  // r1 = r1 - r3 - CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1,
+                          INVALID_SREG, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -94,7 +98,8 @@
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpXor, r0, r2);  // r0 = r0 - r2
   opRegReg(cUnit, kOpXor, r1, r3);  // r1 = r1 - r3 - CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1,
+                          INVALID_SREG, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -109,7 +114,8 @@
   opRegReg(cUnit, kOpNeg, r0, r0);  // r0 = -r0
   opRegImm(cUnit, kOpAdc, r1, 0);   // r1 = r1 + CF
   opRegReg(cUnit, kOpNeg, r1, r1);  // r1 = -r1
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1,
+                          INVALID_SREG, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -157,7 +163,7 @@
   newLIR2(cUnit, opcode, rDest, threadOffset);
 }
 
-void genEntrySequence(CompilationUnit* cUnit, BasicBlock* bb)
+void genEntrySequence(CompilationUnit* cUnit)
 {
   /*
    * On entry, rARG0, rARG1, rARG2 are live.  Let the register
@@ -210,7 +216,7 @@
   oatFreeTemp(cUnit, rARG2);
 }
 
-void genExitSequence(CompilationUnit* cUnit, BasicBlock* bb) {
+void genExitSequence(CompilationUnit* cUnit) {
   /*
    * In the exit path, rRET0/rRET1 are live - make sure they aren't
    * allocated by the register utilities as temps.