Use shorter opcodes on x86 for opCmpImmBranch.
Gets instruction expansion from ~5.1 to ~4.9.
Change-Id: I14719df1f256589035635edcc20e25ebd396657c
diff --git a/src/compiler/codegen/x86/X86/Factory.cc b/src/compiler/codegen/x86/X86/Factory.cc
index 9538931..291b761 100644
--- a/src/compiler/codegen/x86/X86/Factory.cc
+++ b/src/compiler/codegen/x86/X86/Factory.cc
@@ -105,6 +105,7 @@
if (value == 0) {
res = newLIR2(cUnit, kX86Xor32RR, rDest, rDest);
} else {
+ // Note, there is no byte immediate form of a 32 bit immediate move.
res = newLIR2(cUnit, kX86Mov32RI, rDest, value);
}
diff --git a/src/compiler/codegen/x86/X86/Gen.cc b/src/compiler/codegen/x86/X86/Gen.cc
index fb8bcd7..28c6914 100644
--- a/src/compiler/codegen/x86/X86/Gen.cc
+++ b/src/compiler/codegen/x86/X86/Gen.cc
@@ -312,11 +312,11 @@
LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
int checkValue, LIR* target)
{
- if (false && (checkValue == 0) && (cond == kCondEq || cond == kCondNe)) {
+ if ((checkValue == 0) && (cond == kCondEq || cond == kCondNe)) {
// TODO: when checkValue == 0 and reg is rCX, use the jcxz/nz opcode
- // newLIR2(cUnit, kX86Test32RR, reg, reg);
+ newLIR2(cUnit, kX86Test32RR, reg, reg);
} else {
- newLIR2(cUnit, kX86Cmp32RI, reg, checkValue);
+ newLIR2(cUnit, IS_SIMM8(checkValue) ? kX86Cmp32RI8 : kX86Cmp32RI, reg, checkValue);
}
X86ConditionCode cc = oatX86ConditionEncoding(cond);
LIR* branch = newLIR2(cUnit, kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc);