Merge "Revert "Revert "Avoid compiling monster methods in boot image"""
diff --git a/build/Android.common.mk b/build/Android.common.mk
index 28546e9..0522456 100644
--- a/build/Android.common.mk
+++ b/build/Android.common.mk
@@ -119,6 +119,7 @@
external/gtest/include \
external/valgrind/main/include \
external/valgrind/main \
+ external/vixl/src \
external/zlib \
frameworks/compile/mclinker/include
diff --git a/build/Android.gtest.mk b/build/Android.gtest.mk
index 6907603..19748a8 100644
--- a/build/Android.gtest.mk
+++ b/build/Android.gtest.mk
@@ -68,12 +68,14 @@
compiler/image_test.cc \
compiler/jni/jni_compiler_test.cc \
compiler/oat_test.cc \
+ compiler/optimizing/codegen_test.cc \
compiler/optimizing/dominator_test.cc \
compiler/optimizing/pretty_printer_test.cc \
compiler/output_stream_test.cc \
compiler/utils/arena_allocator_test.cc \
compiler/utils/dedupe_set_test.cc \
compiler/utils/arm/managed_register_arm_test.cc \
+ compiler/utils/arm64/managed_register_arm64_test.cc \
compiler/utils/x86/managed_register_x86_test.cc \
ifeq ($(ART_SEA_IR_MODE),true)
diff --git a/compiler/Android.mk b/compiler/Android.mk
index 2f785ce..499f23f 100644
--- a/compiler/Android.mk
+++ b/compiler/Android.mk
@@ -70,12 +70,17 @@
jni/quick/calling_convention.cc \
jni/quick/jni_compiler.cc \
optimizing/builder.cc \
+ optimizing/code_generator.cc \
+ optimizing/code_generator_arm.cc \
+ optimizing/code_generator_x86.cc \
optimizing/nodes.cc \
trampolines/trampoline_compiler.cc \
utils/arena_allocator.cc \
utils/arena_bit_vector.cc \
utils/arm/assembler_arm.cc \
utils/arm/managed_register_arm.cc \
+ utils/arm64/assembler_arm64.cc \
+ utils/arm64/managed_register_arm64.cc \
utils/assembler.cc \
utils/mips/assembler_mips.cc \
utils/mips/managed_register_mips.cc \
@@ -220,7 +225,7 @@
LOCAL_STATIC_LIBRARIES += libmcldMipsInfo libmcldMipsTarget
include $(LLVM_HOST_BUILD_MK)
endif
- LOCAL_STATIC_LIBRARIES += libmcldCore libmcldObject libmcldADT libmcldFragment libmcldTarget libmcldCodeGen libmcldLDVariant libmcldMC libmcldSupport libmcldLD
+ LOCAL_STATIC_LIBRARIES += libmcldCore libmcldObject libmcldADT libmcldFragment libmcldTarget libmcldCodeGen libmcldLDVariant libmcldMC libmcldSupport libmcldLD libmcldScript
include $(LLVM_GEN_INTRINSICS_MK)
endif
@@ -232,10 +237,10 @@
LOCAL_ADDITIONAL_DEPENDENCIES := art/build/Android.common.mk
LOCAL_ADDITIONAL_DEPENDENCIES += $(LOCAL_PATH)/Android.mk
ifeq ($$(art_target_or_host),target)
- LOCAL_SHARED_LIBRARIES += libcutils
+ LOCAL_SHARED_LIBRARIES += libcutils libvixl
include $(BUILD_SHARED_LIBRARY)
else # host
- LOCAL_STATIC_LIBRARIES += libcutils
+ LOCAL_STATIC_LIBRARIES += libcutils libvixl
include $(BUILD_HOST_SHARED_LIBRARY)
endif
diff --git a/compiler/dex/quick/gen_invoke.cc b/compiler/dex/quick/gen_invoke.cc
index dd3d466..2f017c8 100644
--- a/compiler/dex/quick/gen_invoke.cc
+++ b/compiler/dex/quick/gen_invoke.cc
@@ -1251,12 +1251,12 @@
RegLocation rl_obj = info->args[0];
RegLocation rl_char = info->args[1];
- RegLocation rl_start = info->args[2];
LoadValueDirectFixed(rl_obj, reg_ptr);
LoadValueDirectFixed(rl_char, reg_char);
if (zero_based) {
LoadConstant(reg_start, 0);
} else {
+ RegLocation rl_start = info->args[2]; // 3rd arg only present in III flavor of IndexOf.
LoadValueDirectFixed(rl_start, reg_start);
}
int r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pIndexOf));
diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc
index ef8be3c..78a2169 100644
--- a/compiler/dex/quick/x86/target_x86.cc
+++ b/compiler/dex/quick/x86/target_x86.cc
@@ -948,7 +948,7 @@
RegLocation rl_obj = info->args[0];
RegLocation rl_char = info->args[1];
- RegLocation rl_start = info->args[2];
+ RegLocation rl_start; // Note: only present in III flavor or IndexOf.
uint32_t char_value =
rl_char.is_const ? mir_graph_->ConstantValue(rl_char.orig_sreg) : 0;
@@ -1007,6 +1007,7 @@
// We have to handle an empty string. Use special instruction JECXZ.
length_compare = NewLIR0(kX86Jecxz8);
} else {
+ rl_start = info->args[2];
// We have to offset by the start index.
if (rl_start.is_const) {
start_value = mir_graph_->ConstantValue(rl_start.orig_sreg);
diff --git a/compiler/elf_writer_mclinker.cc b/compiler/elf_writer_mclinker.cc
index b2d3a69..f688103 100644
--- a/compiler/elf_writer_mclinker.cc
+++ b/compiler/elf_writer_mclinker.cc
@@ -33,6 +33,7 @@
#include "class_linker.h"
#include "dex_method_iterator.h"
#include "driver/compiler_driver.h"
+#include "elf_file.h"
#include "globals.h"
#include "mirror/art_method.h"
#include "mirror/art_method-inl.h"
@@ -176,7 +177,7 @@
mcld::LDSection* null_section = ir_builder_->CreateELFHeader(*oat_input_,
"",
mcld::LDFileFormat::Null,
- llvm::ELF::SHT_NULL,
+ SHT_NULL,
0);
CHECK(null_section != NULL);
@@ -194,9 +195,8 @@
// TODO: ownership of text_section?
mcld::LDSection* text_section = ir_builder_->CreateELFHeader(*oat_input_,
".text",
- llvm::ELF::SHT_PROGBITS,
- llvm::ELF::SHF_EXECINSTR
- | llvm::ELF::SHF_ALLOC,
+ SHT_PROGBITS,
+ SHF_EXECINSTR | SHF_ALLOC,
alignment);
CHECK(text_section != NULL);
@@ -336,7 +336,7 @@
PLOG(ERROR) << "Failed to dup file descriptor for " << elf_file_->GetPath();
return false;
}
- if (!linker_->emit(fd)) {
+ if (!linker_->emit(*module_.get(), fd)) {
LOG(ERROR) << "Failed to emit " << elf_file_->GetPath();
return false;
}
@@ -350,7 +350,7 @@
UniquePtr<ElfFile> elf_file(ElfFile::Open(elf_file_, true, false, &error_msg));
CHECK(elf_file.get() != NULL) << elf_file_->GetPath() << ": " << error_msg;
- llvm::ELF::Elf32_Addr oatdata_address = GetOatDataAddress(elf_file.get());
+ uint32_t oatdata_address = GetOatDataAddress(elf_file.get());
DexMethodIterator it(dex_files);
while (it.HasNext()) {
const DexFile& dex_file = it.GetDexFile();
@@ -384,7 +384,7 @@
}
uint32_t ElfWriterMclinker::FixupCompiledCodeOffset(ElfFile& elf_file,
- llvm::ELF::Elf32_Addr oatdata_address,
+ Elf32_Addr oatdata_address,
const CompiledCode& compiled_code) {
const std::string& symbol = compiled_code.GetSymbol();
SafeMap<const std::string*, uint32_t>::iterator it = symbol_to_compiled_code_offset_.find(&symbol);
@@ -392,9 +392,9 @@
return it->second;
}
- llvm::ELF::Elf32_Addr compiled_code_address = elf_file.FindSymbolAddress(llvm::ELF::SHT_SYMTAB,
- symbol,
- true);
+ Elf32_Addr compiled_code_address = elf_file.FindSymbolAddress(SHT_SYMTAB,
+ symbol,
+ true);
CHECK_NE(0U, compiled_code_address) << symbol;
CHECK_LT(oatdata_address, compiled_code_address) << symbol;
uint32_t compiled_code_offset = compiled_code_address - oatdata_address;
diff --git a/compiler/oat_writer.cc b/compiler/oat_writer.cc
index 186ab38..5394bbc 100644
--- a/compiler/oat_writer.cc
+++ b/compiler/oat_writer.cc
@@ -1014,6 +1014,7 @@
}
OatWriter::OatClass::~OatClass() {
+ delete method_bitmap_;
delete compiled_methods_;
}
diff --git a/compiler/optimizing/builder.cc b/compiler/optimizing/builder.cc
index e6db7bc..f78e56b 100644
--- a/compiler/optimizing/builder.cc
+++ b/compiler/optimizing/builder.cc
@@ -29,6 +29,8 @@
entry_block_->AddInstruction(new (arena_) HGoto());
exit_block_ = new (arena_) HBasicBlock(graph_);
exit_block_->AddInstruction(new (arena_) HExit());
+ graph_->set_entry_block(entry_block_);
+ graph_->set_exit_block(exit_block_);
// To avoid splitting blocks, we compute ahead of time the instructions that
// start a new block, and create these blocks.
diff --git a/compiler/optimizing/code_generator.cc b/compiler/optimizing/code_generator.cc
new file mode 100644
index 0000000..01fc23b
--- /dev/null
+++ b/compiler/optimizing/code_generator.cc
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "code_generator.h"
+
+#include "code_generator_arm.h"
+#include "code_generator_x86.h"
+#include "utils/assembler.h"
+#include "utils/arm/assembler_arm.h"
+#include "utils/mips/assembler_mips.h"
+#include "utils/x86/assembler_x86.h"
+
+namespace art {
+
+void CodeGenerator::Compile(CodeAllocator* allocator) {
+ GenerateFrameEntry();
+ const GrowableArray<HBasicBlock*>* blocks = graph()->blocks();
+ for (size_t i = 0; i < blocks->Size(); i++) {
+ CompileBlock(blocks->Get(i));
+ }
+ size_t code_size = assembler_->CodeSize();
+ uint8_t* buffer = allocator->Allocate(code_size);
+ MemoryRegion code(buffer, code_size);
+ assembler_->FinalizeInstructions(code);
+}
+
+void CodeGenerator::CompileBlock(HBasicBlock* block) {
+ Bind(GetLabelOf(block));
+ for (HInstructionIterator it(block); !it.Done(); it.Advance()) {
+ it.Current()->Accept(this);
+ }
+}
+
+bool CodeGenerator::GoesToNextBlock(HGoto* goto_instruction) const {
+ HBasicBlock* successor = goto_instruction->GetSuccessor();
+ // We currently iterate over the block in insertion order.
+ return goto_instruction->block()->block_id() + 1 == successor->block_id();
+}
+
+Label* CodeGenerator::GetLabelOf(HBasicBlock* block) const {
+ return block_labels_.GetRawStorage() + block->block_id();
+}
+
+bool CodeGenerator::CompileGraph(HGraph* graph,
+ InstructionSet instruction_set,
+ CodeAllocator* allocator) {
+ switch (instruction_set) {
+ case kArm:
+ case kThumb2: {
+ arm::ArmAssembler assembler;
+ arm::CodeGeneratorARM(&assembler, graph).Compile(allocator);
+ return true;
+ }
+ case kMips:
+ return false;
+ case kX86: {
+ x86::X86Assembler assembler;
+ x86::CodeGeneratorX86(&assembler, graph).Compile(allocator);
+ return true;
+ }
+ default:
+ return false;
+ }
+}
+
+} // namespace art
diff --git a/compiler/optimizing/code_generator.h b/compiler/optimizing/code_generator.h
new file mode 100644
index 0000000..2a5ae7d
--- /dev/null
+++ b/compiler/optimizing/code_generator.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ART_COMPILER_OPTIMIZING_CODE_GENERATOR_H_
+#define ART_COMPILER_OPTIMIZING_CODE_GENERATOR_H_
+
+#include "instruction_set.h"
+#include "memory_region.h"
+#include "nodes.h"
+#include "utils/assembler.h"
+
+namespace art {
+
+class CodeAllocator {
+ public:
+ CodeAllocator() { }
+ virtual ~CodeAllocator() { }
+
+ virtual uint8_t* Allocate(size_t size) = 0;
+
+ private:
+ DISALLOW_COPY_AND_ASSIGN(CodeAllocator);
+};
+
+class CodeGenerator : public HGraphVisitor {
+ public:
+ // Compiles the graph to executable instructions. Returns whether the compilation
+ // succeeded.
+ static bool CompileGraph(
+ HGraph* graph, InstructionSet instruction_set, CodeAllocator* allocator);
+
+ Assembler* assembler() const { return assembler_; }
+
+ // Visit functions for instruction classes.
+#define DECLARE_VISIT_INSTRUCTION(name) \
+ virtual void Visit##name(H##name* instr) = 0;
+
+ FOR_EACH_INSTRUCTION(DECLARE_VISIT_INSTRUCTION)
+
+#undef DECLARE_VISIT_INSTRUCTION
+
+ protected:
+ CodeGenerator(Assembler* assembler, HGraph* graph)
+ : HGraphVisitor(graph), assembler_(assembler), block_labels_(graph->arena(), 0) {
+ block_labels_.SetSize(graph->blocks()->Size());
+ }
+
+ Label* GetLabelOf(HBasicBlock* block) const;
+ bool GoesToNextBlock(HGoto* got) const;
+
+ private:
+ virtual void GenerateFrameEntry() = 0;
+ virtual void GenerateFrameExit() = 0;
+ virtual void Bind(Label* label) = 0;
+
+ void Compile(CodeAllocator* allocator);
+ void CompileBlock(HBasicBlock* block);
+
+ Assembler* const assembler_;
+
+ // Labels for each block that will be compiled.
+ GrowableArray<Label> block_labels_;
+
+ DISALLOW_COPY_AND_ASSIGN(CodeGenerator);
+};
+
+} // namespace art
+
+#endif // ART_COMPILER_OPTIMIZING_CODE_GENERATOR_H_
diff --git a/compiler/optimizing/code_generator_arm.cc b/compiler/optimizing/code_generator_arm.cc
new file mode 100644
index 0000000..99bbaa0
--- /dev/null
+++ b/compiler/optimizing/code_generator_arm.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "code_generator_arm.h"
+#include "utils/assembler.h"
+#include "utils/arm/assembler_arm.h"
+
+#define __ reinterpret_cast<ArmAssembler*>(assembler())->
+
+namespace art {
+namespace arm {
+
+void CodeGeneratorARM::GenerateFrameEntry() {
+ RegList registers = (1 << LR) | (1 << FP);
+ __ PushList(registers);
+}
+
+void CodeGeneratorARM::GenerateFrameExit() {
+ RegList registers = (1 << PC) | (1 << FP);
+ __ PopList(registers);
+}
+
+void CodeGeneratorARM::Bind(Label* label) {
+ __ Bind(label);
+}
+
+void CodeGeneratorARM::VisitGoto(HGoto* got) {
+ HBasicBlock* successor = got->GetSuccessor();
+ if (graph()->exit_block() == successor) {
+ GenerateFrameExit();
+ } else if (!GoesToNextBlock(got)) {
+ __ b(GetLabelOf(successor));
+ }
+}
+
+void CodeGeneratorARM::VisitExit(HExit* exit) {
+ if (kIsDebugBuild) {
+ __ Comment("Unreachable");
+ __ bkpt(0);
+ }
+}
+
+void CodeGeneratorARM::VisitIf(HIf* if_instr) {
+ LOG(FATAL) << "UNIMPLEMENTED";
+}
+
+void CodeGeneratorARM::VisitReturnVoid(HReturnVoid* ret) {
+ GenerateFrameExit();
+}
+
+} // namespace arm
+} // namespace art
diff --git a/compiler/optimizing/code_generator_arm.h b/compiler/optimizing/code_generator_arm.h
new file mode 100644
index 0000000..27a83b8
--- /dev/null
+++ b/compiler/optimizing/code_generator_arm.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM_H_
+#define ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM_H_
+
+#include "code_generator.h"
+#include "nodes.h"
+
+namespace art {
+
+class Assembler;
+class Label;
+
+namespace arm {
+
+class CodeGeneratorARM : public CodeGenerator {
+ public:
+ CodeGeneratorARM(Assembler* assembler, HGraph* graph)
+ : CodeGenerator(assembler, graph) { }
+
+ // Visit functions for instruction classes.
+#define DECLARE_VISIT_INSTRUCTION(name) \
+ virtual void Visit##name(H##name* instr);
+
+ FOR_EACH_INSTRUCTION(DECLARE_VISIT_INSTRUCTION)
+
+#undef DECLARE_VISIT_INSTRUCTION
+
+ private:
+ virtual void GenerateFrameEntry();
+ virtual void GenerateFrameExit();
+ virtual void Bind(Label* label);
+
+ DISALLOW_COPY_AND_ASSIGN(CodeGeneratorARM);
+};
+
+} // namespace arm
+} // namespace art
+
+#endif // ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM_H_
diff --git a/compiler/optimizing/code_generator_x86.cc b/compiler/optimizing/code_generator_x86.cc
new file mode 100644
index 0000000..1facfd7
--- /dev/null
+++ b/compiler/optimizing/code_generator_x86.cc
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "code_generator_x86.h"
+#include "utils/assembler.h"
+#include "utils/x86/assembler_x86.h"
+
+#define __ reinterpret_cast<X86Assembler*>(assembler())->
+
+namespace art {
+namespace x86 {
+
+void CodeGeneratorX86::GenerateFrameEntry() {
+ __ pushl(EBP);
+ __ movl(EBP, ESP);
+}
+
+void CodeGeneratorX86::GenerateFrameExit() {
+ __ movl(ESP, EBP);
+ __ popl(EBP);
+}
+
+void CodeGeneratorX86::Bind(Label* label) {
+ __ Bind(label);
+}
+
+void CodeGeneratorX86::VisitGoto(HGoto* got) {
+ HBasicBlock* successor = got->GetSuccessor();
+ if (graph()->exit_block() == successor) {
+ GenerateFrameExit();
+ } else if (!GoesToNextBlock(got)) {
+ __ jmp(GetLabelOf(successor));
+ }
+}
+
+void CodeGeneratorX86::VisitExit(HExit* exit) {
+ if (kIsDebugBuild) {
+ __ Comment("Unreachable");
+ __ int3();
+ }
+}
+
+void CodeGeneratorX86::VisitIf(HIf* if_instr) {
+ LOG(FATAL) << "UNIMPLEMENTED";
+}
+
+void CodeGeneratorX86::VisitReturnVoid(HReturnVoid* ret) {
+ GenerateFrameExit();
+ __ ret();
+}
+
+} // namespace x86
+} // namespace art
diff --git a/compiler/optimizing/code_generator_x86.h b/compiler/optimizing/code_generator_x86.h
new file mode 100644
index 0000000..7dae2ab
--- /dev/null
+++ b/compiler/optimizing/code_generator_x86.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ART_COMPILER_OPTIMIZING_CODE_GENERATOR_X86_H_
+#define ART_COMPILER_OPTIMIZING_CODE_GENERATOR_X86_H_
+
+#include "code_generator.h"
+#include "nodes.h"
+
+namespace art {
+
+class Assembler;
+class Label;
+
+namespace x86 {
+
+class CodeGeneratorX86 : public CodeGenerator {
+ public:
+ CodeGeneratorX86(Assembler* assembler, HGraph* graph)
+ : CodeGenerator(assembler, graph) { }
+
+ // Visit functions for instruction classes.
+#define DECLARE_VISIT_INSTRUCTION(name) \
+ virtual void Visit##name(H##name* instr);
+
+ FOR_EACH_INSTRUCTION(DECLARE_VISIT_INSTRUCTION)
+
+#undef DECLARE_VISIT_INSTRUCTION
+
+ private:
+ virtual void GenerateFrameEntry();
+ virtual void GenerateFrameExit();
+ virtual void Bind(Label* label);
+
+ DISALLOW_COPY_AND_ASSIGN(CodeGeneratorX86);
+};
+
+} // namespace x86
+} // namespace art
+
+#endif // ART_COMPILER_OPTIMIZING_CODE_GENERATOR_X86_H_
diff --git a/compiler/optimizing/codegen_test.cc b/compiler/optimizing/codegen_test.cc
new file mode 100644
index 0000000..dc4999b
--- /dev/null
+++ b/compiler/optimizing/codegen_test.cc
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "builder.h"
+#include "code_generator.h"
+#include "common_compiler_test.h"
+#include "dex_instruction.h"
+#include "instruction_set.h"
+#include "nodes.h"
+
+#include "gtest/gtest.h"
+
+namespace art {
+
+class ExecutableMemoryAllocator : public CodeAllocator {
+ public:
+ ExecutableMemoryAllocator() { }
+
+ virtual uint8_t* Allocate(size_t size) {
+ memory_.reset(new uint8_t[size]);
+ CommonCompilerTest::MakeExecutable(memory_.get(), size);
+ return memory_.get();
+ }
+
+ uint8_t* memory() const { return memory_.get(); }
+
+ private:
+ UniquePtr<uint8_t[]> memory_;
+
+ DISALLOW_COPY_AND_ASSIGN(ExecutableMemoryAllocator);
+};
+
+static void TestCode(const uint16_t* data, int length) {
+ ArenaPool pool;
+ ArenaAllocator arena(&pool);
+ HGraphBuilder builder(&arena);
+ HGraph* graph = builder.BuildGraph(data, data + length);
+ ASSERT_NE(graph, nullptr);
+ ExecutableMemoryAllocator allocator;
+ CHECK(CodeGenerator::CompileGraph(graph, kX86, &allocator));
+ typedef void (*fptr)();
+#if defined(__i386__)
+ reinterpret_cast<fptr>(allocator.memory())();
+#endif
+ CHECK(CodeGenerator::CompileGraph(graph, kArm, &allocator));
+#if defined(__arm__)
+ reinterpret_cast<fptr>(allocator.memory())();
+#endif
+}
+
+TEST(CodegenTest, ReturnVoid) {
+ const uint16_t data[] = { Instruction::RETURN_VOID };
+ TestCode(data, sizeof(data) / sizeof(uint16_t));
+}
+
+TEST(PrettyPrinterTest, CFG1) {
+ const uint16_t data[] = {
+ Instruction::GOTO | 0x100,
+ Instruction::RETURN_VOID
+ };
+
+ TestCode(data, sizeof(data) / sizeof(uint16_t));
+}
+
+TEST(PrettyPrinterTest, CFG2) {
+ const uint16_t data[] = {
+ Instruction::GOTO | 0x100,
+ Instruction::GOTO | 0x100,
+ Instruction::RETURN_VOID
+ };
+
+ TestCode(data, sizeof(data) / sizeof(uint16_t));
+}
+
+TEST(PrettyPrinterTest, CFG3) {
+ const uint16_t data1[] = {
+ Instruction::GOTO | 0x200,
+ Instruction::RETURN_VOID,
+ Instruction::GOTO | 0xFF00
+ };
+
+ TestCode(data1, sizeof(data1) / sizeof(uint16_t));
+
+ const uint16_t data2[] = {
+ Instruction::GOTO_16, 3,
+ Instruction::RETURN_VOID,
+ Instruction::GOTO_16, 0xFFFF
+ };
+
+ TestCode(data2, sizeof(data2) / sizeof(uint16_t));
+
+ const uint16_t data3[] = {
+ Instruction::GOTO_32, 4, 0,
+ Instruction::RETURN_VOID,
+ Instruction::GOTO_32, 0xFFFF, 0xFFFF
+ };
+
+ TestCode(data3, sizeof(data3) / sizeof(uint16_t));
+}
+
+TEST(PrettyPrinterTest, CFG4) {
+ const uint16_t data[] = {
+ Instruction::RETURN_VOID,
+ Instruction::GOTO | 0x100,
+ Instruction::GOTO | 0xFE00
+ };
+
+ TestCode(data, sizeof(data) / sizeof(uint16_t));
+}
+
+} // namespace art
diff --git a/compiler/optimizing/nodes.cc b/compiler/optimizing/nodes.cc
index 9ec8e89..aefb089 100644
--- a/compiler/optimizing/nodes.cc
+++ b/compiler/optimizing/nodes.cc
@@ -26,7 +26,7 @@
void HGraph::FindBackEdges(ArenaBitVector* visited) const {
ArenaBitVector visiting(arena_, blocks_.Size(), false);
- VisitBlockForBackEdges(GetEntryBlock(), visited, &visiting);
+ VisitBlockForBackEdges(entry_block_, visited, &visiting);
}
void HGraph::RemoveDeadBlocks(const ArenaBitVector& visited) const {
@@ -75,10 +75,9 @@
// have been processed.
GrowableArray<size_t> visits(arena_, blocks_.Size());
visits.SetSize(blocks_.Size());
- HBasicBlock* entry = GetEntryBlock();
- dominator_order_.Add(entry);
- for (size_t i = 0; i < entry->successors()->Size(); i++) {
- VisitBlockForDominatorTree(entry->successors()->Get(i), entry, &visits);
+ dominator_order_.Add(entry_block_);
+ for (size_t i = 0; i < entry_block_->successors()->Size(); i++) {
+ VisitBlockForDominatorTree(entry_block_->successors()->Get(i), entry_block_, &visits);
}
}
@@ -122,6 +121,7 @@
}
void HBasicBlock::AddInstruction(HInstruction* instruction) {
+ instruction->set_block(this);
if (first_instruction_ == nullptr) {
DCHECK(last_instruction_ == nullptr);
first_instruction_ = last_instruction_ = instruction;
diff --git a/compiler/optimizing/nodes.h b/compiler/optimizing/nodes.h
index 3d5d531..46fe95e 100644
--- a/compiler/optimizing/nodes.h
+++ b/compiler/optimizing/nodes.h
@@ -43,6 +43,13 @@
ArenaAllocator* arena() const { return arena_; }
const GrowableArray<HBasicBlock*>* blocks() const { return &blocks_; }
+ HBasicBlock* entry_block() const { return entry_block_; }
+ HBasicBlock* exit_block() const { return exit_block_; }
+
+ void set_entry_block(HBasicBlock* block) { entry_block_ = block; }
+ void set_exit_block(HBasicBlock* block) { exit_block_ = block; }
+
+
void AddBlock(HBasicBlock* block);
void BuildDominatorTree();
@@ -57,8 +64,6 @@
ArenaBitVector* visiting) const;
void RemoveDeadBlocks(const ArenaBitVector& visited) const;
- HBasicBlock* GetEntryBlock() const { return blocks_.Get(0); }
-
ArenaAllocator* const arena_;
// List of blocks in insertion order.
@@ -67,6 +72,9 @@
// List of blocks to perform a pre-order dominator tree traversal.
GrowableArray<HBasicBlock*> dominator_order_;
+ HBasicBlock* entry_block_;
+ HBasicBlock* exit_block_;
+
DISALLOW_COPY_AND_ASSIGN(HGraph);
};
@@ -174,12 +182,15 @@
class HInstruction : public ArenaObject {
public:
- HInstruction() : previous_(nullptr), next_(nullptr) { }
+ HInstruction() : previous_(nullptr), next_(nullptr), block_(nullptr) { }
virtual ~HInstruction() { }
HInstruction* next() const { return next_; }
HInstruction* previous() const { return previous_; }
+ HBasicBlock* block() const { return block_; }
+ void set_block(HBasicBlock* block) { block_ = block; }
+
virtual intptr_t InputCount() const = 0;
virtual HInstruction* InputAt(intptr_t i) const = 0;
@@ -189,6 +200,7 @@
private:
HInstruction* previous_;
HInstruction* next_;
+ HBasicBlock* block_;
friend class HBasicBlock;
@@ -304,6 +316,10 @@
public:
HGoto() { }
+ HBasicBlock* GetSuccessor() const {
+ return block()->successors()->Get(0);
+ }
+
DECLARE_INSTRUCTION(Goto)
private:
@@ -333,6 +349,8 @@
void VisitInsertionOrder();
+ HGraph* graph() const { return graph_; }
+
// Visit functions for instruction classes.
#define DECLARE_VISIT_INSTRUCTION(name) \
virtual void Visit##name(H##name* instr) { VisitInstruction(instr); }
diff --git a/compiler/utils/arena_allocator.cc b/compiler/utils/arena_allocator.cc
index ec41293..00c3c57 100644
--- a/compiler/utils/arena_allocator.cc
+++ b/compiler/utils/arena_allocator.cc
@@ -112,7 +112,7 @@
void ArenaPool::FreeArena(Arena* arena) {
Thread* self = Thread::Current();
- if (UNLIKELY(RUNNING_ON_VALGRIND)) {
+ if (UNLIKELY(RUNNING_ON_VALGRIND > 0)) {
VALGRIND_MAKE_MEM_UNDEFINED(arena->memory_, arena->bytes_allocated_);
}
{
@@ -137,7 +137,7 @@
ptr_(nullptr),
arena_head_(nullptr),
num_allocations_(0),
- running_on_valgrind_(RUNNING_ON_VALGRIND) {
+ running_on_valgrind_(RUNNING_ON_VALGRIND > 0) {
memset(&alloc_stats_[0], 0, sizeof(alloc_stats_));
}
diff --git a/compiler/utils/arm64/assembler_arm64.cc b/compiler/utils/arm64/assembler_arm64.cc
new file mode 100644
index 0000000..b364ba0
--- /dev/null
+++ b/compiler/utils/arm64/assembler_arm64.cc
@@ -0,0 +1,616 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "assembler_arm64.h"
+#include "base/logging.h"
+#include "entrypoints/quick/quick_entrypoints.h"
+#include "offsets.h"
+#include "thread.h"
+#include "utils.h"
+
+namespace art {
+namespace arm64 {
+
+#ifdef ___
+#error "ARM64 Assembler macro already defined."
+#else
+#define ___ vixl_masm_->
+#endif
+
+void Arm64Assembler::EmitSlowPaths() {
+ if (!exception_blocks_.empty()) {
+ for (size_t i = 0; i < exception_blocks_.size(); i++) {
+ EmitExceptionPoll(exception_blocks_.at(i));
+ }
+ }
+ ___ FinalizeCode();
+}
+
+size_t Arm64Assembler::CodeSize() const {
+ return ___ SizeOfCodeGenerated();
+}
+
+void Arm64Assembler::FinalizeInstructions(const MemoryRegion& region) {
+ // Copy the instructions from the buffer.
+ MemoryRegion from(reinterpret_cast<void*>(vixl_buf_), CodeSize());
+ region.CopyFrom(0, from);
+}
+
+void Arm64Assembler::GetCurrentThread(ManagedRegister tr) {
+ ___ Mov(reg_x(tr.AsArm64().AsCoreRegister()), reg_x(TR));
+}
+
+void Arm64Assembler::GetCurrentThread(FrameOffset offset, ManagedRegister /* scratch */) {
+ StoreToOffset(TR, SP, offset.Int32Value());
+}
+
+// See Arm64 PCS Section 5.2.2.1.
+void Arm64Assembler::IncreaseFrameSize(size_t adjust) {
+ CHECK_ALIGNED(adjust, kStackAlignment);
+ AddConstant(SP, -adjust);
+}
+
+// See Arm64 PCS Section 5.2.2.1.
+void Arm64Assembler::DecreaseFrameSize(size_t adjust) {
+ CHECK_ALIGNED(adjust, kStackAlignment);
+ AddConstant(SP, adjust);
+}
+
+void Arm64Assembler::AddConstant(Register rd, int32_t value, Condition cond) {
+ AddConstant(rd, rd, value, cond);
+}
+
+void Arm64Assembler::AddConstant(Register rd, Register rn, int32_t value,
+ Condition cond) {
+ if ((cond == AL) || (cond == NV)) {
+ // VIXL macro-assembler handles all variants.
+ ___ Add(reg_x(rd), reg_x(rn), value);
+ } else {
+ // ip1 = rd + value
+ // rd = cond ? ip1 : rn
+ CHECK_NE(rn, IP1);
+ ___ Add(reg_x(IP1), reg_x(rn), value);
+ ___ Csel(reg_x(rd), reg_x(IP1), reg_x(rd), COND_OP(cond));
+ }
+}
+
+void Arm64Assembler::StoreWToOffset(StoreOperandType type, WRegister source,
+ Register base, int32_t offset) {
+ switch (type) {
+ case kStoreByte:
+ ___ Strb(reg_w(source), MEM_OP(reg_x(base), offset));
+ break;
+ case kStoreHalfword:
+ ___ Strh(reg_w(source), MEM_OP(reg_x(base), offset));
+ break;
+ case kStoreWord:
+ ___ Str(reg_w(source), MEM_OP(reg_x(base), offset));
+ break;
+ default:
+ LOG(FATAL) << "UNREACHABLE";
+ }
+}
+
+void Arm64Assembler::StoreToOffset(Register source, Register base, int32_t offset) {
+ CHECK_NE(source, SP);
+ ___ Str(reg_x(source), MEM_OP(reg_x(base), offset));
+}
+
+void Arm64Assembler::StoreSToOffset(SRegister source, Register base, int32_t offset) {
+ ___ Str(reg_s(source), MEM_OP(reg_x(base), offset));
+}
+
+void Arm64Assembler::StoreDToOffset(DRegister source, Register base, int32_t offset) {
+ ___ Str(reg_d(source), MEM_OP(reg_x(base), offset));
+}
+
+void Arm64Assembler::Store(FrameOffset offs, ManagedRegister m_src, size_t size) {
+ Arm64ManagedRegister src = m_src.AsArm64();
+ if (src.IsNoRegister()) {
+ CHECK_EQ(0u, size);
+ } else if (src.IsWRegister()) {
+ CHECK_EQ(4u, size);
+ StoreWToOffset(kStoreWord, src.AsWRegister(), SP, offs.Int32Value());
+ } else if (src.IsCoreRegister()) {
+ CHECK_EQ(8u, size);
+ StoreToOffset(src.AsCoreRegister(), SP, offs.Int32Value());
+ } else if (src.IsSRegister()) {
+ StoreSToOffset(src.AsSRegister(), SP, offs.Int32Value());
+ } else {
+ CHECK(src.IsDRegister()) << src;
+ StoreDToOffset(src.AsDRegister(), SP, offs.Int32Value());
+ }
+}
+
+void Arm64Assembler::StoreRef(FrameOffset offs, ManagedRegister m_src) {
+ Arm64ManagedRegister src = m_src.AsArm64();
+ CHECK(src.IsCoreRegister()) << src;
+ StoreToOffset(src.AsCoreRegister(), SP, offs.Int32Value());
+}
+
+void Arm64Assembler::StoreRawPtr(FrameOffset offs, ManagedRegister m_src) {
+ Arm64ManagedRegister src = m_src.AsArm64();
+ CHECK(src.IsCoreRegister()) << src;
+ StoreToOffset(src.AsCoreRegister(), SP, offs.Int32Value());
+}
+
+void Arm64Assembler::StoreImmediateToFrame(FrameOffset offs, uint32_t imm,
+ ManagedRegister m_scratch) {
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ CHECK(scratch.IsCoreRegister()) << scratch;
+ LoadImmediate(scratch.AsCoreRegister(), imm);
+ StoreToOffset(scratch.AsCoreRegister(), SP, offs.Int32Value());
+}
+
+void Arm64Assembler::StoreImmediateToThread(ThreadOffset offs, uint32_t imm,
+ ManagedRegister m_scratch) {
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ CHECK(scratch.IsCoreRegister()) << scratch;
+ LoadImmediate(scratch.AsCoreRegister(), imm);
+ StoreToOffset(scratch.AsCoreRegister(), TR, offs.Int32Value());
+}
+
+void Arm64Assembler::StoreStackOffsetToThread(ThreadOffset tr_offs,
+ FrameOffset fr_offs,
+ ManagedRegister m_scratch) {
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ CHECK(scratch.IsCoreRegister()) << scratch;
+ AddConstant(scratch.AsCoreRegister(), SP, fr_offs.Int32Value());
+ StoreToOffset(scratch.AsCoreRegister(), TR, tr_offs.Int32Value());
+}
+
+void Arm64Assembler::StoreStackPointerToThread(ThreadOffset tr_offs) {
+ // Arm64 does not support: "str sp, [dest]" therefore we use IP1 as a temp reg.
+ ___ Mov(reg_x(IP1), reg_x(SP));
+ StoreToOffset(IP1, TR, tr_offs.Int32Value());
+}
+
+void Arm64Assembler::StoreSpanning(FrameOffset dest_off, ManagedRegister m_source,
+ FrameOffset in_off, ManagedRegister m_scratch) {
+ Arm64ManagedRegister source = m_source.AsArm64();
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ StoreToOffset(source.AsCoreRegister(), SP, dest_off.Int32Value());
+ LoadFromOffset(scratch.AsCoreRegister(), SP, in_off.Int32Value());
+ StoreToOffset(scratch.AsCoreRegister(), SP, dest_off.Int32Value() + 8);
+}
+
+// Load routines.
+void Arm64Assembler::LoadImmediate(Register dest, int32_t value,
+ Condition cond) {
+ if ((cond == AL) || (cond == NV)) {
+ ___ Mov(reg_x(dest), value);
+ } else {
+ // ip1 = value
+ // rd = cond ? ip1 : rd
+ if (value != 0) {
+ CHECK_NE(dest, IP1);
+ ___ Mov(reg_x(IP1), value);
+ ___ Csel(reg_x(dest), reg_x(IP1), reg_x(dest), COND_OP(cond));
+ } else {
+ ___ Csel(reg_x(dest), reg_x(XZR), reg_x(dest), COND_OP(cond));
+ }
+ }
+}
+
+void Arm64Assembler::LoadWFromOffset(LoadOperandType type, WRegister dest,
+ Register base, int32_t offset) {
+ switch (type) {
+ case kLoadSignedByte:
+ ___ Ldrsb(reg_w(dest), MEM_OP(reg_x(base), offset));
+ break;
+ case kLoadSignedHalfword:
+ ___ Ldrsh(reg_w(dest), MEM_OP(reg_x(base), offset));
+ break;
+ case kLoadUnsignedByte:
+ ___ Ldrb(reg_w(dest), MEM_OP(reg_x(base), offset));
+ break;
+ case kLoadUnsignedHalfword:
+ ___ Ldrh(reg_w(dest), MEM_OP(reg_x(base), offset));
+ break;
+ case kLoadWord:
+ ___ Ldr(reg_w(dest), MEM_OP(reg_x(base), offset));
+ break;
+ default:
+ LOG(FATAL) << "UNREACHABLE";
+ }
+}
+
+// Note: We can extend this member by adding load type info - see
+// sign extended A64 load variants.
+void Arm64Assembler::LoadFromOffset(Register dest, Register base,
+ int32_t offset) {
+ CHECK_NE(dest, SP);
+ ___ Ldr(reg_x(dest), MEM_OP(reg_x(base), offset));
+}
+
+void Arm64Assembler::LoadSFromOffset(SRegister dest, Register base,
+ int32_t offset) {
+ ___ Ldr(reg_s(dest), MEM_OP(reg_x(base), offset));
+}
+
+void Arm64Assembler::LoadDFromOffset(DRegister dest, Register base,
+ int32_t offset) {
+ ___ Ldr(reg_d(dest), MEM_OP(reg_x(base), offset));
+}
+
+void Arm64Assembler::Load(Arm64ManagedRegister dest, Register base,
+ int32_t offset, size_t size) {
+ if (dest.IsNoRegister()) {
+ CHECK_EQ(0u, size) << dest;
+ } else if (dest.IsWRegister()) {
+ CHECK_EQ(4u, size) << dest;
+ ___ Ldr(reg_w(dest.AsWRegister()), MEM_OP(reg_x(base), offset));
+ } else if (dest.IsCoreRegister()) {
+ CHECK_EQ(8u, size) << dest;
+ CHECK_NE(dest.AsCoreRegister(), SP) << dest;
+ ___ Ldr(reg_x(dest.AsCoreRegister()), MEM_OP(reg_x(base), offset));
+ } else if (dest.IsSRegister()) {
+ ___ Ldr(reg_s(dest.AsSRegister()), MEM_OP(reg_x(base), offset));
+ } else {
+ CHECK(dest.IsDRegister()) << dest;
+ ___ Ldr(reg_d(dest.AsDRegister()), MEM_OP(reg_x(base), offset));
+ }
+}
+
+void Arm64Assembler::Load(ManagedRegister m_dst, FrameOffset src, size_t size) {
+ return Load(m_dst.AsArm64(), SP, src.Int32Value(), size);
+}
+
+void Arm64Assembler::Load(ManagedRegister m_dst, ThreadOffset src, size_t size) {
+ return Load(m_dst.AsArm64(), TR, src.Int32Value(), size);
+}
+
+void Arm64Assembler::LoadRef(ManagedRegister m_dst, FrameOffset offs) {
+ Arm64ManagedRegister dst = m_dst.AsArm64();
+ CHECK(dst.IsCoreRegister()) << dst;
+ LoadFromOffset(dst.AsCoreRegister(), SP, offs.Int32Value());
+}
+
+void Arm64Assembler::LoadRef(ManagedRegister m_dst, ManagedRegister m_base,
+ MemberOffset offs) {
+ Arm64ManagedRegister dst = m_dst.AsArm64();
+ Arm64ManagedRegister base = m_base.AsArm64();
+ CHECK(dst.IsCoreRegister() && base.IsCoreRegister());
+ LoadFromOffset(dst.AsCoreRegister(), base.AsCoreRegister(), offs.Int32Value());
+}
+
+void Arm64Assembler::LoadRawPtr(ManagedRegister m_dst, ManagedRegister m_base, Offset offs) {
+ Arm64ManagedRegister dst = m_dst.AsArm64();
+ Arm64ManagedRegister base = m_base.AsArm64();
+ CHECK(dst.IsCoreRegister() && base.IsCoreRegister());
+ LoadFromOffset(dst.AsCoreRegister(), base.AsCoreRegister(), offs.Int32Value());
+}
+
+void Arm64Assembler::LoadRawPtrFromThread(ManagedRegister m_dst, ThreadOffset offs) {
+ Arm64ManagedRegister dst = m_dst.AsArm64();
+ CHECK(dst.IsCoreRegister()) << dst;
+ LoadFromOffset(dst.AsCoreRegister(), TR, offs.Int32Value());
+}
+
+// Copying routines.
+void Arm64Assembler::Move(ManagedRegister m_dst, ManagedRegister m_src, size_t size) {
+ Arm64ManagedRegister dst = m_dst.AsArm64();
+ Arm64ManagedRegister src = m_src.AsArm64();
+ if (!dst.Equals(src)) {
+ if (dst.IsCoreRegister()) {
+ CHECK(src.IsCoreRegister()) << src;
+ ___ Mov(reg_x(dst.AsCoreRegister()), reg_x(src.AsCoreRegister()));
+ } else if (dst.IsWRegister()) {
+ CHECK(src.IsWRegister()) << src;
+ ___ Mov(reg_w(dst.AsWRegister()), reg_w(src.AsWRegister()));
+ } else if (dst.IsSRegister()) {
+ CHECK(src.IsSRegister()) << src;
+ ___ Fmov(reg_s(dst.AsSRegister()), reg_s(src.AsSRegister()));
+ } else {
+ CHECK(dst.IsDRegister()) << dst;
+ CHECK(src.IsDRegister()) << src;
+ ___ Fmov(reg_d(dst.AsDRegister()), reg_d(src.AsDRegister()));
+ }
+ }
+}
+
+void Arm64Assembler::CopyRawPtrFromThread(FrameOffset fr_offs,
+ ThreadOffset tr_offs,
+ ManagedRegister m_scratch) {
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ CHECK(scratch.IsCoreRegister()) << scratch;
+ LoadFromOffset(scratch.AsCoreRegister(), TR, tr_offs.Int32Value());
+ StoreToOffset(scratch.AsCoreRegister(), SP, fr_offs.Int32Value());
+}
+
+void Arm64Assembler::CopyRawPtrToThread(ThreadOffset tr_offs,
+ FrameOffset fr_offs,
+ ManagedRegister m_scratch) {
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ CHECK(scratch.IsCoreRegister()) << scratch;
+ LoadFromOffset(scratch.AsCoreRegister(), SP, fr_offs.Int32Value());
+ StoreToOffset(scratch.AsCoreRegister(), TR, tr_offs.Int32Value());
+}
+
+void Arm64Assembler::CopyRef(FrameOffset dest, FrameOffset src,
+ ManagedRegister m_scratch) {
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ CHECK(scratch.IsCoreRegister()) << scratch;
+ LoadFromOffset(scratch.AsCoreRegister(), SP, src.Int32Value());
+ StoreToOffset(scratch.AsCoreRegister(), SP, dest.Int32Value());
+}
+
+void Arm64Assembler::Copy(FrameOffset dest, FrameOffset src,
+ ManagedRegister m_scratch, size_t size) {
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ CHECK(scratch.IsCoreRegister() || scratch.IsWRegister()) << scratch;
+ CHECK(size == 4 || size == 8) << size;
+ if (size == 4) {
+ LoadWFromOffset(kLoadWord, scratch.AsWRegister(), SP, src.Int32Value());
+ StoreWToOffset(kStoreWord, scratch.AsWRegister(), SP, dest.Int32Value());
+ } else if (size == 8) {
+ LoadFromOffset(scratch.AsCoreRegister(), SP, src.Int32Value());
+ StoreToOffset(scratch.AsCoreRegister(), SP, dest.Int32Value());
+ } else {
+ UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8";
+ }
+}
+
+void Arm64Assembler::Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset,
+ ManagedRegister m_scratch, size_t size) {
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ Arm64ManagedRegister base = src_base.AsArm64();
+ CHECK(base.IsCoreRegister()) << base;
+ CHECK(scratch.IsCoreRegister() || scratch.IsWRegister()) << scratch;
+ CHECK(size == 4 || size == 8) << size;
+ if (size == 4) {
+ LoadWFromOffset(kLoadWord, scratch.AsWRegister(), base.AsCoreRegister(),
+ src_offset.Int32Value());
+ StoreWToOffset(kStoreWord, scratch.AsWRegister(), SP, dest.Int32Value());
+ } else if (size == 8) {
+ LoadFromOffset(scratch.AsCoreRegister(), base.AsCoreRegister(), src_offset.Int32Value());
+ StoreToOffset(scratch.AsCoreRegister(), SP, dest.Int32Value());
+ } else {
+ UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8";
+ }
+}
+
+void Arm64Assembler::Copy(ManagedRegister m_dest_base, Offset dest_offs, FrameOffset src,
+ ManagedRegister m_scratch, size_t size) {
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ Arm64ManagedRegister base = m_dest_base.AsArm64();
+ CHECK(base.IsCoreRegister()) << base;
+ CHECK(scratch.IsCoreRegister() || scratch.IsWRegister()) << scratch;
+ CHECK(size == 4 || size == 8) << size;
+ if (size == 4) {
+ LoadWFromOffset(kLoadWord, scratch.AsWRegister(), SP, src.Int32Value());
+ StoreWToOffset(kStoreWord, scratch.AsWRegister(), base.AsCoreRegister(),
+ dest_offs.Int32Value());
+ } else if (size == 8) {
+ LoadFromOffset(scratch.AsCoreRegister(), SP, src.Int32Value());
+ StoreToOffset(scratch.AsCoreRegister(), base.AsCoreRegister(), dest_offs.Int32Value());
+ } else {
+ UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8";
+ }
+}
+
+void Arm64Assembler::Copy(FrameOffset /*dst*/, FrameOffset /*src_base*/, Offset /*src_offset*/,
+ ManagedRegister /*mscratch*/, size_t /*size*/) {
+ UNIMPLEMENTED(FATAL) << "Unimplemented Copy() variant";
+}
+
+void Arm64Assembler::Copy(ManagedRegister m_dest, Offset dest_offset,
+ ManagedRegister m_src, Offset src_offset,
+ ManagedRegister m_scratch, size_t size) {
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ Arm64ManagedRegister src = m_src.AsArm64();
+ Arm64ManagedRegister dest = m_dest.AsArm64();
+ CHECK(dest.IsCoreRegister()) << dest;
+ CHECK(src.IsCoreRegister()) << src;
+ CHECK(scratch.IsCoreRegister() || scratch.IsWRegister()) << scratch;
+ CHECK(size == 4 || size == 8) << size;
+ if (size == 4) {
+ LoadWFromOffset(kLoadWord, scratch.AsWRegister(), src.AsCoreRegister(),
+ src_offset.Int32Value());
+ StoreWToOffset(kStoreWord, scratch.AsWRegister(), dest.AsCoreRegister(),
+ dest_offset.Int32Value());
+ } else if (size == 8) {
+ LoadFromOffset(scratch.AsCoreRegister(), src.AsCoreRegister(), src_offset.Int32Value());
+ StoreToOffset(scratch.AsCoreRegister(), dest.AsCoreRegister(), dest_offset.Int32Value());
+ } else {
+ UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8";
+ }
+}
+
+void Arm64Assembler::Copy(FrameOffset /*dst*/, Offset /*dest_offset*/,
+ FrameOffset /*src*/, Offset /*src_offset*/,
+ ManagedRegister /*scratch*/, size_t /*size*/) {
+ UNIMPLEMENTED(FATAL) << "Unimplemented Copy() variant";
+}
+
+void Arm64Assembler::MemoryBarrier(ManagedRegister m_scratch) {
+ // TODO: Should we check that m_scratch is IP? - see arm.
+#if ANDROID_SMP != 0
+ ___ Dmb(vixl::InnerShareable, vixl::BarrierAll);
+#endif
+}
+
+void Arm64Assembler::SignExtend(ManagedRegister /*mreg*/, size_t /*size*/) {
+ UNIMPLEMENTED(FATAL) << "no sign extension necessary for Arm64";
+}
+
+void Arm64Assembler::ZeroExtend(ManagedRegister /*mreg*/, size_t /*size*/) {
+ UNIMPLEMENTED(FATAL) << "no zero extension necessary for Arm64";
+}
+
+void Arm64Assembler::VerifyObject(ManagedRegister /*src*/, bool /*could_be_null*/) {
+ // TODO: not validating references.
+}
+
+void Arm64Assembler::VerifyObject(FrameOffset /*src*/, bool /*could_be_null*/) {
+ // TODO: not validating references.
+}
+
+void Arm64Assembler::Call(ManagedRegister m_base, Offset offs, ManagedRegister m_scratch) {
+ Arm64ManagedRegister base = m_base.AsArm64();
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ CHECK(base.IsCoreRegister()) << base;
+ CHECK(scratch.IsCoreRegister()) << scratch;
+ LoadFromOffset(scratch.AsCoreRegister(), base.AsCoreRegister(), offs.Int32Value());
+ ___ Blr(reg_x(scratch.AsCoreRegister()));
+}
+
+void Arm64Assembler::Call(FrameOffset base, Offset offs, ManagedRegister m_scratch) {
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ CHECK(scratch.IsCoreRegister()) << scratch;
+ // Call *(*(SP + base) + offset)
+ LoadFromOffset(scratch.AsCoreRegister(), SP, base.Int32Value());
+ LoadFromOffset(scratch.AsCoreRegister(), scratch.AsCoreRegister(), offs.Int32Value());
+ ___ Blr(reg_x(scratch.AsCoreRegister()));
+}
+
+void Arm64Assembler::Call(ThreadOffset /*offset*/, ManagedRegister /*scratch*/) {
+ UNIMPLEMENTED(FATAL) << "Unimplemented Call() variant";
+}
+
+void Arm64Assembler::CreateSirtEntry(ManagedRegister m_out_reg, FrameOffset sirt_offs,
+ ManagedRegister m_in_reg, bool null_allowed) {
+ Arm64ManagedRegister out_reg = m_out_reg.AsArm64();
+ Arm64ManagedRegister in_reg = m_in_reg.AsArm64();
+ // For now we only hold stale sirt entries in x registers.
+ CHECK(in_reg.IsNoRegister() || in_reg.IsCoreRegister()) << in_reg;
+ CHECK(out_reg.IsCoreRegister()) << out_reg;
+ if (null_allowed) {
+ // Null values get a SIRT entry value of 0. Otherwise, the SIRT entry is
+ // the address in the SIRT holding the reference.
+ // e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset)
+ if (in_reg.IsNoRegister()) {
+ LoadFromOffset(out_reg.AsCoreRegister(), SP, sirt_offs.Int32Value());
+ in_reg = out_reg;
+ }
+ ___ Cmp(reg_x(in_reg.AsCoreRegister()), 0);
+ if (!out_reg.Equals(in_reg)) {
+ LoadImmediate(out_reg.AsCoreRegister(), 0, EQ);
+ }
+ AddConstant(out_reg.AsCoreRegister(), SP, sirt_offs.Int32Value(), NE);
+ } else {
+ AddConstant(out_reg.AsCoreRegister(), SP, sirt_offs.Int32Value(), AL);
+ }
+}
+
+void Arm64Assembler::CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset,
+ ManagedRegister m_scratch, bool null_allowed) {
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ CHECK(scratch.IsCoreRegister()) << scratch;
+ if (null_allowed) {
+ LoadFromOffset(scratch.AsCoreRegister(), SP, sirt_offset.Int32Value());
+ // Null values get a SIRT entry value of 0. Otherwise, the sirt entry is
+ // the address in the SIRT holding the reference.
+ // e.g. scratch = (scratch == 0) ? 0 : (SP+sirt_offset)
+ ___ Cmp(reg_x(scratch.AsCoreRegister()), 0);
+ // Move this logic in add constants with flags.
+ AddConstant(scratch.AsCoreRegister(), SP, sirt_offset.Int32Value(), NE);
+ } else {
+ AddConstant(scratch.AsCoreRegister(), SP, sirt_offset.Int32Value(), AL);
+ }
+ StoreToOffset(scratch.AsCoreRegister(), SP, out_off.Int32Value());
+}
+
+void Arm64Assembler::LoadReferenceFromSirt(ManagedRegister m_out_reg,
+ ManagedRegister m_in_reg) {
+ Arm64ManagedRegister out_reg = m_out_reg.AsArm64();
+ Arm64ManagedRegister in_reg = m_in_reg.AsArm64();
+ CHECK(out_reg.IsCoreRegister()) << out_reg;
+ CHECK(in_reg.IsCoreRegister()) << in_reg;
+ vixl::Label exit;
+ if (!out_reg.Equals(in_reg)) {
+ // FIXME: Who sets the flags here?
+ LoadImmediate(out_reg.AsCoreRegister(), 0, EQ);
+ }
+ ___ Cmp(reg_x(in_reg.AsCoreRegister()), 0);
+ ___ B(&exit, COND_OP(EQ));
+ LoadFromOffset(out_reg.AsCoreRegister(), in_reg.AsCoreRegister(), 0);
+ ___ Bind(&exit);
+}
+
+void Arm64Assembler::ExceptionPoll(ManagedRegister m_scratch, size_t stack_adjust) {
+ CHECK_ALIGNED(stack_adjust, kStackAlignment);
+ Arm64ManagedRegister scratch = m_scratch.AsArm64();
+ Arm64Exception *current_exception = new Arm64Exception(scratch, stack_adjust);
+ exception_blocks_.push_back(current_exception);
+ LoadFromOffset(scratch.AsCoreRegister(), TR, Thread::ExceptionOffset().Int32Value());
+ ___ Cmp(reg_x(scratch.AsCoreRegister()), 0);
+ ___ B(current_exception->Entry(), COND_OP(NE));
+}
+
+void Arm64Assembler::EmitExceptionPoll(Arm64Exception *exception) {
+ // Bind exception poll entry.
+ ___ Bind(exception->Entry());
+ if (exception->stack_adjust_ != 0) { // Fix up the frame.
+ DecreaseFrameSize(exception->stack_adjust_);
+ }
+ // Pass exception object as argument.
+ // Don't care about preserving X0 as this won't return.
+ ___ Mov(reg_x(X0), reg_x(exception->scratch_.AsCoreRegister()));
+ LoadFromOffset(IP1, TR, QUICK_ENTRYPOINT_OFFSET(pDeliverException).Int32Value());
+ ___ Blr(reg_x(IP1));
+ // Call should never return.
+ ___ Brk();
+}
+
+void Arm64Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg,
+ const std::vector<ManagedRegister>& callee_save_regs,
+ const std::vector<ManagedRegister>& entry_spills) {
+ CHECK_ALIGNED(frame_size, kStackAlignment);
+ CHECK(X0 == method_reg.AsArm64().AsCoreRegister());
+
+ // TODO: *create APCS FP - end of FP chain;
+ // *add support for saving a different set of callee regs.
+ // For now we check that the size of callee regs vector is 20
+ // equivalent to the APCS callee saved regs [X19, x30] [D8, D15].
+ CHECK_EQ(callee_save_regs.size(), kCalleeSavedRegsSize);
+ ___ PushCalleeSavedRegisters();
+
+ // Increate frame to required size - must be at least space to push Method*.
+ CHECK_GT(frame_size, kCalleeSavedRegsSize * kPointerSize);
+ size_t adjust = frame_size - (kCalleeSavedRegsSize * kPointerSize);
+ IncreaseFrameSize(adjust);
+
+ // Write Method*.
+ StoreToOffset(X0, SP, 0);
+
+ // Write out entry spills, treated as X regs.
+ // TODO: we can implement a %2 STRP variant of StoreToOffset.
+ for (size_t i = 0; i < entry_spills.size(); ++i) {
+ Register reg = entry_spills.at(i).AsArm64().AsCoreRegister();
+ StoreToOffset(reg, SP, frame_size + kPointerSize + (i * kPointerSize));
+ }
+}
+
+void Arm64Assembler::RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs) {
+ CHECK_ALIGNED(frame_size, kStackAlignment);
+
+ // For now we only check that the size of the frame is greater than the
+ // no of APCS callee saved regs [X19, X30] [D8, D15].
+ CHECK_EQ(callee_save_regs.size(), kCalleeSavedRegsSize);
+ CHECK_GT(frame_size, kCalleeSavedRegsSize * kPointerSize);
+
+ // Decrease frame size to start of callee saved regs.
+ size_t adjust = frame_size - (kCalleeSavedRegsSize * kPointerSize);
+ DecreaseFrameSize(adjust);
+
+ // Pop callee saved and return to LR.
+ ___ PopCalleeSavedRegisters();
+ ___ Ret();
+}
+
+} // namespace arm64
+} // namespace art
diff --git a/compiler/utils/arm64/assembler_arm64.h b/compiler/utils/arm64/assembler_arm64.h
new file mode 100644
index 0000000..70df252
--- /dev/null
+++ b/compiler/utils/arm64/assembler_arm64.h
@@ -0,0 +1,286 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ART_COMPILER_UTILS_ARM64_ASSEMBLER_ARM64_H_
+#define ART_COMPILER_UTILS_ARM64_ASSEMBLER_ARM64_H_
+
+#include <vector>
+
+#include "base/logging.h"
+#include "constants_arm64.h"
+#include "utils/arm64/managed_register_arm64.h"
+#include "utils/assembler.h"
+#include "offsets.h"
+#include "utils.h"
+#include "UniquePtr.h"
+#include "a64/macro-assembler-a64.h"
+#include "a64/disasm-a64.h"
+
+namespace art {
+namespace arm64 {
+
+#define MEM_OP(x...) vixl::MemOperand(x)
+#define COND_OP(x) static_cast<vixl::Condition>(x)
+
+enum Condition {
+ kNoCondition = -1,
+ EQ = 0,
+ NE = 1,
+ HS = 2,
+ LO = 3,
+ MI = 4,
+ PL = 5,
+ VS = 6,
+ VC = 7,
+ HI = 8,
+ LS = 9,
+ GE = 10,
+ LT = 11,
+ GT = 12,
+ LE = 13,
+ AL = 14, // Always.
+ NV = 15, // Behaves as always/al.
+ kMaxCondition = 16,
+};
+
+enum LoadOperandType {
+ kLoadSignedByte,
+ kLoadUnsignedByte,
+ kLoadSignedHalfword,
+ kLoadUnsignedHalfword,
+ kLoadWord,
+ kLoadCoreWord,
+ kLoadSWord,
+ kLoadDWord
+};
+
+enum StoreOperandType {
+ kStoreByte,
+ kStoreHalfword,
+ kStoreWord,
+ kStoreCoreWord,
+ kStoreSWord,
+ kStoreDWord
+};
+
+class Arm64Exception;
+
+class Arm64Assembler : public Assembler {
+ public:
+ Arm64Assembler() : vixl_buf_(new byte[BUF_SIZE]),
+ vixl_masm_(new vixl::MacroAssembler(vixl_buf_, BUF_SIZE)) {}
+
+ virtual ~Arm64Assembler() {
+ if (kIsDebugBuild) {
+ vixl::Decoder *decoder = new vixl::Decoder();
+ vixl::PrintDisassembler *test = new vixl::PrintDisassembler(stdout);
+ decoder->AppendVisitor(test);
+
+ for (size_t i = 0; i < CodeSize() / vixl::kInstructionSize; ++i) {
+ vixl::Instruction *instr =
+ reinterpret_cast<vixl::Instruction*>(vixl_buf_ + i * vixl::kInstructionSize);
+ decoder->Decode(instr);
+ }
+ }
+ delete[] vixl_buf_;
+ }
+
+ // Emit slow paths queued during assembly.
+ void EmitSlowPaths();
+
+ // Size of generated code.
+ size_t CodeSize() const;
+
+ // Copy instructions out of assembly buffer into the given region of memory.
+ void FinalizeInstructions(const MemoryRegion& region);
+
+ // Emit code that will create an activation on the stack.
+ void BuildFrame(size_t frame_size, ManagedRegister method_reg,
+ const std::vector<ManagedRegister>& callee_save_regs,
+ const std::vector<ManagedRegister>& entry_spills);
+
+ // Emit code that will remove an activation from the stack.
+ void RemoveFrame(size_t frame_size,
+ const std::vector<ManagedRegister>& callee_save_regs);
+
+ void IncreaseFrameSize(size_t adjust);
+ void DecreaseFrameSize(size_t adjust);
+
+ // Store routines.
+ void Store(FrameOffset offs, ManagedRegister src, size_t size);
+ void StoreRef(FrameOffset dest, ManagedRegister src);
+ void StoreRawPtr(FrameOffset dest, ManagedRegister src);
+ void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
+ ManagedRegister scratch);
+ void StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
+ ManagedRegister scratch);
+ void StoreStackOffsetToThread(ThreadOffset thr_offs,
+ FrameOffset fr_offs,
+ ManagedRegister scratch);
+ void StoreStackPointerToThread(ThreadOffset thr_offs);
+ void StoreSpanning(FrameOffset dest, ManagedRegister src,
+ FrameOffset in_off, ManagedRegister scratch);
+
+ // Load routines.
+ void Load(ManagedRegister dest, FrameOffset src, size_t size);
+ void Load(ManagedRegister dest, ThreadOffset src, size_t size);
+ void LoadRef(ManagedRegister dest, FrameOffset src);
+ void LoadRef(ManagedRegister dest, ManagedRegister base,
+ MemberOffset offs);
+ void LoadRawPtr(ManagedRegister dest, ManagedRegister base,
+ Offset offs);
+ void LoadRawPtrFromThread(ManagedRegister dest,
+ ThreadOffset offs);
+ // Copying routines.
+ void Move(ManagedRegister dest, ManagedRegister src, size_t size);
+ void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
+ ManagedRegister scratch);
+ void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
+ ManagedRegister scratch);
+ void CopyRef(FrameOffset dest, FrameOffset src,
+ ManagedRegister scratch);
+ void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset,
+ ManagedRegister scratch, size_t size);
+ void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src,
+ ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset,
+ ManagedRegister scratch, size_t size);
+ void Copy(ManagedRegister dest, Offset dest_offset,
+ ManagedRegister src, Offset src_offset,
+ ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
+ ManagedRegister scratch, size_t size);
+ void MemoryBarrier(ManagedRegister scratch);
+
+ // Sign extension.
+ void SignExtend(ManagedRegister mreg, size_t size);
+
+ // Zero extension.
+ void ZeroExtend(ManagedRegister mreg, size_t size);
+
+ // Exploit fast access in managed code to Thread::Current().
+ void GetCurrentThread(ManagedRegister tr);
+ void GetCurrentThread(FrameOffset dest_offset,
+ ManagedRegister scratch);
+
+ // Set up out_reg to hold a Object** into the SIRT, or to be NULL if the
+ // value is null and null_allowed. in_reg holds a possibly stale reference
+ // that can be used to avoid loading the SIRT entry to see if the value is
+ // NULL.
+ void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset,
+ ManagedRegister in_reg, bool null_allowed);
+
+ // Set up out_off to hold a Object** into the SIRT, or to be NULL if the
+ // value is null and null_allowed.
+ void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset,
+ ManagedRegister scratch, bool null_allowed);
+
+ // src holds a SIRT entry (Object**) load this into dst.
+ void LoadReferenceFromSirt(ManagedRegister dst,
+ ManagedRegister src);
+
+ // Heap::VerifyObject on src. In some cases (such as a reference to this) we
+ // know that src may not be null.
+ void VerifyObject(ManagedRegister src, bool could_be_null);
+ void VerifyObject(FrameOffset src, bool could_be_null);
+
+ // Call to address held at [base+offset].
+ void Call(ManagedRegister base, Offset offset, ManagedRegister scratch);
+ void Call(FrameOffset base, Offset offset, ManagedRegister scratch);
+ void Call(ThreadOffset offset, ManagedRegister scratch);
+
+ // Generate code to check if Thread::Current()->exception_ is non-null
+ // and branch to a ExceptionSlowPath if it is.
+ void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust);
+
+ private:
+ static vixl::Register reg_x(int code) {
+ CHECK(code < kNumberOfCoreRegisters) << code;
+ if (code == SP) {
+ return vixl::sp;
+ }
+ return vixl::Register::XRegFromCode(code);
+ }
+
+ static vixl::Register reg_w(int code) {
+ return vixl::Register::WRegFromCode(code);
+ }
+
+ static vixl::FPRegister reg_d(int code) {
+ return vixl::FPRegister::DRegFromCode(code);
+ }
+
+ static vixl::FPRegister reg_s(int code) {
+ return vixl::FPRegister::SRegFromCode(code);
+ }
+
+ // Emits Exception block.
+ void EmitExceptionPoll(Arm64Exception *exception);
+
+ void StoreWToOffset(StoreOperandType type, WRegister source,
+ Register base, int32_t offset);
+ void StoreToOffset(Register source, Register base, int32_t offset);
+ void StoreSToOffset(SRegister source, Register base, int32_t offset);
+ void StoreDToOffset(DRegister source, Register base, int32_t offset);
+
+ void LoadImmediate(Register dest, int32_t value, Condition cond = AL);
+ void Load(Arm64ManagedRegister dst, Register src, int32_t src_offset, size_t size);
+ void LoadWFromOffset(LoadOperandType type, WRegister dest,
+ Register base, int32_t offset);
+ void LoadFromOffset(Register dest, Register base, int32_t offset);
+ void LoadSFromOffset(SRegister dest, Register base, int32_t offset);
+ void LoadDFromOffset(DRegister dest, Register base, int32_t offset);
+ void AddConstant(Register rd, int32_t value, Condition cond = AL);
+ void AddConstant(Register rd, Register rn, int32_t value, Condition cond = AL);
+
+ // Vixl buffer size.
+ static constexpr size_t BUF_SIZE = 4096;
+
+ // Vixl buffer.
+ byte* vixl_buf_;
+
+ // Unique ptr - vixl assembler.
+ UniquePtr<vixl::MacroAssembler> vixl_masm_;
+
+ // List of exception blocks to generate at the end of the code cache.
+ std::vector<Arm64Exception*> exception_blocks_;
+};
+
+class Arm64Exception {
+ private:
+ explicit Arm64Exception(Arm64ManagedRegister scratch, size_t stack_adjust)
+ : scratch_(scratch), stack_adjust_(stack_adjust) {
+ }
+
+ vixl::Label* Entry() { return &exception_entry_; }
+
+ // Register used for passing Thread::Current()->exception_ .
+ const Arm64ManagedRegister scratch_;
+
+ // Stack adjust for ExceptionPool.
+ const size_t stack_adjust_;
+
+ vixl::Label exception_entry_;
+
+ friend class Arm64Assembler;
+ DISALLOW_COPY_AND_ASSIGN(Arm64Exception);
+};
+
+} // namespace arm64
+} // namespace art
+
+#endif // ART_COMPILER_UTILS_ARM64_ASSEMBLER_ARM64_H_
diff --git a/compiler/utils/arm64/constants_arm64.h b/compiler/utils/arm64/constants_arm64.h
new file mode 100644
index 0000000..c05c2f1
--- /dev/null
+++ b/compiler/utils/arm64/constants_arm64.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ART_COMPILER_UTILS_ARM64_CONSTANTS_ARM64_H_
+#define ART_COMPILER_UTILS_ARM64_CONSTANTS_ARM64_H_
+
+#include <stdint.h>
+#include <iosfwd>
+#include "arch/arm64/registers_arm64.h"
+#include "base/casts.h"
+#include "base/logging.h"
+#include "globals.h"
+
+// TODO: Extend this file by adding missing functionality.
+
+namespace art {
+namespace arm64 {
+
+ constexpr unsigned int kCalleeSavedRegsSize = 20;
+
+} // arm64
+} // art
+
+#endif // ART_COMPILER_UTILS_ARM64_CONSTANTS_ARM64_H_
diff --git a/compiler/utils/arm64/managed_register_arm64.cc b/compiler/utils/arm64/managed_register_arm64.cc
new file mode 100644
index 0000000..cc0b509
--- /dev/null
+++ b/compiler/utils/arm64/managed_register_arm64.cc
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "managed_register_arm64.h"
+#include "globals.h"
+
+namespace art {
+namespace arm64 {
+
+// TODO: Define convention
+//
+// Do not use APCS callee saved regs for now. Use:
+// * [X0, X15]
+// * [W0, W15]
+// * [D0, D31]
+// * [S0, S31]
+static const int kNumberOfAvailableCoreRegisters = (X15 - X0) + 1;
+static const int kNumberOfAvailableWRegisters = (W15 - W0) + 1;
+static const int kNumberOfAvailableDRegisters = kNumberOfDRegisters;
+static const int kNumberOfAvailableSRegisters = kNumberOfSRegisters;
+
+// Returns true if this managed-register overlaps the other managed-register.
+// GP Register Bank:
+// 31____0 W[n]
+// 63__________0 X[n]
+//
+// FP Register Bank:
+// 31____0 S[n]
+// 63__________0 D[n]
+bool Arm64ManagedRegister::Overlaps(const Arm64ManagedRegister& other) const {
+ if (IsNoRegister() || other.IsNoRegister()) return false;
+ if ((IsGPRegister() && other.IsGPRegister()) ||
+ (IsFPRegister() && other.IsFPRegister())) {
+ return (RegNo() == other.RegNo());
+ }
+ return false;
+}
+
+int Arm64ManagedRegister::RegNo() const {
+ CHECK(!IsNoRegister());
+ int no;
+ if (IsCoreRegister()) {
+ if (IsStackPointer()) {
+ no = static_cast<int>(X31);
+ } else {
+ no = static_cast<int>(AsCoreRegister());
+ }
+ } else if (IsWRegister()) {
+ no = static_cast<int>(AsWRegister());
+ } else if (IsDRegister()) {
+ no = static_cast<int>(AsDRegister());
+ } else if (IsSRegister()) {
+ no = static_cast<int>(AsSRegister());
+ } else {
+ no = kNoRegister;
+ }
+ return no;
+}
+
+int Arm64ManagedRegister::RegIdLow() const {
+ CHECK(IsCoreRegister() || IsDRegister());
+ int low = RegNo();
+ if (IsCoreRegister()) {
+ low += kNumberOfCoreRegIds;
+ } else if (IsDRegister()) {
+ low += kNumberOfCoreRegIds + kNumberOfWRegIds + kNumberOfDRegIds;
+ }
+ return low;
+}
+
+// FIXME: Find better naming.
+int Arm64ManagedRegister::RegIdHigh() const {
+ CHECK(IsWRegister() || IsSRegister());
+ int high = RegNo();
+ if (IsSRegister()) {
+ high += kNumberOfCoreRegIds + kNumberOfWRegIds;
+ }
+ return high;
+}
+
+void Arm64ManagedRegister::Print(std::ostream& os) const {
+ if (!IsValidManagedRegister()) {
+ os << "No Register";
+ } else if (IsCoreRegister()) {
+ os << "XCore: " << static_cast<int>(AsCoreRegister());
+ } else if (IsWRegister()) {
+ os << "WCore: " << static_cast<int>(AsWRegister());
+ } else if (IsDRegister()) {
+ os << "DRegister: " << static_cast<int>(AsDRegister());
+ } else if (IsSRegister()) {
+ os << "SRegister: " << static_cast<int>(AsSRegister());
+ } else {
+ os << "??: " << RegId();
+ }
+}
+
+std::ostream& operator<<(std::ostream& os, const Arm64ManagedRegister& reg) {
+ reg.Print(os);
+ return os;
+}
+
+} // namespace arm64
+} // namespace art
diff --git a/compiler/utils/arm64/managed_register_arm64.h b/compiler/utils/arm64/managed_register_arm64.h
new file mode 100644
index 0000000..5df37cc
--- /dev/null
+++ b/compiler/utils/arm64/managed_register_arm64.h
@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ART_COMPILER_UTILS_ARM64_MANAGED_REGISTER_ARM64_H_
+#define ART_COMPILER_UTILS_ARM64_MANAGED_REGISTER_ARM64_H_
+
+#include "base/logging.h"
+#include "constants_arm64.h"
+#include "utils/managed_register.h"
+
+namespace art {
+namespace arm64 {
+
+const int kNumberOfCoreRegIds = kNumberOfCoreRegisters;
+const int kNumberOfWRegIds = kNumberOfWRegisters;
+const int kNumberOfDRegIds = kNumberOfDRegisters;
+const int kNumberOfSRegIds = kNumberOfSRegisters;
+
+const int kNumberOfRegIds = kNumberOfCoreRegIds + kNumberOfWRegIds +
+ kNumberOfDRegIds + kNumberOfSRegIds;
+
+// Register ids map:
+// [0..X[ core registers 64bit (enum Register)
+// [X..W[ core registers 32bit (enum WRegister)
+// [W..D[ double precision VFP registers (enum DRegister)
+// [D..S[ single precision VFP registers (enum SRegister)
+//
+// where:
+// X = kNumberOfCoreRegIds
+// W = X + kNumberOfWRegIds
+// D = W + kNumberOfDRegIds
+// S = D + kNumberOfSRegIds
+//
+// An instance of class 'ManagedRegister' represents a single Arm64
+// register. A register can be one of the following:
+// * core register 64bit context (enum Register)
+// * core register 32bit context (enum WRegister)
+// * VFP double precision register (enum DRegister)
+// * VFP single precision register (enum SRegister)
+//
+// There is a one to one mapping between ManagedRegister and register id.
+
+class Arm64ManagedRegister : public ManagedRegister {
+ public:
+ Register AsCoreRegister() const {
+ CHECK(IsCoreRegister());
+ return static_cast<Register>(id_);
+ }
+
+ WRegister AsWRegister() const {
+ CHECK(IsWRegister());
+ return static_cast<WRegister>(id_ - kNumberOfCoreRegIds);
+ }
+
+ DRegister AsDRegister() const {
+ CHECK(IsDRegister());
+ return static_cast<DRegister>(id_ - kNumberOfCoreRegIds - kNumberOfWRegIds);
+ }
+
+ SRegister AsSRegister() const {
+ CHECK(IsSRegister());
+ return static_cast<SRegister>(id_ - kNumberOfCoreRegIds - kNumberOfWRegIds -
+ kNumberOfDRegIds);
+ }
+
+ WRegister AsOverlappingCoreRegisterLow() const {
+ CHECK(IsValidManagedRegister());
+ if (IsStackPointer()) return W31;
+ return static_cast<WRegister>(AsCoreRegister());
+ }
+
+ // FIXME: Find better naming.
+ Register AsOverlappingWRegisterCore() const {
+ CHECK(IsValidManagedRegister());
+ return static_cast<Register>(AsWRegister());
+ }
+
+ SRegister AsOverlappingDRegisterLow() const {
+ CHECK(IsValidManagedRegister());
+ return static_cast<SRegister>(AsDRegister());
+ }
+
+ // FIXME: Find better naming.
+ DRegister AsOverlappingSRegisterD() const {
+ CHECK(IsValidManagedRegister());
+ return static_cast<DRegister>(AsSRegister());
+ }
+
+ bool IsCoreRegister() const {
+ CHECK(IsValidManagedRegister());
+ return (0 <= id_) && (id_ < kNumberOfCoreRegIds);
+ }
+
+ bool IsWRegister() const {
+ CHECK(IsValidManagedRegister());
+ const int test = id_ - kNumberOfCoreRegIds;
+ return (0 <= test) && (test < kNumberOfWRegIds);
+ }
+
+ bool IsDRegister() const {
+ CHECK(IsValidManagedRegister());
+ const int test = id_ - (kNumberOfCoreRegIds + kNumberOfWRegIds);
+ return (0 <= test) && (test < kNumberOfDRegIds);
+ }
+
+ bool IsSRegister() const {
+ CHECK(IsValidManagedRegister());
+ const int test = id_ - (kNumberOfCoreRegIds + kNumberOfWRegIds +
+ kNumberOfDRegIds);
+ return (0 <= test) && (test < kNumberOfSRegIds);
+ }
+
+ bool IsGPRegister() const {
+ return IsCoreRegister() || IsWRegister();
+ }
+
+ bool IsFPRegister() const {
+ return IsDRegister() || IsSRegister();
+ }
+
+ bool IsSameType(Arm64ManagedRegister test) const {
+ CHECK(IsValidManagedRegister() && test.IsValidManagedRegister());
+ return
+ (IsCoreRegister() && test.IsCoreRegister()) ||
+ (IsWRegister() && test.IsWRegister()) ||
+ (IsDRegister() && test.IsDRegister()) ||
+ (IsSRegister() && test.IsSRegister());
+ }
+
+ // Returns true if the two managed-registers ('this' and 'other') overlap.
+ // Either managed-register may be the NoRegister. If both are the NoRegister
+ // then false is returned.
+ bool Overlaps(const Arm64ManagedRegister& other) const;
+
+ void Print(std::ostream& os) const;
+
+ static Arm64ManagedRegister FromCoreRegister(Register r) {
+ CHECK_NE(r, kNoRegister);
+ return FromRegId(r);
+ }
+
+ static Arm64ManagedRegister FromWRegister(WRegister r) {
+ CHECK_NE(r, kNoWRegister);
+ return FromRegId(r + kNumberOfCoreRegIds);
+ }
+
+ static Arm64ManagedRegister FromDRegister(DRegister r) {
+ CHECK_NE(r, kNoDRegister);
+ return FromRegId(r + (kNumberOfCoreRegIds + kNumberOfWRegIds));
+ }
+
+ static Arm64ManagedRegister FromSRegister(SRegister r) {
+ CHECK_NE(r, kNoSRegister);
+ return FromRegId(r + (kNumberOfCoreRegIds + kNumberOfWRegIds +
+ kNumberOfDRegIds));
+ }
+
+ // Returns the X register overlapping W register r.
+ static Arm64ManagedRegister FromWRegisterCore(WRegister r) {
+ CHECK_NE(r, kNoWRegister);
+ return FromRegId(r);
+ }
+
+ // Return the D register overlapping S register r.
+ static Arm64ManagedRegister FromSRegisterD(SRegister r) {
+ CHECK_NE(r, kNoSRegister);
+ return FromRegId(r + (kNumberOfCoreRegIds + kNumberOfWRegIds));
+ }
+
+ private:
+ bool IsValidManagedRegister() const {
+ return (0 <= id_) && (id_ < kNumberOfRegIds);
+ }
+
+ bool IsStackPointer() const {
+ return IsCoreRegister() && (id_ == SP);
+ }
+
+ int RegId() const {
+ CHECK(!IsNoRegister());
+ return id_;
+ }
+
+ int RegNo() const;
+ int RegIdLow() const;
+ int RegIdHigh() const;
+
+ friend class ManagedRegister;
+
+ explicit Arm64ManagedRegister(int reg_id) : ManagedRegister(reg_id) {}
+
+ static Arm64ManagedRegister FromRegId(int reg_id) {
+ Arm64ManagedRegister reg(reg_id);
+ CHECK(reg.IsValidManagedRegister());
+ return reg;
+ }
+};
+
+std::ostream& operator<<(std::ostream& os, const Arm64ManagedRegister& reg);
+
+} // namespace arm64
+
+inline arm64::Arm64ManagedRegister ManagedRegister::AsArm64() const {
+ arm64::Arm64ManagedRegister reg(id_);
+ CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister());
+ return reg;
+}
+
+} // namespace art
+
+#endif // ART_COMPILER_UTILS_ARM64_MANAGED_REGISTER_ARM64_H_
diff --git a/compiler/utils/arm64/managed_register_arm64_test.cc b/compiler/utils/arm64/managed_register_arm64_test.cc
new file mode 100644
index 0000000..3d98e12
--- /dev/null
+++ b/compiler/utils/arm64/managed_register_arm64_test.cc
@@ -0,0 +1,611 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "globals.h"
+#include "managed_register_arm64.h"
+#include "gtest/gtest.h"
+
+namespace art {
+namespace arm64 {
+
+TEST(Arm64ManagedRegister, NoRegister) {
+ Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64();
+ EXPECT_TRUE(reg.IsNoRegister());
+ EXPECT_TRUE(!reg.Overlaps(reg));
+}
+
+// X Register test.
+TEST(Arm64ManagedRegister, CoreRegister) {
+ Arm64ManagedRegister reg = Arm64ManagedRegister::FromCoreRegister(X0);
+ Arm64ManagedRegister wreg = Arm64ManagedRegister::FromWRegister(W0);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(wreg));
+ EXPECT_EQ(X0, reg.AsCoreRegister());
+
+ reg = Arm64ManagedRegister::FromCoreRegister(X1);
+ wreg = Arm64ManagedRegister::FromWRegister(W1);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(wreg));
+ EXPECT_EQ(X1, reg.AsCoreRegister());
+
+ reg = Arm64ManagedRegister::FromCoreRegister(X7);
+ wreg = Arm64ManagedRegister::FromWRegister(W7);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(wreg));
+ EXPECT_EQ(X7, reg.AsCoreRegister());
+
+ reg = Arm64ManagedRegister::FromCoreRegister(X15);
+ wreg = Arm64ManagedRegister::FromWRegister(W15);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(wreg));
+ EXPECT_EQ(X15, reg.AsCoreRegister());
+
+ reg = Arm64ManagedRegister::FromCoreRegister(X19);
+ wreg = Arm64ManagedRegister::FromWRegister(W19);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(wreg));
+ EXPECT_EQ(X19, reg.AsCoreRegister());
+
+ reg = Arm64ManagedRegister::FromCoreRegister(X16);
+ wreg = Arm64ManagedRegister::FromWRegister(W16);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(wreg));
+ EXPECT_EQ(IP0, reg.AsCoreRegister());
+
+ reg = Arm64ManagedRegister::FromCoreRegister(SP);
+ wreg = Arm64ManagedRegister::FromWRegister(WZR);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(wreg));
+ EXPECT_EQ(SP, reg.AsCoreRegister());
+}
+
+// W register test.
+TEST(Arm64ManagedRegister, WRegister) {
+ Arm64ManagedRegister reg = Arm64ManagedRegister::FromWRegister(W0);
+ Arm64ManagedRegister xreg = Arm64ManagedRegister::FromCoreRegister(X0);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(!reg.IsCoreRegister());
+ EXPECT_TRUE(reg.IsWRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(xreg));
+ EXPECT_EQ(W0, reg.AsWRegister());
+
+ reg = Arm64ManagedRegister::FromWRegister(W5);
+ xreg = Arm64ManagedRegister::FromCoreRegister(X5);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(!reg.IsCoreRegister());
+ EXPECT_TRUE(reg.IsWRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(xreg));
+ EXPECT_EQ(W5, reg.AsWRegister());
+
+ reg = Arm64ManagedRegister::FromWRegister(W6);
+ xreg = Arm64ManagedRegister::FromCoreRegister(X6);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(!reg.IsCoreRegister());
+ EXPECT_TRUE(reg.IsWRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(xreg));
+ EXPECT_EQ(W6, reg.AsWRegister());
+
+ reg = Arm64ManagedRegister::FromWRegister(W18);
+ xreg = Arm64ManagedRegister::FromCoreRegister(X18);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(!reg.IsCoreRegister());
+ EXPECT_TRUE(reg.IsWRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(xreg));
+ EXPECT_EQ(W18, reg.AsWRegister());
+
+ reg = Arm64ManagedRegister::FromWRegister(W29);
+ xreg = Arm64ManagedRegister::FromCoreRegister(FP);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(!reg.IsCoreRegister());
+ EXPECT_TRUE(reg.IsWRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(xreg));
+ EXPECT_EQ(W29, reg.AsWRegister());
+
+ reg = Arm64ManagedRegister::FromWRegister(WZR);
+ xreg = Arm64ManagedRegister::FromCoreRegister(SP);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(!reg.IsCoreRegister());
+ EXPECT_TRUE(reg.IsWRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(xreg));
+ EXPECT_EQ(W31, reg.AsWRegister());
+}
+
+// D Register test.
+TEST(Arm64ManagedRegister, DRegister) {
+ Arm64ManagedRegister reg = Arm64ManagedRegister::FromDRegister(D0);
+ Arm64ManagedRegister sreg = Arm64ManagedRegister::FromSRegister(S0);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(!reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(sreg));
+ EXPECT_EQ(D0, reg.AsDRegister());
+ EXPECT_EQ(S0, reg.AsOverlappingDRegisterLow());
+ EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromDRegister(D0)));
+
+ reg = Arm64ManagedRegister::FromDRegister(D1);
+ sreg = Arm64ManagedRegister::FromSRegister(S1);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(!reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(sreg));
+ EXPECT_EQ(D1, reg.AsDRegister());
+ EXPECT_EQ(S1, reg.AsOverlappingDRegisterLow());
+ EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromDRegister(D1)));
+
+ reg = Arm64ManagedRegister::FromDRegister(D20);
+ sreg = Arm64ManagedRegister::FromSRegister(S20);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(!reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(sreg));
+ EXPECT_EQ(D20, reg.AsDRegister());
+ EXPECT_EQ(S20, reg.AsOverlappingDRegisterLow());
+ EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromDRegister(D20)));
+
+ reg = Arm64ManagedRegister::FromDRegister(D31);
+ sreg = Arm64ManagedRegister::FromSRegister(S31);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(!reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(reg.IsDRegister());
+ EXPECT_TRUE(!reg.IsSRegister());
+ EXPECT_TRUE(reg.Overlaps(sreg));
+ EXPECT_EQ(D31, reg.AsDRegister());
+ EXPECT_EQ(S31, reg.AsOverlappingDRegisterLow());
+ EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromDRegister(D31)));
+}
+
+// S Register test.
+TEST(Arm64ManagedRegister, SRegister) {
+ Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0);
+ Arm64ManagedRegister dreg = Arm64ManagedRegister::FromDRegister(D0);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(!reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(reg.IsSRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(reg.Overlaps(dreg));
+ EXPECT_EQ(S0, reg.AsSRegister());
+ EXPECT_EQ(D0, reg.AsOverlappingSRegisterD());
+ EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S0)));
+
+ reg = Arm64ManagedRegister::FromSRegister(S5);
+ dreg = Arm64ManagedRegister::FromDRegister(D5);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(!reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(reg.IsSRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(reg.Overlaps(dreg));
+ EXPECT_EQ(S5, reg.AsSRegister());
+ EXPECT_EQ(D5, reg.AsOverlappingSRegisterD());
+ EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S5)));
+
+ reg = Arm64ManagedRegister::FromSRegister(S7);
+ dreg = Arm64ManagedRegister::FromDRegister(D7);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(!reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(reg.IsSRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(reg.Overlaps(dreg));
+ EXPECT_EQ(S7, reg.AsSRegister());
+ EXPECT_EQ(D7, reg.AsOverlappingSRegisterD());
+ EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S7)));
+
+ reg = Arm64ManagedRegister::FromSRegister(S31);
+ dreg = Arm64ManagedRegister::FromDRegister(D31);
+ EXPECT_TRUE(!reg.IsNoRegister());
+ EXPECT_TRUE(!reg.IsCoreRegister());
+ EXPECT_TRUE(!reg.IsWRegister());
+ EXPECT_TRUE(reg.IsSRegister());
+ EXPECT_TRUE(!reg.IsDRegister());
+ EXPECT_TRUE(reg.Overlaps(dreg));
+ EXPECT_EQ(S31, reg.AsSRegister());
+ EXPECT_EQ(D31, reg.AsOverlappingSRegisterD());
+ EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S31)));
+}
+
+TEST(Arm64ManagedRegister, Equals) {
+ ManagedRegister no_reg = ManagedRegister::NoRegister();
+ EXPECT_TRUE(no_reg.Equals(Arm64ManagedRegister::NoRegister()));
+ EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromCoreRegister(X0)));
+ EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromWRegister(W0)));
+ EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromWRegister(W1)));
+ EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromSRegister(S0)));
+
+ Arm64ManagedRegister reg_X0 = Arm64ManagedRegister::FromCoreRegister(X0);
+ EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::NoRegister()));
+ EXPECT_TRUE(reg_X0.Equals(Arm64ManagedRegister::FromCoreRegister(X0)));
+ EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromWRegister(W0)));
+ EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromDRegister(D0)));
+
+ Arm64ManagedRegister reg_X1 = Arm64ManagedRegister::FromCoreRegister(X1);
+ EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::NoRegister()));
+ EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromCoreRegister(X0)));
+ EXPECT_TRUE(reg_X1.Equals(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromWRegister(W1)));
+ EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromDRegister(D1)));
+ EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromSRegister(S1)));
+
+ Arm64ManagedRegister reg_X31 = Arm64ManagedRegister::FromCoreRegister(X31);
+ EXPECT_TRUE(!reg_X31.Equals(Arm64ManagedRegister::NoRegister()));
+ EXPECT_TRUE(!reg_X31.Equals(Arm64ManagedRegister::FromCoreRegister(SP)));
+ EXPECT_TRUE(reg_X31.Equals(Arm64ManagedRegister::FromCoreRegister(XZR)));
+ EXPECT_TRUE(!reg_X31.Equals(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_TRUE(!reg_X31.Equals(Arm64ManagedRegister::FromWRegister(WZR)));
+ EXPECT_TRUE(!reg_X31.Equals(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg_X31.Equals(Arm64ManagedRegister::FromDRegister(D0)));
+
+ Arm64ManagedRegister reg_SP = Arm64ManagedRegister::FromCoreRegister(SP);
+ EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::NoRegister()));
+ // We expect these to pass - SP has a different semantic than X31/XZR.
+ EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromCoreRegister(X31)));
+ EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromCoreRegister(XZR)));
+ EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromDRegister(D0)));
+
+ Arm64ManagedRegister reg_W8 = Arm64ManagedRegister::FromWRegister(W8);
+ EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::NoRegister()));
+ EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromCoreRegister(X0)));
+ EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromCoreRegister(X8)));
+ EXPECT_TRUE(reg_W8.Equals(Arm64ManagedRegister::FromWRegister(W8)));
+ EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromDRegister(D1)));
+ EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromSRegister(S1)));
+
+ Arm64ManagedRegister reg_W12 = Arm64ManagedRegister::FromWRegister(W12);
+ EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::NoRegister()));
+ EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromCoreRegister(X0)));
+ EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromCoreRegister(X8)));
+ EXPECT_TRUE(reg_W12.Equals(Arm64ManagedRegister::FromWRegister(W12)));
+ EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromDRegister(D1)));
+ EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromSRegister(S1)));
+
+ Arm64ManagedRegister reg_S0 = Arm64ManagedRegister::FromSRegister(S0);
+ EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::NoRegister()));
+ EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromCoreRegister(X0)));
+ EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromWRegister(W0)));
+ EXPECT_TRUE(reg_S0.Equals(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromSRegister(S1)));
+ EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromDRegister(D1)));
+
+ Arm64ManagedRegister reg_S1 = Arm64ManagedRegister::FromSRegister(S1);
+ EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::NoRegister()));
+ EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::FromCoreRegister(X0)));
+ EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::FromWRegister(W0)));
+ EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(reg_S1.Equals(Arm64ManagedRegister::FromSRegister(S1)));
+ EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::FromDRegister(D1)));
+
+ Arm64ManagedRegister reg_S31 = Arm64ManagedRegister::FromSRegister(S31);
+ EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::NoRegister()));
+ EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::FromCoreRegister(X0)));
+ EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::FromWRegister(W0)));
+ EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(reg_S31.Equals(Arm64ManagedRegister::FromSRegister(S31)));
+ EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::FromDRegister(D1)));
+
+ Arm64ManagedRegister reg_D0 = Arm64ManagedRegister::FromDRegister(D0);
+ EXPECT_TRUE(!reg_D0.Equals(Arm64ManagedRegister::NoRegister()));
+ EXPECT_TRUE(!reg_D0.Equals(Arm64ManagedRegister::FromCoreRegister(X0)));
+ EXPECT_TRUE(!reg_D0.Equals(Arm64ManagedRegister::FromWRegister(W1)));
+ EXPECT_TRUE(!reg_D0.Equals(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg_D0.Equals(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg_D0.Equals(Arm64ManagedRegister::FromSRegister(S31)));
+ EXPECT_TRUE(reg_D0.Equals(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg_D0.Equals(Arm64ManagedRegister::FromDRegister(D1)));
+
+ Arm64ManagedRegister reg_D15 = Arm64ManagedRegister::FromDRegister(D15);
+ EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::NoRegister()));
+ EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromCoreRegister(X0)));
+ EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromWRegister(W0)));
+ EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromSRegister(S31)));
+ EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromDRegister(D1)));
+ EXPECT_TRUE(reg_D15.Equals(Arm64ManagedRegister::FromDRegister(D15)));
+}
+
+TEST(Arm64ManagedRegister, Overlaps) {
+ Arm64ManagedRegister reg = Arm64ManagedRegister::FromCoreRegister(X0);
+ Arm64ManagedRegister reg_o = Arm64ManagedRegister::FromWRegister(W0);
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(SP)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(W0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
+ EXPECT_EQ(X0, reg_o.AsOverlappingWRegisterCore());
+ EXPECT_EQ(W0, reg.AsOverlappingCoreRegisterLow());
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S30)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D7)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15)));
+
+ reg = Arm64ManagedRegister::FromCoreRegister(X10);
+ reg_o = Arm64ManagedRegister::FromWRegister(W10);
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X10)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(SP)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(W10)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
+ EXPECT_EQ(X10, reg_o.AsOverlappingWRegisterCore());
+ EXPECT_EQ(W10, reg.AsOverlappingCoreRegisterLow());
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S30)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D7)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15)));
+
+ reg = Arm64ManagedRegister::FromCoreRegister(IP1);
+ reg_o = Arm64ManagedRegister::FromWRegister(W17);
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X17)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(SP)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(W17)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
+ EXPECT_EQ(X17, reg_o.AsOverlappingWRegisterCore());
+ EXPECT_EQ(W17, reg.AsOverlappingCoreRegisterLow());
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S30)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D7)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15)));
+
+ reg = Arm64ManagedRegister::FromCoreRegister(XZR);
+ reg_o = Arm64ManagedRegister::FromWRegister(WZR);
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(SP)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W19)));
+ EXPECT_EQ(X31, reg_o.AsOverlappingWRegisterCore());
+ EXPECT_EQ(W31, reg.AsOverlappingCoreRegisterLow());
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S30)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D7)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15)));
+
+ reg = Arm64ManagedRegister::FromCoreRegister(SP);
+ reg_o = Arm64ManagedRegister::FromWRegister(WZR);
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_EQ(X31, reg_o.AsOverlappingWRegisterCore());
+ EXPECT_EQ(W31, reg.AsOverlappingCoreRegisterLow());
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S30)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D7)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15)));
+
+ reg = Arm64ManagedRegister::FromWRegister(W1);
+ reg_o = Arm64ManagedRegister::FromCoreRegister(X1);
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_EQ(W1, reg_o.AsOverlappingCoreRegisterLow());
+ EXPECT_EQ(X1, reg.AsOverlappingWRegisterCore());
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S30)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D7)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15)));
+
+ reg = Arm64ManagedRegister::FromWRegister(W21);
+ reg_o = Arm64ManagedRegister::FromCoreRegister(X21);
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(W21)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X21)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_EQ(W21, reg_o.AsOverlappingCoreRegisterLow());
+ EXPECT_EQ(X21, reg.AsOverlappingWRegisterCore());
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S30)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D7)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15)));
+
+
+ reg = Arm64ManagedRegister::FromSRegister(S1);
+ reg_o = Arm64ManagedRegister::FromDRegister(D1);
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_EQ(S1, reg_o.AsOverlappingDRegisterLow());
+ EXPECT_EQ(D1, reg.AsOverlappingSRegisterD());
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S30)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D0)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromDRegister(D1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D2)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D7)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15)));
+
+ reg = Arm64ManagedRegister::FromSRegister(S15);
+ reg_o = Arm64ManagedRegister::FromDRegister(D15);
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_EQ(S15, reg_o.AsOverlappingDRegisterLow());
+ EXPECT_EQ(D15, reg.AsOverlappingSRegisterD());
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromSRegister(S15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S17)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S16)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D16)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D2)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D17)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D20)));
+
+ reg = Arm64ManagedRegister::FromDRegister(D15);
+ reg_o = Arm64ManagedRegister::FromSRegister(S15);
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_EQ(S15, reg.AsOverlappingDRegisterLow());
+ EXPECT_EQ(D15, reg_o.AsOverlappingSRegisterD());
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromSRegister(S15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S17)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S16)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D16)));
+ EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D2)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D17)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D20)));
+}
+
+} // namespace arm64
+} // namespace art
diff --git a/compiler/utils/assembler.cc b/compiler/utils/assembler.cc
index 92ce0b8..6732476 100644
--- a/compiler/utils/assembler.cc
+++ b/compiler/utils/assembler.cc
@@ -20,6 +20,7 @@
#include <vector>
#include "arm/assembler_arm.h"
+#include "arm64/assembler_arm64.h"
#include "mips/assembler_mips.h"
#include "x86/assembler_x86.h"
#include "globals.h"
@@ -106,6 +107,8 @@
case kArm:
case kThumb2:
return new arm::ArmAssembler();
+ case kArm64:
+ return new arm64::Arm64Assembler();
case kMips:
return new mips::MipsAssembler();
case kX86:
diff --git a/compiler/utils/assembler.h b/compiler/utils/assembler.h
index 296254d..f02c20f 100644
--- a/compiler/utils/assembler.h
+++ b/compiler/utils/assembler.h
@@ -316,16 +316,19 @@
static Assembler* Create(InstructionSet instruction_set);
// Emit slow paths queued during assembly
- void EmitSlowPaths() { buffer_.EmitSlowPaths(this); }
+ virtual void EmitSlowPaths() { buffer_.EmitSlowPaths(this); }
// Size of generated code
- size_t CodeSize() const { return buffer_.Size(); }
+ virtual size_t CodeSize() const { return buffer_.Size(); }
// Copy instructions out of assembly buffer into the given region of memory
- void FinalizeInstructions(const MemoryRegion& region) {
+ virtual void FinalizeInstructions(const MemoryRegion& region) {
buffer_.FinalizeInstructions(region);
}
+ // TODO: Implement with disassembler.
+ virtual void Comment(const char* format, ...) { }
+
// Emit code that will create an activation on the stack
virtual void BuildFrame(size_t frame_size, ManagedRegister method_reg,
const std::vector<ManagedRegister>& callee_save_regs,
diff --git a/compiler/utils/managed_register.h b/compiler/utils/managed_register.h
index 4ad1763..04c9723 100644
--- a/compiler/utils/managed_register.h
+++ b/compiler/utils/managed_register.h
@@ -22,6 +22,9 @@
namespace arm {
class ArmManagedRegister;
}
+namespace arm64 {
+class Arm64ManagedRegister;
+}
namespace mips {
class MipsManagedRegister;
}
@@ -42,6 +45,7 @@
}
arm::ArmManagedRegister AsArm() const;
+ arm64::Arm64ManagedRegister AsArm64() const;
mips::MipsManagedRegister AsMips() const;
x86::X86ManagedRegister AsX86() const;
diff --git a/runtime/Android.mk b/runtime/Android.mk
index fd9dc4c..bb1bc99 100644
--- a/runtime/Android.mk
+++ b/runtime/Android.mk
@@ -152,6 +152,7 @@
LIBART_COMMON_SRC_FILES += \
arch/context.cc \
arch/arm/registers_arm.cc \
+ arch/arm64/registers_arm64.cc \
arch/x86/registers_x86.cc \
arch/mips/registers_mips.cc \
entrypoints/entrypoint_utils.cc \
diff --git a/runtime/arch/arm64/registers_arm64.cc b/runtime/arch/arm64/registers_arm64.cc
new file mode 100644
index 0000000..c5bb06b
--- /dev/null
+++ b/runtime/arch/arm64/registers_arm64.cc
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "registers_arm64.h"
+
+#include <ostream>
+
+namespace art {
+namespace arm64 {
+
+static const char* kRegisterNames[] = {
+ "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9",
+ "x10", "x11", "x12", "x13", "x14", "x15", "ip0", "ip1", "x18", "x19",
+ "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp",
+ "lr", "xzr", "sp"
+};
+
+static const char* kWRegisterNames[] = {
+ "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9",
+ "w10", "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19",
+ "w20", "w21", "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29",
+ "w30", "wzr"
+};
+
+std::ostream& operator<<(std::ostream& os, const Register& rhs) {
+ if (rhs >= X0 && rhs <= SP) {
+ os << kRegisterNames[rhs];
+ } else {
+ os << "XRegister[" << static_cast<int>(rhs) << "]";
+ }
+ return os;
+}
+
+std::ostream& operator<<(std::ostream& os, const WRegister& rhs) {
+ if (rhs >= W0 && rhs <= WZR) {
+ os << kWRegisterNames[rhs];
+ } else {
+ os << "WRegister[" << static_cast<int>(rhs) << "]";
+ }
+ return os;
+}
+
+std::ostream& operator<<(std::ostream& os, const DRegister& rhs) {
+ if (rhs >= D0 && rhs < kNumberOfDRegisters) {
+ os << "d" << static_cast<int>(rhs);
+ } else {
+ os << "DRegister[" << static_cast<int>(rhs) << "]";
+ }
+ return os;
+}
+
+std::ostream& operator<<(std::ostream& os, const SRegister& rhs) {
+ if (rhs >= S0 && rhs < kNumberOfSRegisters) {
+ os << "s" << static_cast<int>(rhs);
+ } else {
+ os << "SRegister[" << static_cast<int>(rhs) << "]";
+ }
+ return os;
+}
+
+} // namespace arm64
+} // namespace art
diff --git a/runtime/arch/arm64/registers_arm64.h b/runtime/arch/arm64/registers_arm64.h
new file mode 100644
index 0000000..e9460e4
--- /dev/null
+++ b/runtime/arch/arm64/registers_arm64.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2014 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ART_RUNTIME_ARCH_ARM64_REGISTERS_ARM64_H_
+#define ART_RUNTIME_ARCH_ARM64_REGISTERS_ARM64_H_
+
+#include <iosfwd>
+
+namespace art {
+namespace arm64 {
+
+// Values for GP XRegisters - 64bit registers.
+enum Register {
+ X0 = 0,
+ X1 = 1,
+ X2 = 2,
+ X3 = 3,
+ X4 = 4,
+ X5 = 5,
+ X6 = 6,
+ X7 = 7,
+ X8 = 8,
+ X9 = 9,
+ X10 = 10,
+ X11 = 11,
+ X12 = 12,
+ X13 = 13,
+ X14 = 14,
+ X15 = 15,
+ X16 = 16,
+ X17 = 17,
+ X18 = 18,
+ X19 = 19,
+ X20 = 20,
+ X21 = 21,
+ X22 = 22,
+ X23 = 23,
+ X24 = 24,
+ X25 = 25,
+ X26 = 26,
+ X27 = 27,
+ X28 = 28,
+ X29 = 29,
+ X30 = 30,
+ X31 = 31,
+ TR = 18, // ART Thread Register.
+ IP0 = 16, // Used as scratch by VIXL.
+ IP1 = 17, // Used as scratch by ART JNI Assembler.
+ FP = 29,
+ LR = 30,
+ XZR = 31,
+ SP = 32, // SP is X31 and overlaps with XRZ but we encode it as a
+ // special register, due to the different instruction semantics.
+ kNumberOfCoreRegisters = 33,
+ kNoRegister = -1,
+};
+std::ostream& operator<<(std::ostream& os, const Register& rhs);
+
+// Values for GP WRegisters - 32bit registers.
+enum WRegister {
+ W0 = 0,
+ W1 = 1,
+ W2 = 2,
+ W3 = 3,
+ W4 = 4,
+ W5 = 5,
+ W6 = 6,
+ W7 = 7,
+ W8 = 8,
+ W9 = 9,
+ W10 = 10,
+ W11 = 11,
+ W12 = 12,
+ W13 = 13,
+ W14 = 14,
+ W15 = 15,
+ W16 = 16,
+ W17 = 17,
+ W18 = 18,
+ W19 = 19,
+ W20 = 20,
+ W21 = 21,
+ W22 = 22,
+ W23 = 23,
+ W24 = 24,
+ W25 = 25,
+ W26 = 26,
+ W27 = 27,
+ W28 = 28,
+ W29 = 29,
+ W30 = 30,
+ W31 = 31,
+ WZR = 31,
+ kNumberOfWRegisters = 32,
+ kNoWRegister = -1,
+};
+std::ostream& operator<<(std::ostream& os, const WRegister& rhs);
+
+// Values for FP DRegisters - double precision floating point.
+enum DRegister {
+ D0 = 0,
+ D1 = 1,
+ D2 = 2,
+ D3 = 3,
+ D4 = 4,
+ D5 = 5,
+ D6 = 6,
+ D7 = 7,
+ D8 = 8,
+ D9 = 9,
+ D10 = 10,
+ D11 = 11,
+ D12 = 12,
+ D13 = 13,
+ D14 = 14,
+ D15 = 15,
+ D16 = 16,
+ D17 = 17,
+ D18 = 18,
+ D19 = 19,
+ D20 = 20,
+ D21 = 21,
+ D22 = 22,
+ D23 = 23,
+ D24 = 24,
+ D25 = 25,
+ D26 = 26,
+ D27 = 27,
+ D28 = 28,
+ D29 = 29,
+ D30 = 30,
+ D31 = 31,
+ kNumberOfDRegisters = 32,
+ kNoDRegister = -1,
+};
+std::ostream& operator<<(std::ostream& os, const DRegister& rhs);
+
+// Values for FP SRegisters - single precision floating point.
+enum SRegister {
+ S0 = 0,
+ S1 = 1,
+ S2 = 2,
+ S3 = 3,
+ S4 = 4,
+ S5 = 5,
+ S6 = 6,
+ S7 = 7,
+ S8 = 8,
+ S9 = 9,
+ S10 = 10,
+ S11 = 11,
+ S12 = 12,
+ S13 = 13,
+ S14 = 14,
+ S15 = 15,
+ S16 = 16,
+ S17 = 17,
+ S18 = 18,
+ S19 = 19,
+ S20 = 20,
+ S21 = 21,
+ S22 = 22,
+ S23 = 23,
+ S24 = 24,
+ S25 = 25,
+ S26 = 26,
+ S27 = 27,
+ S28 = 28,
+ S29 = 29,
+ S30 = 30,
+ S31 = 31,
+ kNumberOfSRegisters = 32,
+ kNoSRegister = -1,
+};
+std::ostream& operator<<(std::ostream& os, const SRegister& rhs);
+
+} // namespace arm64
+} // namespace art
+
+#endif // ART_RUNTIME_ARCH_ARM64_REGISTERS_ARM64_H_
diff --git a/runtime/arch/x86_64/asm_support_x86_64.h b/runtime/arch/x86_64/asm_support_x86_64.h
index 444fa22..5a4e63e 100644
--- a/runtime/arch/x86_64/asm_support_x86_64.h
+++ b/runtime/arch/x86_64/asm_support_x86_64.h
@@ -20,11 +20,11 @@
#include "asm_support.h"
// Offset of field Runtime::callee_save_methods_[kSaveAll]
-#define RUNTIME_SAVE_ALL_CALLEE_SAVE_FRAME_OFFSET 208
+#define RUNTIME_SAVE_ALL_CALLEE_SAVE_FRAME_OFFSET 200
// Offset of field Runtime::callee_save_methods_[kRefsOnly]
-#define RUNTIME_REFS_ONLY_CALLEE_SAVE_FRAME_OFFSET 216
+#define RUNTIME_REFS_ONLY_CALLEE_SAVE_FRAME_OFFSET 208
// Offset of field Runtime::callee_save_methods_[kRefsAndArgs]
-#define RUNTIME_REF_AND_ARGS_CALLEE_SAVE_FRAME_OFFSET 224
+#define RUNTIME_REF_AND_ARGS_CALLEE_SAVE_FRAME_OFFSET 216
// Offset of field Thread::self_ verified in InitCpu
#define THREAD_SELF_OFFSET 72
diff --git a/runtime/gc/allocator/rosalloc.cc b/runtime/gc/allocator/rosalloc.cc
index e86bee6..e13bd71 100644
--- a/runtime/gc/allocator/rosalloc.cc
+++ b/runtime/gc/allocator/rosalloc.cc
@@ -93,6 +93,12 @@
}
}
+RosAlloc::~RosAlloc() {
+ for (size_t i = 0; i < kNumOfSizeBrackets; i++) {
+ delete size_bracket_locks_[i];
+ }
+}
+
void* RosAlloc::AllocPages(Thread* self, size_t num_pages, byte page_map_type) {
lock_.AssertHeld(self);
DCHECK(page_map_type == kPageMapRun || page_map_type == kPageMapLargeObject);
diff --git a/runtime/gc/allocator/rosalloc.h b/runtime/gc/allocator/rosalloc.h
index 4b0dd79..738d917 100644
--- a/runtime/gc/allocator/rosalloc.h
+++ b/runtime/gc/allocator/rosalloc.h
@@ -515,6 +515,7 @@
RosAlloc(void* base, size_t capacity, size_t max_capacity,
PageReleaseMode page_release_mode,
size_t page_release_size_threshold = kDefaultPageReleaseSizeThreshold);
+ ~RosAlloc();
void* Alloc(Thread* self, size_t size, size_t* bytes_allocated)
LOCKS_EXCLUDED(lock_);
void Free(Thread* self, void* ptr)
diff --git a/runtime/gc/heap.cc b/runtime/gc/heap.cc
index b97b9ec..87ee21b 100644
--- a/runtime/gc/heap.cc
+++ b/runtime/gc/heap.cc
@@ -152,7 +152,7 @@
total_allocation_time_(0),
verify_object_mode_(kVerifyObjectModeDisabled),
disable_moving_gc_count_(0),
- running_on_valgrind_(RUNNING_ON_VALGRIND),
+ running_on_valgrind_(RUNNING_ON_VALGRIND > 0),
use_tlab_(use_tlab) {
if (VLOG_IS_ON(heap) || VLOG_IS_ON(startup)) {
LOG(INFO) << "Heap() entering";
diff --git a/runtime/gc/space/dlmalloc_space.cc b/runtime/gc/space/dlmalloc_space.cc
index b591486..0597422 100644
--- a/runtime/gc/space/dlmalloc_space.cc
+++ b/runtime/gc/space/dlmalloc_space.cc
@@ -43,9 +43,8 @@
}
DlMallocSpace* DlMallocSpace::CreateFromMemMap(MemMap* mem_map, const std::string& name,
- size_t starting_size,
- size_t initial_size, size_t growth_limit,
- size_t capacity) {
+ size_t starting_size, size_t initial_size,
+ size_t growth_limit, size_t capacity) {
DCHECK(mem_map != nullptr);
void* mspace = CreateMspace(mem_map->Begin(), starting_size, initial_size);
if (mspace == nullptr) {
@@ -133,12 +132,12 @@
size_t footprint = mspace_footprint(mspace_);
mspace_set_footprint_limit(mspace_, footprint);
}
- if (result != NULL) {
+ if (result != nullptr) {
// Zero freshly allocated memory, done while not holding the space's lock.
memset(result, 0, num_bytes);
+ // Check that the result is contained in the space.
+ CHECK(!kDebugSpaces || Contains(result));
}
- // Return the new allocation or NULL.
- CHECK(!kDebugSpaces || result == NULL || Contains(result));
return result;
}
@@ -151,7 +150,7 @@
size_t DlMallocSpace::Free(Thread* self, mirror::Object* ptr) {
MutexLock mu(self, lock_);
if (kDebugSpaces) {
- CHECK(ptr != NULL);
+ CHECK(ptr != nullptr);
CHECK(Contains(ptr)) << "Free (" << ptr << ") not in bounds of heap " << *this;
}
const size_t bytes_freed = AllocationSizeNonvirtual(ptr, nullptr);
diff --git a/runtime/gc/space/image_space.cc b/runtime/gc/space/image_space.cc
index 8426fab..ca5b5a9 100644
--- a/runtime/gc/space/image_space.cc
+++ b/runtime/gc/space/image_space.cc
@@ -115,6 +115,8 @@
space::ImageSpace* image_space = ImageSpace::Init(image_file_name.c_str(), true, &error_msg);
if (image_space != nullptr) {
return image_space;
+ } else {
+ LOG(WARNING) << error_msg;
}
}
CHECK(GenerateImage(image_file_name, &error_msg))
diff --git a/runtime/gc/space/malloc_space.h b/runtime/gc/space/malloc_space.h
index 30c7c45..fbcee5f 100644
--- a/runtime/gc/space/malloc_space.h
+++ b/runtime/gc/space/malloc_space.h
@@ -139,7 +139,7 @@
virtual void* CreateAllocator(void* base, size_t morecore_start, size_t initial_size,
size_t maximum_size, bool low_memory_mode) = 0;
- void RegisterRecentFree(mirror::Object* ptr)
+ virtual void RegisterRecentFree(mirror::Object* ptr)
SHARED_LOCKS_REQUIRED(Locks::mutator_lock_)
EXCLUSIVE_LOCKS_REQUIRED(lock_);
diff --git a/runtime/gc/space/rosalloc_space-inl.h b/runtime/gc/space/rosalloc_space-inl.h
index 2627c85..d270885 100644
--- a/runtime/gc/space/rosalloc_space-inl.h
+++ b/runtime/gc/space/rosalloc_space-inl.h
@@ -50,7 +50,7 @@
size_t* bytes_allocated, size_t* usable_size) {
size_t rosalloc_size = 0;
mirror::Object* result = reinterpret_cast<mirror::Object*>(
- rosalloc_for_alloc_->Alloc(self, num_bytes, &rosalloc_size));
+ rosalloc_->Alloc(self, num_bytes, &rosalloc_size));
if (LIKELY(result != NULL)) {
if (kDebugSpaces) {
CHECK(Contains(result)) << "Allocation (" << reinterpret_cast<void*>(result)
diff --git a/runtime/gc/space/rosalloc_space.cc b/runtime/gc/space/rosalloc_space.cc
index b13ac3d..c4ce94d 100644
--- a/runtime/gc/space/rosalloc_space.cc
+++ b/runtime/gc/space/rosalloc_space.cc
@@ -39,8 +39,7 @@
RosAllocSpace::RosAllocSpace(const std::string& name, MemMap* mem_map,
art::gc::allocator::RosAlloc* rosalloc, byte* begin, byte* end,
byte* limit, size_t growth_limit)
- : MallocSpace(name, mem_map, begin, end, limit, growth_limit), rosalloc_(rosalloc),
- rosalloc_for_alloc_(rosalloc) {
+ : MallocSpace(name, mem_map, begin, end, limit, growth_limit), rosalloc_(rosalloc) {
CHECK(rosalloc != NULL);
}
@@ -64,7 +63,9 @@
// Everything is set so record in immutable structure and leave
byte* begin = mem_map->Begin();
- if (RUNNING_ON_VALGRIND > 0) {
+ // TODO: Fix RosAllocSpace to support valgrind. There is currently some issues with
+ // AllocationSize caused by redzones. b/12944686
+ if (false && RUNNING_ON_VALGRIND > 0) {
return new ValgrindMallocSpace<RosAllocSpace, allocator::RosAlloc*>(
name, mem_map, rosalloc, begin, end, begin + capacity, growth_limit, initial_size);
} else {
@@ -72,6 +73,10 @@
}
}
+RosAllocSpace::~RosAllocSpace() {
+ delete rosalloc_;
+}
+
RosAllocSpace* RosAllocSpace::Create(const std::string& name, size_t initial_size,
size_t growth_limit, size_t capacity, byte* requested_begin,
bool low_memory_mode) {
diff --git a/runtime/gc/space/rosalloc_space.h b/runtime/gc/space/rosalloc_space.h
index 9f756aa..9b9adf8 100644
--- a/runtime/gc/space/rosalloc_space.h
+++ b/runtime/gc/space/rosalloc_space.h
@@ -105,6 +105,8 @@
rosalloc_->Verify();
}
+ virtual ~RosAllocSpace();
+
protected:
RosAllocSpace(const std::string& name, MemMap* mem_map, allocator::RosAlloc* rosalloc,
byte* begin, byte* end, byte* limit, size_t growth_limit);
@@ -127,10 +129,6 @@
// Underlying rosalloc.
allocator::RosAlloc* const rosalloc_;
- // The rosalloc pointer used for allocation. Equal to rosalloc_ or nullptr after
- // InvalidateAllocator() is called.
- allocator::RosAlloc* rosalloc_for_alloc_;
-
friend class collector::MarkSweep;
DISALLOW_COPY_AND_ASSIGN(RosAllocSpace);
diff --git a/runtime/gc/space/valgrind_malloc_space-inl.h b/runtime/gc/space/valgrind_malloc_space-inl.h
index 4b0c8e3..ed97e60 100644
--- a/runtime/gc/space/valgrind_malloc_space-inl.h
+++ b/runtime/gc/space/valgrind_malloc_space-inl.h
@@ -38,9 +38,6 @@
if (obj_with_rdz == nullptr) {
return nullptr;
}
- if (usable_size != nullptr) {
- *usable_size -= 2 * kValgrindRedZoneBytes;
- }
mirror::Object* result = reinterpret_cast<mirror::Object*>(
reinterpret_cast<byte*>(obj_with_rdz) + kValgrindRedZoneBytes);
// Make redzones as no access.
@@ -58,9 +55,6 @@
if (obj_with_rdz == nullptr) {
return nullptr;
}
- if (usable_size != nullptr) {
- *usable_size -= 2 * kValgrindRedZoneBytes;
- }
mirror::Object* result = reinterpret_cast<mirror::Object*>(
reinterpret_cast<byte*>(obj_with_rdz) + kValgrindRedZoneBytes);
// Make redzones as no access.
@@ -73,10 +67,7 @@
size_t ValgrindMallocSpace<S, A>::AllocationSize(mirror::Object* obj, size_t* usable_size) {
size_t result = S::AllocationSize(reinterpret_cast<mirror::Object*>(
reinterpret_cast<byte*>(obj) - kValgrindRedZoneBytes), usable_size);
- if (usable_size != nullptr) {
- *usable_size -= 2 * kValgrindRedZoneBytes;
- }
- return result - 2 * kValgrindRedZoneBytes;
+ return result;
}
template <typename S, typename A>
@@ -84,11 +75,10 @@
void* obj_after_rdz = reinterpret_cast<void*>(ptr);
void* obj_with_rdz = reinterpret_cast<byte*>(obj_after_rdz) - kValgrindRedZoneBytes;
// Make redzones undefined.
- size_t allocation_size =
- AllocationSize(reinterpret_cast<mirror::Object*>(obj_with_rdz), nullptr);
- VALGRIND_MAKE_MEM_UNDEFINED(obj_with_rdz, allocation_size);
- size_t freed = S::Free(self, reinterpret_cast<mirror::Object*>(obj_with_rdz));
- return freed - 2 * kValgrindRedZoneBytes;
+ size_t usable_size = 0;
+ AllocationSize(ptr, &usable_size);
+ VALGRIND_MAKE_MEM_UNDEFINED(obj_with_rdz, usable_size);
+ return S::Free(self, reinterpret_cast<mirror::Object*>(obj_with_rdz));
}
template <typename S, typename A>
@@ -96,6 +86,7 @@
size_t freed = 0;
for (size_t i = 0; i < num_ptrs; i++) {
freed += Free(self, ptrs[i]);
+ ptrs[i] = nullptr;
}
return freed;
}
diff --git a/runtime/gc/space/valgrind_malloc_space.h b/runtime/gc/space/valgrind_malloc_space.h
index 8d00b30..6b755c4 100644
--- a/runtime/gc/space/valgrind_malloc_space.h
+++ b/runtime/gc/space/valgrind_malloc_space.h
@@ -43,6 +43,9 @@
size_t FreeList(Thread* self, size_t num_ptrs, mirror::Object** ptrs) OVERRIDE
SHARED_LOCKS_REQUIRED(Locks::mutator_lock_);
+ void RegisterRecentFree(mirror::Object* ptr) OVERRIDE {
+ }
+
ValgrindMallocSpace(const std::string& name, MemMap* mem_map, AllocatorType allocator,
byte* begin, byte* end, byte* limit, size_t growth_limit,
size_t initial_size);
diff --git a/runtime/instruction_set.h b/runtime/instruction_set.h
index ac83601..cbc9912 100644
--- a/runtime/instruction_set.h
+++ b/runtime/instruction_set.h
@@ -27,6 +27,7 @@
enum InstructionSet {
kNone,
kArm,
+ kArm64,
kThumb2,
kX86,
kX86_64,
diff --git a/runtime/instrumentation.cc b/runtime/instrumentation.cc
index e10d881..89a63ac 100644
--- a/runtime/instrumentation.cc
+++ b/runtime/instrumentation.cc
@@ -457,6 +457,22 @@
thread->ResetQuickAllocEntryPointsForThread();
}
+void Instrumentation::SetEntrypointsInstrumented(bool instrumented) {
+ Runtime* runtime = Runtime::Current();
+ ThreadList* tl = runtime->GetThreadList();
+ if (runtime->IsStarted()) {
+ tl->SuspendAll();
+ }
+ {
+ MutexLock mu(Thread::Current(), *Locks::runtime_shutdown_lock_);
+ SetQuickAllocEntryPointsInstrumented(instrumented);
+ ResetQuickAllocEntryPoints();
+ }
+ if (runtime->IsStarted()) {
+ tl->ResumeAll();
+ }
+}
+
void Instrumentation::InstrumentQuickAllocEntryPoints() {
// TODO: the read of quick_alloc_entry_points_instrumentation_counter_ is racey and this code
// should be guarded by a lock.
@@ -464,15 +480,7 @@
const bool enable_instrumentation =
quick_alloc_entry_points_instrumentation_counter_.FetchAndAdd(1) == 0;
if (enable_instrumentation) {
- // Instrumentation wasn't enabled so enable it.
- ThreadList* tl = Runtime::Current()->GetThreadList();
- tl->SuspendAll();
- {
- MutexLock mu(Thread::Current(), *Locks::runtime_shutdown_lock_);
- SetQuickAllocEntryPointsInstrumented(true);
- ResetQuickAllocEntryPoints();
- }
- tl->ResumeAll();
+ SetEntrypointsInstrumented(true);
}
}
@@ -483,14 +491,7 @@
const bool disable_instrumentation =
quick_alloc_entry_points_instrumentation_counter_.FetchAndSub(1) == 1;
if (disable_instrumentation) {
- ThreadList* tl = Runtime::Current()->GetThreadList();
- tl->SuspendAll();
- {
- MutexLock mu(Thread::Current(), *Locks::runtime_shutdown_lock_);
- SetQuickAllocEntryPointsInstrumented(false);
- ResetQuickAllocEntryPoints();
- }
- tl->ResumeAll();
+ SetEntrypointsInstrumented(false);
}
}
diff --git a/runtime/instrumentation.h b/runtime/instrumentation.h
index d7a0b4d..e04d7b2 100644
--- a/runtime/instrumentation.h
+++ b/runtime/instrumentation.h
@@ -296,6 +296,10 @@
interpreter_handler_table_ = IsActive() ? kAlternativeHandlerTable : kMainHandlerTable;
}
+ // No thread safety analysis to get around SetQuickAllocEntryPointsInstrumented requiring
+ // exclusive access to mutator lock which you can't get if the runtime isn't started.
+ void SetEntrypointsInstrumented(bool instrumented) NO_THREAD_SAFETY_ANALYSIS;
+
void MethodEnterEventImpl(Thread* thread, mirror::Object* this_object,
mirror::ArtMethod* method, uint32_t dex_pc) const
SHARED_LOCKS_REQUIRED(Locks::mutator_lock_);
diff --git a/runtime/mem_map.cc b/runtime/mem_map.cc
index 393ea68..fdfb477 100644
--- a/runtime/mem_map.cc
+++ b/runtime/mem_map.cc
@@ -110,7 +110,7 @@
if (actual == MAP_FAILED) {
std::string maps;
ReadFileToString("/proc/self/maps", &maps);
- *error_msg = StringPrintf("anonymous mmap(%p, %zd, %x, %x, %d, 0) failed\n%s",
+ *error_msg = StringPrintf("anonymous mmap(%p, %zd, 0x%x, 0x%x, %d, 0) failed\n%s",
addr, page_aligned_byte_count, prot, flags, fd.get(),
maps.c_str());
return nullptr;
@@ -151,7 +151,8 @@
std::string strerr(strerror(errno));
std::string maps;
ReadFileToString("/proc/self/maps", &maps);
- *error_msg = StringPrintf("mmap(%p, %zd, %x, %x, %d, %" PRId64 ") of file '%s' failed: %s\n%s",
+ *error_msg = StringPrintf("mmap(%p, %zd, 0x%x, 0x%x, %d, %" PRId64
+ ") of file '%s' failed: %s\n%s",
page_aligned_addr, page_aligned_byte_count, prot, flags, fd,
static_cast<int64_t>(page_aligned_offset), filename, strerr.c_str(),
maps.c_str());
@@ -247,7 +248,7 @@
if (actual == MAP_FAILED) {
std::string maps;
ReadFileToString("/proc/self/maps", &maps);
- *error_msg = StringPrintf("anonymous mmap(%p, %zd, %x, %x, %d, 0) failed\n%s",
+ *error_msg = StringPrintf("anonymous mmap(%p, %zd, 0x%x, 0x%x, %d, 0) failed\n%s",
tail_base_begin, tail_base_size, tail_prot, flags, fd.get(),
maps.c_str());
return nullptr;
@@ -272,7 +273,7 @@
}
std::ostream& operator<<(std::ostream& os, const MemMap& mem_map) {
- os << StringPrintf("[MemMap: %s prot=%x %p-%p]",
+ os << StringPrintf("[MemMap: %s prot=0x%x %p-%p]",
mem_map.GetName().c_str(), mem_map.GetProtect(),
mem_map.BaseBegin(), mem_map.BaseEnd());
return os;
diff --git a/runtime/parsed_options.cc b/runtime/parsed_options.cc
index b6f36b6..04f1a05 100644
--- a/runtime/parsed_options.cc
+++ b/runtime/parsed_options.cc
@@ -288,13 +288,13 @@
return false;
}
} else if (StartsWith(option, "-XX:LongPauseLogThreshold=")) {
- size_t value;
+ unsigned int value;
if (!ParseUnsignedInteger(option, '=', &value)) {
return false;
}
long_pause_log_threshold_ = MsToNs(value);
} else if (StartsWith(option, "-XX:LongGCLogThreshold=")) {
- size_t value;
+ unsigned int value;
if (!ParseUnsignedInteger(option, '=', &value)) {
return false;
}
diff --git a/runtime/parsed_options.h b/runtime/parsed_options.h
index 0af17ee..f07bba1 100644
--- a/runtime/parsed_options.h
+++ b/runtime/parsed_options.h
@@ -44,8 +44,8 @@
bool verify_post_gc_heap_;
bool verify_pre_gc_rosalloc_;
bool verify_post_gc_rosalloc_;
- size_t long_pause_log_threshold_;
- size_t long_gc_log_threshold_;
+ unsigned int long_pause_log_threshold_;
+ unsigned int long_gc_log_threshold_;
bool dump_gc_performance_on_shutdown_;
bool ignore_max_footprint_;
size_t heap_initial_size_;
@@ -54,18 +54,18 @@
size_t heap_min_free_;
size_t heap_max_free_;
double heap_target_utilization_;
- size_t parallel_gc_threads_;
- size_t conc_gc_threads_;
+ unsigned int parallel_gc_threads_;
+ unsigned int conc_gc_threads_;
gc::CollectorType collector_type_;
gc::CollectorType background_collector_type_;
size_t stack_size_;
- size_t max_spins_before_thin_lock_inflation_;
+ unsigned int max_spins_before_thin_lock_inflation_;
bool low_memory_mode_;
- size_t lock_profiling_threshold_;
+ unsigned int lock_profiling_threshold_;
std::string stack_trace_file_;
bool method_trace_;
std::string method_trace_file_;
- size_t method_trace_file_size_;
+ unsigned int method_trace_file_size_;
bool (*hook_is_sensitive_thread_)();
jint (*hook_vfprintf_)(FILE* stream, const char* format, va_list ap);
void (*hook_exit_)(jint status);
diff --git a/runtime/runtime.h b/runtime/runtime.h
index f12c3d8..87307ae 100644
--- a/runtime/runtime.h
+++ b/runtime/runtime.h
@@ -68,6 +68,9 @@
class Trace;
class Transaction;
+// Not all combinations of flags are valid. You may not visit all roots as well as the new roots
+// (no logical reason to do this). You also may not start logging new roots and stop logging new
+// roots (also no logical reason to do this).
enum VisitRootFlags : uint8_t {
kVisitRootFlagAllRoots = 0x1,
kVisitRootFlagNewRoots = 0x2,
diff --git a/runtime/transaction_test.cc b/runtime/transaction_test.cc
index 7242b81..2e6ce4f 100644
--- a/runtime/transaction_test.cc
+++ b/runtime/transaction_test.cc
@@ -86,10 +86,10 @@
// Allocate an array during transaction.
SirtRef<mirror::Array> sirt_obj(soa.Self(),
- mirror::Array::Alloc<false>(soa.Self(), sirt_klass.get(),
- kArraySize,
- sirt_klass->GetComponentSize(),
- Runtime::Current()->GetHeap()->GetCurrentAllocator()));
+ mirror::Array::Alloc<true>(soa.Self(), sirt_klass.get(),
+ kArraySize,
+ sirt_klass->GetComponentSize(),
+ Runtime::Current()->GetHeap()->GetCurrentAllocator()));
ASSERT_TRUE(sirt_obj.get() != nullptr);
ASSERT_EQ(sirt_obj->GetClass(), sirt_klass.get());
Runtime::Current()->ExitTransactionMode();
diff --git a/runtime/utils.cc b/runtime/utils.cc
index d8f8f8f..237d217 100644
--- a/runtime/utils.cc
+++ b/runtime/utils.cc
@@ -1049,7 +1049,7 @@
if (last_slash == std::string::npos) {
return map->name;
}
- return map->name.substr(last_slash);
+ return map->name.substr(last_slash + 1);
}
void DumpNativeStack(std::ostream& os, pid_t tid, const char* prefix, bool include_count) {
diff --git a/runtime/utils_test.cc b/runtime/utils_test.cc
index d804f6a..2c1aae8 100644
--- a/runtime/utils_test.cc
+++ b/runtime/utils_test.cc
@@ -25,6 +25,8 @@
#include "scoped_thread_state_change.h"
#include "sirt_ref.h"
+#include <valgrind.h>
+
namespace art {
std::string PrettyArguments(const char* signature);
@@ -358,7 +360,10 @@
command.push_back("/usr/bin/id");
}
std::string error_msg;
- EXPECT_TRUE(Exec(command, &error_msg));
+ if (RUNNING_ON_VALGRIND == 0) {
+ // Running on valgrind fails due to some memory that leaks in thread alternate signal stacks.
+ EXPECT_TRUE(Exec(command, &error_msg));
+ }
EXPECT_EQ(0U, error_msg.size()) << error_msg;
}
@@ -366,8 +371,11 @@
std::vector<std::string> command;
command.push_back("bogus");
std::string error_msg;
- EXPECT_FALSE(Exec(command, &error_msg));
- EXPECT_NE(0U, error_msg.size());
+ if (RUNNING_ON_VALGRIND == 0) {
+ // Running on valgrind fails due to some memory that leaks in thread alternate signal stacks.
+ EXPECT_FALSE(Exec(command, &error_msg));
+ EXPECT_NE(0U, error_msg.size());
+ }
}
} // namespace art
diff --git a/runtime/zip_archive.cc b/runtime/zip_archive.cc
index ba0b91e..ddac7d4 100644
--- a/runtime/zip_archive.cc
+++ b/runtime/zip_archive.cc
@@ -38,6 +38,9 @@
return zip_entry_->crc32;
}
+ZipEntry::~ZipEntry() {
+ delete zip_entry_;
+}
bool ZipEntry::ExtractToFile(File& file, std::string* error_msg) {
const int32_t error = ExtractEntryToFile(handle_, zip_entry_, file.Fd());
diff --git a/runtime/zip_archive.h b/runtime/zip_archive.h
index 2169fe0..3ef0e6b 100644
--- a/runtime/zip_archive.h
+++ b/runtime/zip_archive.h
@@ -38,6 +38,7 @@
public:
bool ExtractToFile(File& file, std::string* error_msg);
MemMap* ExtractToMemMap(const char* entry_filename, std::string* error_msg);
+ virtual ~ZipEntry();
uint32_t GetUncompressedLength();
uint32_t GetCrc32();