ART: Add another special case to GenSelect for ARM64
This adds a special case for a select of two constants that have a
difference of exactly one.
Change-Id: I6e8bea791cb25af1b855d62e2333fd7fe6ac4e3a
diff --git a/compiler/dex/quick/arm64/int_arm64.cc b/compiler/dex/quick/arm64/int_arm64.cc
index f7aa39f..abc239f 100644
--- a/compiler/dex/quick/arm64/int_arm64.cc
+++ b/compiler/dex/quick/arm64/int_arm64.cc
@@ -168,6 +168,19 @@
left_op = rl_result.reg.GetReg();
right_op = zero_reg;
opcode = is_wide ? WIDE(kA64Csinv4rrrc) : kA64Csinv4rrrc;
+ } else if ((true_val + 1 == false_val) || (false_val + 1 == true_val)) {
+ // Load a constant and use CSinc. Use rl_result.
+ if (false_val + 1 == true_val) {
+ // Negate.
+ code = ArmConditionEncoding(NegateComparison(mir->meta.ccode));
+ true_val = false_val;
+ }
+
+ rl_result = EvalLoc(rl_dest, result_reg_class, true);
+ rl_result_evaled = true;
+ LoadConstantNoClobber(rl_result.reg, true_val);
+ left_op = right_op = rl_result.reg.GetReg();
+ opcode = is_wide ? WIDE(kA64Csinc4rrrc) : kA64Csinc4rrrc;
} else {
// Csel. The rest. Use rl_result and a temp.
// TODO: To minimize the constants being loaded, check whether one can be inexpensively