commit 40741f394b2737e503f2c08be0ae9dd490fb106b
author Mark Mendell <mark.p.mendell@intel.com> Mon Apr 20 22:10:34 2015 -0400
committer Mark Mendell <mark.p.mendell@intel.com> Tue Apr 21 16:23:15 2015 -0400
tree d5d9e6d51168e36154de408e2b5d77371bd8c86d
parent dac1a694e4fd79fd5d5ba95319197a1e42f9f054

[optimizing] Use more X86_64 addressing modes

Allow constant and memory addresses to more X86_64 instructions.

Add memory formats to X86_64 instructions to match.

Fix a bug in cmpq(CpuRegister, const Address&).

Allow mov <addr>,immediate (instruction 0xC7) to be a valid faulting
instruction.

Change-Id: I5b8a409444426633920cd08e09f687a7afc88a39
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>

runtime/arch/x86/fault_handler_x86.cc

diff --git a/runtime/arch/x86/fault_handler_x86.cc b/runtime/arch/x86/fault_handler_x86.cc
index 27a4adf..8712506 100644
--- a/runtime/arch/x86/fault_handler_x86.cc
+++ b/runtime/arch/x86/fault_handler_x86.cc
@@ -191,6 +191,7 @@
         break;
 
       case 0x81:        // group 1, word immediate.
+      case 0xc7:        // mov
         modrm = *pc++;
         has_modrm = true;
         immediate_size = operand_size_prefix ? 2 : 4;