Restructure to reduce MIR references
This CL eliminates most of the MIR references in the lower-level
code generator. This allows a higher level of code sharing with
the MIR->LIR and GreenlandIR->LIR lowering passes.
The invoke, launchpads and new array support will need some more
extensive refactoring (future CL).
Change-Id: I75f249268c8ac18da1dd9180ff855d5176d6c4fe
diff --git a/src/compiler/codegen/arm/ArchFactory.cc b/src/compiler/codegen/arm/ArchFactory.cc
index c20151e..bc30335 100644
--- a/src/compiler/codegen/arm/ArchFactory.cc
+++ b/src/compiler/codegen/arm/ArchFactory.cc
@@ -28,7 +28,7 @@
void genDebuggerUpdate(CompilationUnit* cUnit, int32_t offset);
-bool genNegLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+bool genNegLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc)
{
rlSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
@@ -95,7 +95,7 @@
}
if (!skipOverflowCheck) {
opRegRegImm(cUnit, kOpSub, rLR, rSP, cUnit->frameSize - (spillCount * 4));
- genRegRegCheck(cUnit, kCondCc, rLR, r12, NULL, kThrowStackOverflow);
+ genRegRegCheck(cUnit, kCondCc, rLR, r12, kThrowStackOverflow);
opRegCopy(cUnit, rSP, rLR); // Establish stack
} else {
opRegImm(cUnit, kOpSub, rSP, cUnit->frameSize - (spillCount * 4));
diff --git a/src/compiler/codegen/arm/Codegen.h b/src/compiler/codegen/arm/Codegen.h
index 10f5e38..22f6157 100644
--- a/src/compiler/codegen/arm/Codegen.h
+++ b/src/compiler/codegen/arm/Codegen.h
@@ -31,19 +31,20 @@
LIR *opRegReg(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int rSrc2);
LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
int checkValue, LIR* target);
-bool genNegLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+bool genNegLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc);
/* Forward declaraton the portable versions due to circular dependency */
-bool genArithOpFloatPortable(CompilationUnit* cUnit, MIR* mir,
+bool genArithOpFloatPortable(CompilationUnit* cUnit, Instruction::Code opcode,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2);
-bool genArithOpDoublePortable(CompilationUnit* cUnit, MIR* mir,
+bool genArithOpDoublePortable(CompilationUnit* cUnit, Instruction::Code opcode,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2);
-bool genConversionPortable(CompilationUnit* cUnit, MIR* mir);
+bool genConversionPortable(CompilationUnit* cUnit, Instruction::Code opcode,
+ RegLocation rlDest, RegLocation rlSrc);
ArmConditionCode oatArmConditionEncoding(ConditionCode code);
diff --git a/src/compiler/codegen/arm/FP/Thumb2VFP.cc b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
index fbce1f5..fb14aec 100644
--- a/src/compiler/codegen/arm/FP/Thumb2VFP.cc
+++ b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
@@ -16,7 +16,7 @@
namespace art {
-bool genArithOpFloat(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+bool genArithOpFloat(CompilationUnit* cUnit, Instruction::Code opcode, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
int op = kThumbBkpt;
@@ -26,7 +26,7 @@
* Don't attempt to optimize register usage since these opcodes call out to
* the handlers.
*/
- switch (mir->dalvikInsn.opcode) {
+ switch (opcode) {
case Instruction::ADD_FLOAT_2ADDR:
case Instruction::ADD_FLOAT:
op = kThumb2Vadds;
@@ -46,7 +46,7 @@
case Instruction::REM_FLOAT_2ADDR:
case Instruction::REM_FLOAT:
case Instruction::NEG_FLOAT: {
- return genArithOpFloatPortable(cUnit, mir, rlDest, rlSrc1, rlSrc2);
+ return genArithOpFloatPortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
}
default:
return true;
@@ -59,13 +59,13 @@
return false;
}
-bool genArithOpDouble(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2)
+bool genArithOpDouble(CompilationUnit* cUnit, Instruction::Code opcode,
+ RegLocation rlDest, RegLocation rlSrc1, RegLocation rlSrc2)
{
int op = kThumbBkpt;
RegLocation rlResult;
- switch (mir->dalvikInsn.opcode) {
+ switch (opcode) {
case Instruction::ADD_DOUBLE_2ADDR:
case Instruction::ADD_DOUBLE:
op = kThumb2Vaddd;
@@ -85,7 +85,7 @@
case Instruction::REM_DOUBLE_2ADDR:
case Instruction::REM_DOUBLE:
case Instruction::NEG_DOUBLE: {
- return genArithOpDoublePortable(cUnit, mir, rlDest, rlSrc1, rlSrc2);
+ return genArithOpDoublePortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
}
default:
return true;
@@ -105,73 +105,53 @@
return false;
}
-bool genConversion(CompilationUnit* cUnit, MIR* mir)
+bool genConversion(CompilationUnit* cUnit, Instruction::Code opcode,
+ RegLocation rlDest, RegLocation rlSrc)
{
- Instruction::Code opcode = mir->dalvikInsn.opcode;
int op = kThumbBkpt;
- bool longSrc = false;
- bool longDest = false;
int srcReg;
- RegLocation rlSrc;
- RegLocation rlDest;
RegLocation rlResult;
switch (opcode) {
case Instruction::INT_TO_FLOAT:
- longSrc = false;
- longDest = false;
op = kThumb2VcvtIF;
break;
case Instruction::FLOAT_TO_INT:
- longSrc = false;
- longDest = false;
op = kThumb2VcvtFI;
break;
case Instruction::DOUBLE_TO_FLOAT:
- longSrc = true;
- longDest = false;
op = kThumb2VcvtDF;
break;
case Instruction::FLOAT_TO_DOUBLE:
- longSrc = false;
- longDest = true;
op = kThumb2VcvtFd;
break;
case Instruction::INT_TO_DOUBLE:
- longSrc = false;
- longDest = true;
op = kThumb2VcvtID;
break;
case Instruction::DOUBLE_TO_INT:
- longSrc = true;
- longDest = false;
op = kThumb2VcvtDI;
break;
case Instruction::LONG_TO_DOUBLE:
case Instruction::FLOAT_TO_LONG:
case Instruction::LONG_TO_FLOAT:
case Instruction::DOUBLE_TO_LONG:
- return genConversionPortable(cUnit, mir);
+ return genConversionPortable(cUnit, opcode, rlDest, rlSrc);
default:
return true;
}
- if (longSrc) {
- rlSrc = oatGetSrcWide(cUnit, mir, 0, 1);
+ if (rlSrc.wide) {
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
srcReg = S2D(rlSrc.lowReg, rlSrc.highReg);
} else {
- rlSrc = oatGetSrc(cUnit, mir, 0);
rlSrc = loadValue(cUnit, rlSrc, kFPReg);
srcReg = rlSrc.lowReg;
}
- if (longDest) {
- rlDest = oatGetDestWide(cUnit, mir, 0, 1);
+ if (rlDest.wide) {
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, (ArmOpcode)op, S2D(rlResult.lowReg, rlResult.highReg),
srcReg);
storeValueWide(cUnit, rlDest, rlResult);
} else {
- rlDest = oatGetDest(cUnit, mir, 0);
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, (ArmOpcode)op, rlResult.lowReg, srcReg);
storeValue(cUnit, rlDest, rlResult);
@@ -233,14 +213,14 @@
}
-bool genCmpFP(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+bool genCmpFP(CompilationUnit* cUnit, Instruction::Code opcode, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
bool isDouble;
int defaultResult;
RegLocation rlResult;
- switch (mir->dalvikInsn.opcode) {
+ switch (opcode) {
case Instruction::CMPL_FLOAT:
isDouble = false;
defaultResult = -1;
diff --git a/src/compiler/codegen/arm/Thumb2/Factory.cc b/src/compiler/codegen/arm/Thumb2/Factory.cc
index 67f7938..c9dbe62 100644
--- a/src/compiler/codegen/arm/Thumb2/Factory.cc
+++ b/src/compiler/codegen/arm/Thumb2/Factory.cc
@@ -774,7 +774,7 @@
* on base (which must have an associated sReg and MIR). If not
* performing null check, incoming MIR can be null.
*/
-LIR* loadBaseDispBody(CompilationUnit* cUnit, MIR* mir, int rBase,
+LIR* loadBaseDispBody(CompilationUnit* cUnit, int rBase,
int displacement, int rDest, int rDestHi, OpSize size,
int sReg)
{
@@ -802,9 +802,9 @@
}
break;
} else {
- res = loadBaseDispBody(cUnit, mir, rBase, displacement, rDest,
+ res = loadBaseDispBody(cUnit, rBase, displacement, rDest,
-1, kWord, sReg);
- loadBaseDispBody(cUnit, NULL, rBase, displacement + 4, rDestHi,
+ loadBaseDispBody(cUnit, rBase, displacement + 4, rDestHi,
-1, kWord, INVALID_SREG);
return res;
}
@@ -890,17 +890,17 @@
return load;
}
-LIR* loadBaseDisp(CompilationUnit* cUnit, MIR* mir, int rBase,
+LIR* loadBaseDisp(CompilationUnit* cUnit, int rBase,
int displacement, int rDest, OpSize size, int sReg)
{
- return loadBaseDispBody(cUnit, mir, rBase, displacement, rDest, -1, size,
+ return loadBaseDispBody(cUnit, rBase, displacement, rDest, -1, size,
sReg);
}
- LIR* loadBaseDispWide(CompilationUnit* cUnit, MIR* mir, int rBase,
+ LIR* loadBaseDispWide(CompilationUnit* cUnit, int rBase,
int displacement, int rDestLo, int rDestHi, int sReg)
{
- return loadBaseDispBody(cUnit, mir, rBase, displacement, rDestLo, rDestHi,
+ return loadBaseDispBody(cUnit, rBase, displacement, rDestLo, rDestHi,
kLong, sReg);
}
@@ -1011,7 +1011,7 @@
void loadPair(CompilationUnit* cUnit, int base, int lowReg, int highReg)
{
- loadBaseDispWide(cUnit, NULL, base, 0, lowReg, highReg, INVALID_SREG);
+ loadBaseDispWide(cUnit, base, 0, lowReg, highReg, INVALID_SREG);
}
LIR* fpRegCopy(CompilationUnit* cUnit, int rDest, int rSrc)
diff --git a/src/compiler/codegen/arm/Thumb2/Gen.cc b/src/compiler/codegen/arm/Thumb2/Gen.cc
index 5252b49..9ec470c 100644
--- a/src/compiler/codegen/arm/Thumb2/Gen.cc
+++ b/src/compiler/codegen/arm/Thumb2/Gen.cc
@@ -163,7 +163,8 @@
// Point of no return - no aborts after this
genPrintLabel(cUnit, mir);
rlObj = loadArg(cUnit, rlObj);
- genIGet(cUnit, mir, size, rlDest, rlObj, longOrDouble, isObject);
+ genIGet(cUnit, fieldIdx, mir->optimizationFlags, size, rlDest, rlObj,
+ longOrDouble, isObject);
return getNextMir(cUnit, bb, mir);
}
@@ -198,7 +199,8 @@
genPrintLabel(cUnit, mir);
rlObj = loadArg(cUnit, rlObj);
rlSrc = loadArg(cUnit, rlSrc);
- genIPut(cUnit, mir, size, rlSrc, rlObj, longOrDouble, isObject);
+ genIPut(cUnit, fieldIdx, mir->optimizationFlags, size, rlSrc, rlObj,
+ longOrDouble, isObject);
return getNextMir(cUnit, bb, mir);
}
@@ -366,10 +368,10 @@
* add rPC, rDisp ; This is the branch from which we compute displacement
* cbnz rIdx, lp
*/
-void genSparseSwitch(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc,
- LIR* labelList)
+void genSparseSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
+ RegLocation rlSrc, LIR* labelList)
{
- const u2* table = cUnit->insns + mir->offset + mir->dalvikInsn.vB;
+ const u2* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
if (cUnit->printMe) {
dumpSparseSwitchTable(table);
}
@@ -377,7 +379,7 @@
SwitchTable *tabRec = (SwitchTable *)oatNew(cUnit, sizeof(SwitchTable),
true, kAllocData);
tabRec->table = table;
- tabRec->vaddr = mir->offset;
+ tabRec->vaddr = cUnit->currentDalvikOffset;
int size = table[1];
tabRec->targets = (LIR* *)oatNew(cUnit, size * sizeof(LIR*), true, kAllocLIR);
oatInsertGrowableList(cUnit, &cUnit->switchTables, (intptr_t)tabRec);
@@ -414,9 +416,10 @@
}
-void genPackedSwitch(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
+void genPackedSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
+ RegLocation rlSrc)
{
- const u2* table = cUnit->insns + mir->offset + mir->dalvikInsn.vB;
+ const u2* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
if (cUnit->printMe) {
dumpPackedSwitchTable(table);
}
@@ -424,7 +427,7 @@
SwitchTable *tabRec = (SwitchTable *)oatNew(cUnit, sizeof(SwitchTable),
true, kAllocData);
tabRec->table = table;
- tabRec->vaddr = mir->offset;
+ tabRec->vaddr = cUnit->currentDalvikOffset;
int size = table[1];
tabRec->targets = (LIR* *)oatNew(cUnit, size * sizeof(LIR*), true, kAllocLIR);
oatInsertGrowableList(cUnit, &cUnit->switchTables, (intptr_t)tabRec);
@@ -470,14 +473,14 @@
*
* Total size is 4+(width * size + 1)/2 16-bit code units.
*/
-void genFillArrayData(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
+void genFillArrayData(CompilationUnit* cUnit, uint32_t tableOffset, RegLocation rlSrc)
{
- const u2* table = cUnit->insns + mir->offset + mir->dalvikInsn.vB;
+ const u2* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
// Add the table to the list - we'll process it later
FillArrayData *tabRec = (FillArrayData *)
oatNew(cUnit, sizeof(FillArrayData), true, kAllocData);
tabRec->table = table;
- tabRec->vaddr = mir->offset;
+ tabRec->vaddr = cUnit->currentDalvikOffset;
u2 width = tabRec->table[1];
u4 size = tabRec->table[2] | (((u4)tabRec->table[3]) << 16);
tabRec->size = (size * width) + 8;
@@ -540,13 +543,13 @@
* preserved.
*
*/
-void genMonitorEnter(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
+void genMonitorEnter(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
{
oatFlushAllRegs(cUnit);
DCHECK_EQ(LW_SHAPE_THIN, 0);
loadValueDirectFixed(cUnit, rlSrc, r0); // Get obj
oatLockCallTemps(cUnit); // Prepare for explicit register usage
- genNullCheck(cUnit, rlSrc.sRegLow, r0, mir);
+ genNullCheck(cUnit, rlSrc.sRegLow, r0, optFlags);
loadWordDisp(cUnit, rSELF, Thread::ThinLockIdOffset().Int32Value(), r2);
newLIR3(cUnit, kThumb2Ldrex, r1, r0,
Object::MonitorOffset().Int32Value() >> 2); // Get object->lock
@@ -574,13 +577,13 @@
* a zero recursion count, it's safe to punch it back to the
* initial, unlock thin state with a store word.
*/
-void genMonitorExit(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
+void genMonitorExit(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
{
DCHECK_EQ(LW_SHAPE_THIN, 0);
oatFlushAllRegs(cUnit);
loadValueDirectFixed(cUnit, rlSrc, r0); // Get obj
oatLockCallTemps(cUnit); // Prepare for explicit register usage
- genNullCheck(cUnit, rlSrc.sRegLow, r0, mir);
+ genNullCheck(cUnit, rlSrc.sRegLow, r0, optFlags);
loadWordDisp(cUnit, r0, Object::MonitorOffset().Int32Value(), r1); // Get lock
loadWordDisp(cUnit, rSELF, Thread::ThinLockIdOffset().Int32Value(), r2);
// Is lock unheld on lock or held by us (==threadId) on unlock?
@@ -614,7 +617,7 @@
* neg rX
* done:
*/
-void genCmpLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+void genCmpLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
LIR* target1;