commit 5192cbb12856b12620dc346758605baaa1469ced
author Yixin Shou <yixin.shou@intel.com> Tue Jul 01 13:48:17 2014 -0400
committer Yixin Shou <yixin.shou@intel.com> Wed Jul 02 06:40:12 2014 -0400
tree 46f8727c0009978e1c15f94ea353a9fc92d2fe42
parent 7a59a24987beb52877b72b4e3f841e406413bb6d

Load 64 bit constant into GPR by single instruction for 64bit mode

This patch load 64 bit constant into a register by a single movabsq
instruction on 64 bit bit instead of previous mov, shift, add
instruction sequences.

Change-Id: I9d013c4f6c0b5c2e43bd125f91436263c7e6028c
Signed-off-by: Yixin Shou <yixin.shou@intel.com>

compiler/dex/quick/x86/assemble_x86.cc

diff --git a/compiler/dex/quick/x86/assemble_x86.cc b/compiler/dex/quick/x86/assemble_x86.cc
index 3f362f2..84dc659 100644
--- a/compiler/dex/quick/x86/assemble_x86.cc
+++ b/compiler/dex/quick/x86/assemble_x86.cc
@@ -208,7 +208,8 @@
   { kX86Mov64RM, kRegMem,    IS_LOAD  | IS_TERTIARY_OP | REG_DEF0_USE1,  { REX_W,             0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RM", "!0r,[!1r+!2d]" },
   { kX86Mov64RA, kRegArray,  IS_LOAD  | IS_QUIN_OP     | REG_DEF0_USE12, { REX_W,             0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RA", "!0r,[!1r+!2r<<!3d+!4d]" },
   { kX86Mov64RT, kRegThread, IS_LOAD  | IS_BINARY_OP   | REG_DEF0,       { THREAD_PREFIX, REX_W, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RT", "!0r,fs:[!1d]" },
-  { kX86Mov64RI, kMovRegImm,            IS_BINARY_OP   | REG_DEF0,       { REX_W,             0, 0xB8, 0, 0, 0, 0, 8, false }, "Mov64RI", "!0r,!1d" },
+  { kX86Mov64RI32, kRegImm,             IS_BINARY_OP   | REG_DEF0,       { REX_W,             0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64RI32", "!0r,!1d" },
+  { kX86Mov64RI64, kMovRegQuadImm,      IS_TERTIARY_OP | REG_DEF0,       { REX_W,             0, 0xB8, 0, 0, 0, 0, 8, false }, "Mov64RI64", "!0r,!1q" },
   { kX86Mov64MI, kMemImm,    IS_STORE | IS_TERTIARY_OP | REG_USE0,       { REX_W,             0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64MI", "[!0r+!1d],!2d" },
   { kX86Mov64AI, kArrayImm,  IS_STORE | IS_QUIN_OP     | REG_USE01,      { REX_W,             0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64AI", "[!0r+!1r<<!2d+!3d],!4d" },
   { kX86Mov64TI, kThreadImm, IS_STORE | IS_BINARY_OP,                    { THREAD_PREFIX, REX_W, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64TI", "fs:[!0d],!1d" },
@@ -723,6 +724,7 @@
       return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1],
                          lir->operands[4]);
     case kMovRegImm:  // lir operands - 0: reg, 1: immediate
+    case kMovRegQuadImm:
       return ((entry->skeleton.prefix1 != 0 || NeedsRex(lir->operands[0])) ? 1 : 0) + 1 +
           entry->skeleton.immediate_bytes;
     case kShiftRegImm:  // lir operands - 0: reg, 1: immediate
@@ -1787,6 +1789,12 @@
       case kMovRegImm:  // lir operands - 0: reg, 1: immediate
         EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);
         break;
+      case kMovRegQuadImm: {
+          int64_t value = static_cast<int64_t>(static_cast<int64_t>(lir->operands[1]) << 32 |
+                          static_cast<uint32_t>(lir->operands[2]));
+          EmitMovRegImm(entry, lir->operands[0], value);
+        }
+        break;
       case kShiftRegImm:  // lir operands - 0: reg, 1: immediate
         EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);
         break;