commit 51aff3a6564303cab0b7ac82495b4e2e349c6ff3
author Alexey Frunze <Alexey.Frunze@imgtec.com> Thu Mar 17 17:21:45 2016 -0700
committer Alexey Frunze <Alexey.Frunze@imgtec.com> Mon Mar 21 15:23:42 2016 -0700
tree 783344fdc2f757a8fce4ac1b565e2b2798415d2d
parent 6a329292736c3dd74e9c8cb319c2a233d07fe524

MIPS32: Implement UnsafeCASInt and UnsafeCASObject intrinsics.

Change-Id: Ie871763b9a36075fd3d70ee6e2e241ae1ccc36cf

compiler/utils/mips/assembler_mips.cc

diff --git a/compiler/utils/mips/assembler_mips.cc b/compiler/utils/mips/assembler_mips.cc
index 7c41813..a1798c0 100644
--- a/compiler/utils/mips/assembler_mips.cc
+++ b/compiler/utils/mips/assembler_mips.cc
@@ -485,6 +485,28 @@
   EmitI(0x2e, rs, rt, imm16);
 }
 
+void MipsAssembler::LlR2(Register rt, Register base, int16_t imm16) {
+  CHECK(!IsR6());
+  EmitI(0x30, base, rt, imm16);
+}
+
+void MipsAssembler::ScR2(Register rt, Register base, int16_t imm16) {
+  CHECK(!IsR6());
+  EmitI(0x38, base, rt, imm16);
+}
+
+void MipsAssembler::LlR6(Register rt, Register base, int16_t imm9) {
+  CHECK(IsR6());
+  CHECK(IsInt<9>(imm9));
+  EmitI(0x1f, base, rt, ((imm9 & 0x1ff) << 7) | 0x36);
+}
+
+void MipsAssembler::ScR6(Register rt, Register base, int16_t imm9) {
+  CHECK(IsR6());
+  CHECK(IsInt<9>(imm9));
+  EmitI(0x1f, base, rt, ((imm9 & 0x1ff) << 7) | 0x26);
+}
+
 void MipsAssembler::Slt(Register rd, Register rs, Register rt) {
   EmitR(0, rs, rt, rd, 0, 0x2a);
 }

compiler/utils/mips/assembler_mips.h

diff --git a/compiler/utils/mips/assembler_mips.h b/compiler/utils/mips/assembler_mips.h
index a7179fd..ffac4c4 100644
--- a/compiler/utils/mips/assembler_mips.h
+++ b/compiler/utils/mips/assembler_mips.h
@@ -191,6 +191,11 @@
   void Swl(Register rt, Register rs, uint16_t imm16);
   void Swr(Register rt, Register rs, uint16_t imm16);
 
+  void LlR2(Register rt, Register base, int16_t imm16 = 0);
+  void ScR2(Register rt, Register base, int16_t imm16 = 0);
+  void LlR6(Register rt, Register base, int16_t imm9 = 0);
+  void ScR6(Register rt, Register base, int16_t imm9 = 0);
+
   void Slt(Register rd, Register rs, Register rt);
   void Sltu(Register rd, Register rs, Register rt);
   void Slti(Register rt, Register rs, uint16_t imm16);

compiler/utils/mips/assembler_mips_test.cc

diff --git a/compiler/utils/mips/assembler_mips_test.cc b/compiler/utils/mips/assembler_mips_test.cc
index 9e27f07..cec43ba 100644
--- a/compiler/utils/mips/assembler_mips_test.cc
+++ b/compiler/utils/mips/assembler_mips_test.cc
@@ -489,6 +489,14 @@
   DriverStr(RepeatRRIb(&mips::MipsAssembler::Swr, -16, "swr ${reg1}, {imm}(${reg2})"), "Swr");
 }
 
+TEST_F(AssemblerMIPSTest, LlR2) {
+  DriverStr(RepeatRRIb(&mips::MipsAssembler::LlR2, -16, "ll ${reg1}, {imm}(${reg2})"), "LlR2");
+}
+
+TEST_F(AssemblerMIPSTest, ScR2) {
+  DriverStr(RepeatRRIb(&mips::MipsAssembler::ScR2, -16, "sc ${reg1}, {imm}(${reg2})"), "ScR2");
+}
+
 TEST_F(AssemblerMIPSTest, Slt) {
   DriverStr(RepeatRRR(&mips::MipsAssembler::Slt, "slt ${reg1}, ${reg2}, ${reg3}"), "Slt");
 }