commit 582f541b35f40b75f2629a41259d2162608647d5
author Andreas Gampe <agampe@google.com> Tue Jan 20 18:06:47 2015 -0800
committer Andreas Gampe <agampe@google.com> Tue Jan 20 18:06:47 2015 -0800
tree 6d6f6be798cabf970cbe94df020e16e8de7bb96b
parent b061b894260df6b68bb8a89ed4a1e85e576bb696

ART: Fix arm64 backend

Fix a register size problem after previous commit
f681570077563bb529a30f9e7c572b837cecfb83.

Change-Id: If04e647324bcd6fe279c25e70214a9f7c5b816ec

compiler/dex/quick/arm64/utility_arm64.cc

diff --git a/compiler/dex/quick/arm64/utility_arm64.cc b/compiler/dex/quick/arm64/utility_arm64.cc
index 1c29ab8..a331f41 100644
--- a/compiler/dex/quick/arm64/utility_arm64.cc
+++ b/compiler/dex/quick/arm64/utility_arm64.cc
@@ -1256,7 +1256,9 @@
     // TODO: cleaner support for index/displacement registers?  Not a reference, but must match width.
     RegStorage r_scratch = AllocTempWide();
     LoadConstantWide(r_scratch, displacement);
-    load = LoadBaseIndexed(r_base, r_scratch, r_dest, 0, size);
+    load = LoadBaseIndexed(r_base, r_scratch,
+                           (size == kReference) ? As64BitReg(r_dest) : r_dest,
+                           0, size);
     FreeTemp(r_scratch);
   }
 
@@ -1344,7 +1346,9 @@
     // Use long sequence.
     RegStorage r_scratch = AllocTempWide();
     LoadConstantWide(r_scratch, displacement);
-    store = StoreBaseIndexed(r_base, r_scratch, r_src, 0, size);
+    store = StoreBaseIndexed(r_base, r_scratch,
+                             (size == kReference) ? As64BitReg(r_src) : r_src,
+                             0, size);
     FreeTemp(r_scratch);
   }