ARM64: Remove suspend register.
It also clean up build/remove frame used by JNI compiler and generates
stp/ldp instead of str/ldr. Also x19 has been unblocked in both quick and
optimizing compiler.
Change-Id: Idbeac0942265f493266b2ef9b7a65bb4054f0e2d
diff --git a/compiler/dex/quick/arm64/arm64_lir.h b/compiler/dex/quick/arm64/arm64_lir.h
index f6fa938..5bf77aa 100644
--- a/compiler/dex/quick/arm64/arm64_lir.h
+++ b/compiler/dex/quick/arm64/arm64_lir.h
@@ -36,8 +36,7 @@
* the linker, by the trampolines and other stubs (the backend uses
* these as temporary registers).
* r18 : (rxSELF) is reserved (pointer to thread-local storage).
- * r19 : (rwSUSPEND) is reserved (suspend check/debugger assist).
- * r20-r29: Callee save registers (promotion targets).
+ * r19-r29: Callee save registers (promotion targets).
* r30 : (lr) is reserved (the link register).
* rsp : (sp) is reserved (the stack pointer).
* rzr : (zr) is reserved (the zero register).
@@ -146,7 +145,6 @@
// Aliases which are not defined in "ARM Architecture Reference, register names".
rxIP0 = rx16,
rxIP1 = rx17,
- rxSUSPEND = rx19,
rxSELF = rx18,
rxLR = rx30,
/*
@@ -156,7 +154,6 @@
*/
rwIP0 = rw16,
rwIP1 = rw17,
- rwSUSPEND = rw19,
rwSELF = rw18,
rwLR = rw30,
};
@@ -176,12 +173,10 @@
constexpr RegStorage rs_xIP1(RegStorage::kValid | rxIP1);
constexpr RegStorage rs_wIP1(RegStorage::kValid | rwIP1);
// Reserved registers.
-constexpr RegStorage rs_xSUSPEND(RegStorage::kValid | rxSUSPEND);
constexpr RegStorage rs_xSELF(RegStorage::kValid | rxSELF);
constexpr RegStorage rs_sp(RegStorage::kValid | rsp);
constexpr RegStorage rs_xLR(RegStorage::kValid | rxLR);
// TODO: eliminate the need for these.
-constexpr RegStorage rs_wSUSPEND(RegStorage::kValid | rwSUSPEND);
constexpr RegStorage rs_wSELF(RegStorage::kValid | rwSELF);
constexpr RegStorage rs_wsp(RegStorage::kValid | rwsp);
constexpr RegStorage rs_wLR(RegStorage::kValid | rwLR);
diff --git a/compiler/dex/quick/arm64/int_arm64.cc b/compiler/dex/quick/arm64/int_arm64.cc
index 20f61f2..b7dbd0a 100644
--- a/compiler/dex/quick/arm64/int_arm64.cc
+++ b/compiler/dex/quick/arm64/int_arm64.cc
@@ -1010,8 +1010,12 @@
// Test suspend flag, return target of taken suspend branch
LIR* Arm64Mir2Lir::OpTestSuspend(LIR* target) {
- NewLIR3(kA64Subs3rRd, rwSUSPEND, rwSUSPEND, 1);
- return OpCondBranch((target == NULL) ? kCondEq : kCondNe, target);
+ RegStorage r_tmp = AllocTemp();
+ LoadBaseDisp(rs_xSELF, Thread::ThreadFlagsOffset<kArm64PointerSize>().Int32Value(), r_tmp,
+ kUnsignedHalf, kNotVolatile);
+ LIR* cmp_branch = OpCmpImmBranch(target == nullptr ? kCondNe: kCondEq, r_tmp, 0, target);
+ FreeTemp(r_tmp);
+ return cmp_branch;
}
// Decrement register and branch on condition
diff --git a/compiler/dex/quick/arm64/target_arm64.cc b/compiler/dex/quick/arm64/target_arm64.cc
index c5c0dc5..fc32ecd 100644
--- a/compiler/dex/quick/arm64/target_arm64.cc
+++ b/compiler/dex/quick/arm64/target_arm64.cc
@@ -53,10 +53,9 @@
rs_d24, rs_d25, rs_d26, rs_d27, rs_d28, rs_d29, rs_d30, rs_d31};
// Note: we are not able to call to C function since rs_xSELF is a special register need to be
// preserved but would be scratched by native functions follow aapcs64.
-static constexpr RegStorage reserved_regs_arr[] =
- {rs_wSUSPEND, rs_wSELF, rs_wsp, rs_wLR, rs_wzr};
-static constexpr RegStorage reserved64_regs_arr[] =
- {rs_xSUSPEND, rs_xSELF, rs_sp, rs_xLR, rs_xzr};
+static constexpr RegStorage reserved_regs_arr[] = {rs_wSELF, rs_wsp, rs_wLR, rs_wzr};
+static constexpr RegStorage reserved64_regs_arr[] = {rs_xSELF, rs_sp, rs_xLR, rs_xzr};
+
static constexpr RegStorage core_temps_arr[] =
{rs_w0, rs_w1, rs_w2, rs_w3, rs_w4, rs_w5, rs_w6, rs_w7,
rs_w8, rs_w9, rs_w10, rs_w11, rs_w12, rs_w13, rs_w14, rs_w15, rs_w16,
@@ -110,7 +109,7 @@
RegStorage res_reg = RegStorage::InvalidReg();
switch (reg) {
case kSelf: res_reg = rs_wSELF; break;
- case kSuspend: res_reg = rs_wSUSPEND; break;
+ case kSuspend: res_reg = RegStorage::InvalidReg(); break;
case kLr: res_reg = rs_wLR; break;
case kPc: res_reg = RegStorage::InvalidReg(); break;
case kSp: res_reg = rs_wsp; break;