ART: Add 16-bit Thumb2 ROR, NEGS and CMP for high registers.
Also clean up the usage of set_cc flag. Define a SetCc
enumeration that specifies whether to set or keep condition
codes or whether we don't care and a 16-bit instruction
should be selected if one exists.
This reduces the size of Nexus 5 boot.oat by 44KiB (when
compiled with Optimizing which is not the default yet).
Change-Id: I047072dc197ea678bf2019c01bcb28943fa9b604
diff --git a/compiler/utils/arm/assembler_arm.cc b/compiler/utils/arm/assembler_arm.cc
index 0e3e08c..807beda 100644
--- a/compiler/utils/arm/assembler_arm.cc
+++ b/compiler/utils/arm/assembler_arm.cc
@@ -137,10 +137,14 @@
if (rs_ == kNoRegister) {
// Immediate shift.
if (shift_ == RRX) {
+ DCHECK_EQ(immed_, 0u);
// RRX is encoded as an ROR with imm 0.
return ROR << 4 | static_cast<uint32_t>(rm_);
} else {
- uint32_t imm3 = immed_ >> 2;
+ DCHECK((1 <= immed_ && immed_ <= 31) ||
+ (immed_ == 0u && shift_ == LSL) ||
+ (immed_ == 32u && (shift_ == ASR || shift_ == LSR)));
+ uint32_t imm3 = (immed_ >> 2) & 7 /* 0b111*/;
uint32_t imm2 = immed_ & 3U /* 0b11 */;
return imm3 << 12 | imm2 << 6 | shift_ << 4 |