commit 7934ac288acfb2552bb0b06ec1f61e5820d924a4
author Brian Carlstrom <bdc@google.com> Fri Jul 26 10:54:15 2013 -0700
committer Brian Carlstrom <bdc@google.com> Fri Jul 26 11:55:10 2013 -0700
tree 43f3acd8af7fd34d4ae7b64f6e06bb8429d74bb8
parent fb331d7ca004f39608fcfdae49d38df90c702ea9

Fix cpplint whitespace/comments issues

Change-Id: Iae286862c85fb8fd8901eae1204cd6d271d69496

compiler/dex/quick/x86/assemble_x86.cc

diff --git a/compiler/dex/quick/x86/assemble_x86.cc b/compiler/dex/quick/x86/assemble_x86.cc
index d864115..e883432 100644
--- a/compiler/dex/quick/x86/assemble_x86.cc
+++ b/compiler/dex/quick/x86/assemble_x86.cc
@@ -474,7 +474,7 @@
         return ComputeSize(entry, lir->operands[1], 0x12345678, true);
       } else {
         DCHECK(entry->opcode == kX86PcRelAdr);
-        return 5; // opcode with reg + 4 byte immediate
+        return 5;  // opcode with reg + 4 byte immediate
       }
     case kMacro:
       DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));
@@ -1342,7 +1342,7 @@
       case kShiftRegImm:  // lir operands - 0: reg, 1: immediate
         EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);
         break;
-      case kShiftRegCl: // lir operands - 0: reg, 1: cl
+      case kShiftRegCl:  // lir operands - 0: reg, 1: cl
         EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);
         break;
       case kRegCond:  // lir operands - 0: reg, 1: condition