commit 7fee84c087e0f903e7d43bef180df047db1c8051
author Vladimir Marko <vmarko@google.com> Fri Aug 21 18:39:26 2015 +0000
committer Vladimir Marko <vmarko@google.com> Fri Aug 21 18:39:26 2015 +0000
tree c35065aeef23f857563eacd82e55ae47d8ceb67c
parent a29449dcf57c57fe0876f51367985477317cc557

Revert "[MIPS] Use hard float calling convention for managed code"

MipsMir2Lir::LockCallTemps() is broken for secondary architecture on aosp_mips64-eng.

This reverts commit a29449dcf57c57fe0876f51367985477317cc557.

Change-Id: I480ea7569d73aea7894fc0a6dd804b1135286a37

compiler/dex/quick/mips/codegen_mips.h

diff --git a/compiler/dex/quick/mips/codegen_mips.h b/compiler/dex/quick/mips/codegen_mips.h
index 2173253..43fbcbd 100644
--- a/compiler/dex/quick/mips/codegen_mips.h
+++ b/compiler/dex/quick/mips/codegen_mips.h
@@ -29,18 +29,15 @@
  protected:
   class InToRegStorageMipsMapper : public InToRegStorageMapper {
    public:
-    explicit InToRegStorageMipsMapper(Mir2Lir* m2l) : m2l_(m2l), cur_core_reg_(0), cur_fpu_reg_(0)
-        {}
+    explicit InToRegStorageMipsMapper(Mir2Lir* m2l) : m2l_(m2l), cur_core_reg_(0) {}
     virtual RegStorage GetNextReg(ShortyArg arg);
     virtual void Reset() OVERRIDE {
       cur_core_reg_ = 0;
-      cur_fpu_reg_ = 0;
     }
    protected:
     Mir2Lir* m2l_;
    private:
     size_t cur_core_reg_;
-    size_t cur_fpu_reg_;
   };
 
   class InToRegStorageMips64Mapper : public InToRegStorageMapper {

compiler/dex/quick/mips/target_mips.cc

diff --git a/compiler/dex/quick/mips/target_mips.cc b/compiler/dex/quick/mips/target_mips.cc
index 8abd592..ec4bad7 100644
--- a/compiler/dex/quick/mips/target_mips.cc
+++ b/compiler/dex/quick/mips/target_mips.cc
@@ -195,7 +195,7 @@
 // Return a target-dependent special register.
 RegStorage MipsMir2Lir::TargetReg(SpecialTargetRegister reg, WideKind wide_kind) {
   if (!cu_->target64 && wide_kind == kWide) {
-    DCHECK((kArg0 <= reg && reg < kArg7) || (kFArg0 == reg) || (kFArg2 == reg) || (kRet0 == reg));
+    DCHECK((kArg0 <= reg && reg < kArg7) || (kFArg0 <= reg && reg < kFArg15) || (kRet0 == reg));
     RegStorage ret_reg = RegStorage::MakeRegPair(TargetReg(reg),
                                      TargetReg(static_cast<SpecialTargetRegister>(reg + 1)));
     if (!fpuIs32Bit_ && ret_reg.IsFloat()) {
@@ -250,27 +250,14 @@
 RegStorage MipsMir2Lir::InToRegStorageMipsMapper::GetNextReg(ShortyArg arg) {
   const SpecialTargetRegister coreArgMappingToPhysicalReg[] = {kArg1, kArg2, kArg3};
   const size_t coreArgMappingToPhysicalRegSize = arraysize(coreArgMappingToPhysicalReg);
-  const SpecialTargetRegister fpuArgMappingToPhysicalReg[] = {kFArg0, kFArg2};
-  const size_t fpuArgMappingToPhysicalRegSize = arraysize(fpuArgMappingToPhysicalReg);
 
   RegStorage result = RegStorage::InvalidReg();
-  if (arg.IsFP()) {
-    if (cur_fpu_reg_ < fpuArgMappingToPhysicalRegSize) {
-      result = m2l_->TargetReg(fpuArgMappingToPhysicalReg[cur_fpu_reg_++],
-                               arg.IsWide() ? kWide : kNotWide);
-    }
-  } else {
-    if (cur_core_reg_ < coreArgMappingToPhysicalRegSize) {
-      if (arg.IsWide() && cur_core_reg_ == 0) {
-        // Don't use a1-a2 as a register pair, move to a2-a3 instead.
-        cur_core_reg_++;
-      }
-      result = m2l_->TargetReg(coreArgMappingToPhysicalReg[cur_core_reg_++],
-                               arg.IsRef() ? kRef : kNotWide);
-      if (arg.IsWide() && cur_core_reg_ < coreArgMappingToPhysicalRegSize) {
-        result = RegStorage::MakeRegPair(
-            result, m2l_->TargetReg(coreArgMappingToPhysicalReg[cur_core_reg_++], kNotWide));
-      }
+  if (cur_core_reg_ < coreArgMappingToPhysicalRegSize) {
+    result = m2l_->TargetReg(coreArgMappingToPhysicalReg[cur_core_reg_++],
+                             arg.IsRef() ? kRef : kNotWide);
+    if (arg.IsWide() && cur_core_reg_ < coreArgMappingToPhysicalRegSize) {
+      result = RegStorage::MakeRegPair(
+          result, m2l_->TargetReg(coreArgMappingToPhysicalReg[cur_core_reg_++], kNotWide));
     }
   }
   return result;
@@ -667,18 +654,6 @@
     LockTemp(TargetReg(kArg5));
     LockTemp(TargetReg(kArg6));
     LockTemp(TargetReg(kArg7));
-  } else {
-    LockTemp(TargetReg(kFArg0));
-    LockTemp(TargetReg(kFArg1));
-    LockTemp(TargetReg(kFArg2));
-    LockTemp(TargetReg(kFArg3));
-    if (fpuIs32Bit_) {
-      LockTemp(rs_rD6_fr0);
-      LockTemp(rs_rD7_fr0);
-    } else {
-      LockTemp(rs_rD6_fr1);
-      LockTemp(rs_rD7_fr1);
-    }
   }
 }
 
@@ -693,18 +668,6 @@
     FreeTemp(TargetReg(kArg5));
     FreeTemp(TargetReg(kArg6));
     FreeTemp(TargetReg(kArg7));
-  } else {
-    FreeTemp(TargetReg(kFArg0));
-    FreeTemp(TargetReg(kFArg1));
-    FreeTemp(TargetReg(kFArg2));
-    FreeTemp(TargetReg(kFArg3));
-    if (fpuIs32Bit_) {
-      FreeTemp(rs_rD6_fr0);
-      FreeTemp(rs_rD7_fr0);
-    } else {
-      FreeTemp(rs_rD6_fr1);
-      FreeTemp(rs_rD7_fr1);
-    }
   }
   FreeTemp(TargetReg(kHiddenArg));
 }