ART: Clean up arm64 kNumberOfXRegisters usage.
Avoid undefined behavior for arm64 stemming from 1u << 32 in
loops with upper bound kNumberOfXRegisters.
Create iterators for enumerating bits in an integer either
from high to low or from low to high and use them for
<arch>Context::FillCalleeSaves() on all architectures.
Refactor runtime/utils.{h,cc} by moving all bit-fiddling
functions to runtime/base/bit_utils.{h,cc} (together with
the new bit iterators) and all time-related functions to
runtime/base/time_utils.{h,cc}. Improve test coverage and
fix some corner cases for the bit-fiddling functions.
Bug: 13925192
Change-Id: I704884dab15b41ecf7a1c47d397ab1c3fc7ee0f7
diff --git a/runtime/arch/arm/context_arm.cc b/runtime/arch/arm/context_arm.cc
index 5bd23d0..c0e658c 100644
--- a/runtime/arch/arm/context_arm.cc
+++ b/runtime/arch/arm/context_arm.cc
@@ -16,9 +16,9 @@
#include "context_arm.h"
+#include "base/bit_utils.h"
#include "mirror/art_method-inl.h"
#include "quick/quick_method_frame_info.h"
-#include "utils.h"
namespace art {
namespace arm {
@@ -26,12 +26,8 @@
static constexpr uint32_t gZero = 0;
void ArmContext::Reset() {
- for (size_t i = 0; i < kNumberOfCoreRegisters; i++) {
- gprs_[i] = nullptr;
- }
- for (size_t i = 0; i < kNumberOfSRegisters; i++) {
- fprs_[i] = nullptr;
- }
+ std::fill_n(gprs_, arraysize(gprs_), nullptr);
+ std::fill_n(fprs_, arraysize(fprs_), nullptr);
gprs_[SP] = &sp_;
gprs_[PC] = &pc_;
// Initialize registers with easy to spot debug values.
@@ -42,29 +38,23 @@
void ArmContext::FillCalleeSaves(const StackVisitor& fr) {
mirror::ArtMethod* method = fr.GetMethod();
const QuickMethodFrameInfo frame_info = method->GetQuickFrameInfo();
- size_t spill_count = POPCOUNT(frame_info.CoreSpillMask());
- size_t fp_spill_count = POPCOUNT(frame_info.FpSpillMask());
- if (spill_count > 0) {
- // Lowest number spill is farthest away, walk registers and fill into context
- int j = 1;
- for (size_t i = 0; i < kNumberOfCoreRegisters; i++) {
- if (((frame_info.CoreSpillMask() >> i) & 1) != 0) {
- gprs_[i] = fr.CalleeSaveAddress(spill_count - j, frame_info.FrameSizeInBytes());
- j++;
- }
- }
+ int spill_pos = 0;
+
+ // Core registers come first, from the highest down to the lowest.
+ uint32_t core_regs = frame_info.CoreSpillMask();
+ DCHECK_EQ(0u, core_regs & (static_cast<uint32_t>(-1) << kNumberOfCoreRegisters));
+ for (uint32_t core_reg : HighToLowBits(core_regs)) {
+ gprs_[core_reg] = fr.CalleeSaveAddress(spill_pos, frame_info.FrameSizeInBytes());
+ ++spill_pos;
}
- if (fp_spill_count > 0) {
- // Lowest number spill is farthest away, walk registers and fill into context
- int j = 1;
- for (size_t i = 0; i < kNumberOfSRegisters; i++) {
- if (((frame_info.FpSpillMask() >> i) & 1) != 0) {
- fprs_[i] = fr.CalleeSaveAddress(spill_count + fp_spill_count - j,
- frame_info.FrameSizeInBytes());
- j++;
- }
- }
+ DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()));
+
+ // FP registers come second, from the highest down to the lowest.
+ for (uint32_t fp_reg : HighToLowBits(frame_info.FpSpillMask())) {
+ fprs_[fp_reg] = fr.CalleeSaveAddress(spill_pos, frame_info.FrameSizeInBytes());
+ ++spill_pos;
}
+ DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()) + POPCOUNT(frame_info.FpSpillMask()));
}
void ArmContext::SetGPR(uint32_t reg, uintptr_t value) {
diff --git a/runtime/arch/arm/quick_method_frame_info_arm.h b/runtime/arch/arm/quick_method_frame_info_arm.h
index c1f3fc2..5580ee4 100644
--- a/runtime/arch/arm/quick_method_frame_info_arm.h
+++ b/runtime/arch/arm/quick_method_frame_info_arm.h
@@ -17,10 +17,10 @@
#ifndef ART_RUNTIME_ARCH_ARM_QUICK_METHOD_FRAME_INFO_ARM_H_
#define ART_RUNTIME_ARCH_ARM_QUICK_METHOD_FRAME_INFO_ARM_H_
+#include "base/bit_utils.h"
#include "quick/quick_method_frame_info.h"
#include "registers_arm.h"
#include "runtime.h" // for Runtime::CalleeSaveType.
-#include "utils.h"
namespace art {
namespace arm {
diff --git a/runtime/arch/arm64/context_arm64.cc b/runtime/arch/arm64/context_arm64.cc
index ec9c122..9c7bb55 100644
--- a/runtime/arch/arm64/context_arm64.cc
+++ b/runtime/arch/arm64/context_arm64.cc
@@ -18,9 +18,9 @@
#include "context_arm64.h"
+#include "base/bit_utils.h"
#include "mirror/art_method-inl.h"
#include "quick/quick_method_frame_info.h"
-#include "utils.h"
namespace art {
namespace arm64 {
@@ -28,12 +28,8 @@
static constexpr uint64_t gZero = 0;
void Arm64Context::Reset() {
- for (size_t i = 0; i < kNumberOfXRegisters; i++) {
- gprs_[i] = nullptr;
- }
- for (size_t i = 0; i < kNumberOfDRegisters; i++) {
- fprs_[i] = nullptr;
- }
+ std::fill_n(gprs_, arraysize(gprs_), nullptr);
+ std::fill_n(fprs_, arraysize(fprs_), nullptr);
gprs_[SP] = &sp_;
gprs_[LR] = &pc_;
// Initialize registers with easy to spot debug values.
@@ -44,30 +40,21 @@
void Arm64Context::FillCalleeSaves(const StackVisitor& fr) {
mirror::ArtMethod* method = fr.GetMethod();
const QuickMethodFrameInfo frame_info = method->GetQuickFrameInfo();
- size_t spill_count = POPCOUNT(frame_info.CoreSpillMask());
- size_t fp_spill_count = POPCOUNT(frame_info.FpSpillMask());
- if (spill_count > 0) {
- // Lowest number spill is farthest away, walk registers and fill into context.
- int j = 1;
- for (size_t i = 0; i < kNumberOfXRegisters; i++) {
- if (((frame_info.CoreSpillMask() >> i) & 1) != 0) {
- gprs_[i] = fr.CalleeSaveAddress(spill_count - j, frame_info.FrameSizeInBytes());
- j++;
- }
- }
- }
+ int spill_pos = 0;
- if (fp_spill_count > 0) {
- // Lowest number spill is farthest away, walk registers and fill into context.
- int j = 1;
- for (size_t i = 0; i < kNumberOfDRegisters; i++) {
- if (((frame_info.FpSpillMask() >> i) & 1) != 0) {
- fprs_[i] = fr.CalleeSaveAddress(spill_count + fp_spill_count - j,
- frame_info.FrameSizeInBytes());
- j++;
- }
- }
+ // Core registers come first, from the highest down to the lowest.
+ for (uint32_t core_reg : HighToLowBits(frame_info.CoreSpillMask())) {
+ gprs_[core_reg] = fr.CalleeSaveAddress(spill_pos, frame_info.FrameSizeInBytes());
+ ++spill_pos;
}
+ DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()));
+
+ // FP registers come second, from the highest down to the lowest.
+ for (uint32_t fp_reg : HighToLowBits(frame_info.FpSpillMask())) {
+ fprs_[fp_reg] = fr.CalleeSaveAddress(spill_pos, frame_info.FrameSizeInBytes());
+ ++spill_pos;
+ }
+ DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()) + POPCOUNT(frame_info.FpSpillMask()));
}
void Arm64Context::SetGPR(uint32_t reg, uintptr_t value) {
diff --git a/runtime/arch/arm64/quick_method_frame_info_arm64.h b/runtime/arch/arm64/quick_method_frame_info_arm64.h
index 61b4dff..dfb3f99 100644
--- a/runtime/arch/arm64/quick_method_frame_info_arm64.h
+++ b/runtime/arch/arm64/quick_method_frame_info_arm64.h
@@ -17,10 +17,10 @@
#ifndef ART_RUNTIME_ARCH_ARM64_QUICK_METHOD_FRAME_INFO_ARM64_H_
#define ART_RUNTIME_ARCH_ARM64_QUICK_METHOD_FRAME_INFO_ARM64_H_
+#include "base/bit_utils.h"
#include "quick/quick_method_frame_info.h"
#include "registers_arm64.h"
#include "runtime.h" // for Runtime::CalleeSaveType.
-#include "utils.h" // for POPCOUNT
namespace art {
namespace arm64 {
diff --git a/runtime/arch/mips/context_mips.cc b/runtime/arch/mips/context_mips.cc
index 3b525be..f0c893a 100644
--- a/runtime/arch/mips/context_mips.cc
+++ b/runtime/arch/mips/context_mips.cc
@@ -16,9 +16,9 @@
#include "context_mips.h"
+#include "base/bit_utils.h"
#include "mirror/art_method-inl.h"
#include "quick/quick_method_frame_info.h"
-#include "utils.h"
namespace art {
namespace mips {
@@ -26,12 +26,8 @@
static constexpr uint32_t gZero = 0;
void MipsContext::Reset() {
- for (size_t i = 0; i < kNumberOfCoreRegisters; i++) {
- gprs_[i] = nullptr;
- }
- for (size_t i = 0; i < kNumberOfFRegisters; i++) {
- fprs_[i] = nullptr;
- }
+ std::fill_n(gprs_, arraysize(gprs_), nullptr);
+ std::fill_n(fprs_, arraysize(fprs_), nullptr);
gprs_[SP] = &sp_;
gprs_[RA] = &ra_;
// Initialize registers with easy to spot debug values.
@@ -42,29 +38,21 @@
void MipsContext::FillCalleeSaves(const StackVisitor& fr) {
mirror::ArtMethod* method = fr.GetMethod();
const QuickMethodFrameInfo frame_info = method->GetQuickFrameInfo();
- size_t spill_count = POPCOUNT(frame_info.CoreSpillMask());
- size_t fp_spill_count = POPCOUNT(frame_info.FpSpillMask());
- if (spill_count > 0) {
- // Lowest number spill is farthest away, walk registers and fill into context.
- int j = 1;
- for (size_t i = 0; i < kNumberOfCoreRegisters; i++) {
- if (((frame_info.CoreSpillMask() >> i) & 1) != 0) {
- gprs_[i] = fr.CalleeSaveAddress(spill_count - j, frame_info.FrameSizeInBytes());
- j++;
- }
- }
+ int spill_pos = 0;
+
+ // Core registers come first, from the highest down to the lowest.
+ for (uint32_t core_reg : HighToLowBits(frame_info.CoreSpillMask())) {
+ gprs_[core_reg] = fr.CalleeSaveAddress(spill_pos, frame_info.FrameSizeInBytes());
+ ++spill_pos;
}
- if (fp_spill_count > 0) {
- // Lowest number spill is farthest away, walk registers and fill into context.
- int j = 1;
- for (size_t i = 0; i < kNumberOfFRegisters; i++) {
- if (((frame_info.FpSpillMask() >> i) & 1) != 0) {
- fprs_[i] = fr.CalleeSaveAddress(spill_count + fp_spill_count - j,
- frame_info.FrameSizeInBytes());
- j++;
- }
- }
+ DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()));
+
+ // FP registers come second, from the highest down to the lowest.
+ for (uint32_t fp_reg : HighToLowBits(frame_info.FpSpillMask())) {
+ fprs_[fp_reg] = fr.CalleeSaveAddress(spill_pos, frame_info.FrameSizeInBytes());
+ ++spill_pos;
}
+ DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()) + POPCOUNT(frame_info.FpSpillMask()));
}
void MipsContext::SetGPR(uint32_t reg, uintptr_t value) {
diff --git a/runtime/arch/mips/quick_method_frame_info_mips.h b/runtime/arch/mips/quick_method_frame_info_mips.h
index 5fbffbc..97b295f 100644
--- a/runtime/arch/mips/quick_method_frame_info_mips.h
+++ b/runtime/arch/mips/quick_method_frame_info_mips.h
@@ -17,6 +17,7 @@
#ifndef ART_RUNTIME_ARCH_MIPS_QUICK_METHOD_FRAME_INFO_MIPS_H_
#define ART_RUNTIME_ARCH_MIPS_QUICK_METHOD_FRAME_INFO_MIPS_H_
+#include "base/bit_utils.h"
#include "quick/quick_method_frame_info.h"
#include "registers_mips.h"
#include "runtime.h" // for Runtime::CalleeSaveType.
diff --git a/runtime/arch/mips64/context_mips64.cc b/runtime/arch/mips64/context_mips64.cc
index 6b3f4c9..8ce6cf0 100644
--- a/runtime/arch/mips64/context_mips64.cc
+++ b/runtime/arch/mips64/context_mips64.cc
@@ -16,9 +16,9 @@
#include "context_mips64.h"
+#include "base/bit_utils.h"
#include "mirror/art_method-inl.h"
#include "quick/quick_method_frame_info.h"
-#include "utils.h"
namespace art {
namespace mips64 {
@@ -26,12 +26,8 @@
static constexpr uintptr_t gZero = 0;
void Mips64Context::Reset() {
- for (size_t i = 0; i < kNumberOfGpuRegisters; i++) {
- gprs_[i] = nullptr;
- }
- for (size_t i = 0; i < kNumberOfFpuRegisters; i++) {
- fprs_[i] = nullptr;
- }
+ std::fill_n(gprs_, arraysize(gprs_), nullptr);
+ std::fill_n(fprs_, arraysize(fprs_), nullptr);
gprs_[SP] = &sp_;
gprs_[RA] = &ra_;
// Initialize registers with easy to spot debug values.
@@ -42,29 +38,21 @@
void Mips64Context::FillCalleeSaves(const StackVisitor& fr) {
mirror::ArtMethod* method = fr.GetMethod();
const QuickMethodFrameInfo frame_info = method->GetQuickFrameInfo();
- size_t spill_count = POPCOUNT(frame_info.CoreSpillMask());
- size_t fp_spill_count = POPCOUNT(frame_info.FpSpillMask());
- if (spill_count > 0) {
- // Lowest number spill is farthest away, walk registers and fill into context.
- int j = 1;
- for (size_t i = 0; i < kNumberOfGpuRegisters; i++) {
- if (((frame_info.CoreSpillMask() >> i) & 1) != 0) {
- gprs_[i] = fr.CalleeSaveAddress(spill_count - j, frame_info.FrameSizeInBytes());
- j++;
- }
- }
+ int spill_pos = 0;
+
+ // Core registers come first, from the highest down to the lowest.
+ for (uint32_t core_reg : HighToLowBits(frame_info.CoreSpillMask())) {
+ gprs_[core_reg] = fr.CalleeSaveAddress(spill_pos, frame_info.FrameSizeInBytes());
+ ++spill_pos;
}
- if (fp_spill_count > 0) {
- // Lowest number spill is farthest away, walk registers and fill into context.
- int j = 1;
- for (size_t i = 0; i < kNumberOfFpuRegisters; i++) {
- if (((frame_info.FpSpillMask() >> i) & 1) != 0) {
- fprs_[i] = fr.CalleeSaveAddress(spill_count + fp_spill_count - j,
- frame_info.FrameSizeInBytes());
- j++;
- }
- }
+ DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()));
+
+ // FP registers come second, from the highest down to the lowest.
+ for (uint32_t fp_reg : HighToLowBits(frame_info.FpSpillMask())) {
+ fprs_[fp_reg] = fr.CalleeSaveAddress(spill_pos, frame_info.FrameSizeInBytes());
+ ++spill_pos;
}
+ DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()) + POPCOUNT(frame_info.FpSpillMask()));
}
void Mips64Context::SetGPR(uint32_t reg, uintptr_t value) {
diff --git a/runtime/arch/mips64/quick_method_frame_info_mips64.h b/runtime/arch/mips64/quick_method_frame_info_mips64.h
index de55e81..f967be0 100644
--- a/runtime/arch/mips64/quick_method_frame_info_mips64.h
+++ b/runtime/arch/mips64/quick_method_frame_info_mips64.h
@@ -17,6 +17,7 @@
#ifndef ART_RUNTIME_ARCH_MIPS64_QUICK_METHOD_FRAME_INFO_MIPS64_H_
#define ART_RUNTIME_ARCH_MIPS64_QUICK_METHOD_FRAME_INFO_MIPS64_H_
+#include "base/bit_utils.h"
#include "quick/quick_method_frame_info.h"
#include "registers_mips64.h"
#include "runtime.h" // for Runtime::CalleeSaveType.
diff --git a/runtime/arch/x86/context_x86.cc b/runtime/arch/x86/context_x86.cc
index 52a35dd..7a5d0c5 100644
--- a/runtime/arch/x86/context_x86.cc
+++ b/runtime/arch/x86/context_x86.cc
@@ -16,10 +16,9 @@
#include "context_x86.h"
+#include "base/bit_utils.h"
#include "mirror/art_method-inl.h"
#include "quick/quick_method_frame_info.h"
-#include "utils.h"
-
namespace art {
namespace x86 {
@@ -27,12 +26,8 @@
static constexpr uintptr_t gZero = 0;
void X86Context::Reset() {
- for (size_t i = 0; i < kNumberOfCpuRegisters; i++) {
- gprs_[i] = nullptr;
- }
- for (size_t i = 0; i < kNumberOfFloatRegisters; ++i) {
- fprs_[i] = nullptr;
- }
+ std::fill_n(gprs_, arraysize(gprs_), nullptr);
+ std::fill_n(fprs_, arraysize(fprs_), nullptr);
gprs_[ESP] = &esp_;
// Initialize registers with easy to spot debug values.
esp_ = X86Context::kBadGprBase + ESP;
@@ -42,36 +37,29 @@
void X86Context::FillCalleeSaves(const StackVisitor& fr) {
mirror::ArtMethod* method = fr.GetMethod();
const QuickMethodFrameInfo frame_info = method->GetQuickFrameInfo();
- size_t spill_count = POPCOUNT(frame_info.CoreSpillMask());
- size_t fp_spill_count = POPCOUNT(frame_info.FpSpillMask());
- if (spill_count > 0) {
- // Lowest number spill is farthest away, walk registers and fill into context.
- int j = 2; // Offset j to skip return address spill.
- for (int i = 0; i < kNumberOfCpuRegisters; i++) {
- if (((frame_info.CoreSpillMask() >> i) & 1) != 0) {
- gprs_[i] = fr.CalleeSaveAddress(spill_count - j, frame_info.FrameSizeInBytes());
- j++;
- }
- }
+ int spill_pos = 0;
+
+ // Core registers come first, from the highest down to the lowest.
+ uint32_t core_regs =
+ frame_info.CoreSpillMask() & ~(static_cast<uint32_t>(-1) << kNumberOfCpuRegisters);
+ DCHECK_EQ(1, POPCOUNT(frame_info.CoreSpillMask() & ~core_regs)); // Return address spill.
+ for (uint32_t core_reg : HighToLowBits(core_regs)) {
+ gprs_[core_reg] = fr.CalleeSaveAddress(spill_pos, frame_info.FrameSizeInBytes());
+ ++spill_pos;
}
- if (fp_spill_count > 0) {
- // Lowest number spill is farthest away, walk registers and fill into context.
- size_t j = 2; // Offset j to skip return address spill.
- size_t fp_spill_size_in_words = fp_spill_count * 2;
- for (size_t i = 0; i < kNumberOfFloatRegisters; ++i) {
- if (((frame_info.FpSpillMask() >> i) & 1) != 0) {
- // There are 2 pieces to each XMM register, to match VR size.
- fprs_[2*i] = reinterpret_cast<uint32_t*>(
- fr.CalleeSaveAddress(spill_count + fp_spill_size_in_words - j,
- frame_info.FrameSizeInBytes()));
- fprs_[2*i+1] = reinterpret_cast<uint32_t*>(
- fr.CalleeSaveAddress(spill_count + fp_spill_size_in_words - j - 1,
- frame_info.FrameSizeInBytes()));
- // Two void* per XMM register.
- j += 2;
- }
- }
+ DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()) - 1);
+
+ // FP registers come second, from the highest down to the lowest.
+ uint32_t fp_regs = frame_info.FpSpillMask();
+ DCHECK_EQ(0u, fp_regs & (static_cast<uint32_t>(-1) << kNumberOfFloatRegisters));
+ for (uint32_t fp_reg : HighToLowBits(fp_regs)) {
+ // Two void* per XMM register.
+ fprs_[2 * fp_reg] = fr.CalleeSaveAddress(spill_pos + 1, frame_info.FrameSizeInBytes());
+ fprs_[2 * fp_reg + 1] = fr.CalleeSaveAddress(spill_pos, frame_info.FrameSizeInBytes());
+ spill_pos += 2;
}
+ DCHECK_EQ(spill_pos,
+ POPCOUNT(frame_info.CoreSpillMask()) - 1 + 2 * POPCOUNT(frame_info.FpSpillMask()));
}
void X86Context::SmashCallerSaves() {
diff --git a/runtime/arch/x86/quick_method_frame_info_x86.h b/runtime/arch/x86/quick_method_frame_info_x86.h
index 9bba531..ed1d860 100644
--- a/runtime/arch/x86/quick_method_frame_info_x86.h
+++ b/runtime/arch/x86/quick_method_frame_info_x86.h
@@ -17,6 +17,7 @@
#ifndef ART_RUNTIME_ARCH_X86_QUICK_METHOD_FRAME_INFO_X86_H_
#define ART_RUNTIME_ARCH_X86_QUICK_METHOD_FRAME_INFO_X86_H_
+#include "base/bit_utils.h"
#include "quick/quick_method_frame_info.h"
#include "registers_x86.h"
#include "runtime.h" // for Runtime::CalleeSaveType.
diff --git a/runtime/arch/x86_64/context_x86_64.cc b/runtime/arch/x86_64/context_x86_64.cc
index 6336541..de54e14 100644
--- a/runtime/arch/x86_64/context_x86_64.cc
+++ b/runtime/arch/x86_64/context_x86_64.cc
@@ -16,9 +16,9 @@
#include "context_x86_64.h"
+#include "base/bit_utils.h"
#include "mirror/art_method-inl.h"
#include "quick/quick_method_frame_info.h"
-#include "utils.h"
namespace art {
namespace x86_64 {
@@ -26,12 +26,8 @@
static constexpr uintptr_t gZero = 0;
void X86_64Context::Reset() {
- for (size_t i = 0; i < kNumberOfCpuRegisters; ++i) {
- gprs_[i] = nullptr;
- }
- for (size_t i = 0; i < kNumberOfFloatRegisters; ++i) {
- fprs_[i] = nullptr;
- }
+ std::fill_n(gprs_, arraysize(gprs_), nullptr);
+ std::fill_n(fprs_, arraysize(fprs_), nullptr);
gprs_[RSP] = &rsp_;
// Initialize registers with easy to spot debug values.
rsp_ = X86_64Context::kBadGprBase + RSP;
@@ -41,29 +37,27 @@
void X86_64Context::FillCalleeSaves(const StackVisitor& fr) {
mirror::ArtMethod* method = fr.GetMethod();
const QuickMethodFrameInfo frame_info = method->GetQuickFrameInfo();
- size_t spill_count = POPCOUNT(frame_info.CoreSpillMask());
- size_t fp_spill_count = POPCOUNT(frame_info.FpSpillMask());
- if (spill_count > 0) {
- // Lowest number spill is farthest away, walk registers and fill into context.
- size_t j = 2; // Offset j to skip return address spill.
- for (size_t i = 0; i < kNumberOfCpuRegisters; ++i) {
- if (((frame_info.CoreSpillMask() >> i) & 1) != 0) {
- gprs_[i] = fr.CalleeSaveAddress(spill_count - j, frame_info.FrameSizeInBytes());
- j++;
- }
- }
+ int spill_pos = 0;
+
+ // Core registers come first, from the highest down to the lowest.
+ uint32_t core_regs =
+ frame_info.CoreSpillMask() & ~(static_cast<uint32_t>(-1) << kNumberOfCpuRegisters);
+ DCHECK_EQ(1, POPCOUNT(frame_info.CoreSpillMask() & ~core_regs)); // Return address spill.
+ for (uint32_t core_reg : HighToLowBits(core_regs)) {
+ gprs_[core_reg] = fr.CalleeSaveAddress(spill_pos, frame_info.FrameSizeInBytes());
+ ++spill_pos;
}
- if (fp_spill_count > 0) {
- // Lowest number spill is farthest away, walk registers and fill into context.
- size_t j = 2; // Offset j to skip return address spill.
- for (size_t i = 0; i < kNumberOfFloatRegisters; ++i) {
- if (((frame_info.FpSpillMask() >> i) & 1) != 0) {
- fprs_[i] = reinterpret_cast<uint64_t*>(
- fr.CalleeSaveAddress(spill_count + fp_spill_count - j, frame_info.FrameSizeInBytes()));
- j++;
- }
- }
+ DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()) - 1);
+
+ // FP registers come second, from the highest down to the lowest.
+ uint32_t fp_regs = frame_info.FpSpillMask();
+ DCHECK_EQ(0u, fp_regs & (static_cast<uint32_t>(-1) << kNumberOfFloatRegisters));
+ for (uint32_t fp_reg : HighToLowBits(fp_regs)) {
+ fprs_[fp_reg] = fr.CalleeSaveAddress(spill_pos, frame_info.FrameSizeInBytes());
+ ++spill_pos;
}
+ DCHECK_EQ(spill_pos,
+ POPCOUNT(frame_info.CoreSpillMask()) - 1 + POPCOUNT(frame_info.FpSpillMask()));
}
void X86_64Context::SmashCallerSaves() {
diff --git a/runtime/arch/x86_64/quick_method_frame_info_x86_64.h b/runtime/arch/x86_64/quick_method_frame_info_x86_64.h
index 53aa212..72d7e99 100644
--- a/runtime/arch/x86_64/quick_method_frame_info_x86_64.h
+++ b/runtime/arch/x86_64/quick_method_frame_info_x86_64.h
@@ -17,6 +17,7 @@
#ifndef ART_RUNTIME_ARCH_X86_64_QUICK_METHOD_FRAME_INFO_X86_64_H_
#define ART_RUNTIME_ARCH_X86_64_QUICK_METHOD_FRAME_INFO_X86_64_H_
+#include "base/bit_utils.h"
#include "quick/quick_method_frame_info.h"
#include "registers_x86_64.h"
#include "runtime.h" // for Runtime::CalleeSaveType.