ART: Fix GenSelect for ARM64
Add CSINV and replace CSNEG in GenSelect.
Some tests were failing in 083-complier-regression as CSNEG
was used instead of CSINV. CSNEG on xzr yields 0, whereas
CSINV negates the bits and yields -1, which was the intention.
Change-Id: I60557e34483f98310f7d33f18d8db203fba6e78f
Signed-off-by: Stuart Monteith <stuart.monteith@arm.com>
diff --git a/compiler/dex/quick/arm64/int_arm64.cc b/compiler/dex/quick/arm64/int_arm64.cc
index 3ee3e2e..a7ca685 100644
--- a/compiler/dex/quick/arm64/int_arm64.cc
+++ b/compiler/dex/quick/arm64/int_arm64.cc
@@ -131,7 +131,7 @@
}
left_op = right_op = zero_reg;
- opcode = is_wide ? WIDE(kA64Csneg4rrrc) : kA64Csneg4rrrc;
+ opcode = is_wide ? WIDE(kA64Csinv4rrrc) : kA64Csinv4rrrc;
} else if (true_val == 0 || false_val == 0) {
// Csel half cheap based on wzr.
rl_result = EvalLoc(rl_dest, result_reg_class, true);
@@ -167,7 +167,7 @@
LoadConstantNoClobber(rl_result.reg, true_val == 0xFFFFFFFF ? false_val : true_val);
left_op = rl_result.reg.GetReg();
right_op = zero_reg;
- opcode = is_wide ? WIDE(kA64Csneg4rrrc) : kA64Csneg4rrrc;
+ opcode = is_wide ? WIDE(kA64Csinv4rrrc) : kA64Csinv4rrrc;
} else {
// Csel. The rest. Use rl_result and a temp.
// TODO: To minimize the constants being loaded, check whether one can be inexpensively