Implement Intel QuasiAtomics.
Don't use striped locks for 64bit atomics on x86.
Modify QuasiAtomic::Swap to be QuasiAtomic::Write that fits our current use of
Swap and is closer to Intel's implementation.
Return that MIPS doesn't support 64bit compare-and-exchanges in AtomicLong.
Set the SSE2 flag for host and target Intel ART builds as our codegen assumes
it.
Change-Id: Ic1cd5c3b06838e42c6f94e0dd91e77a2d0bb5868
diff --git a/src/jdwp/jdwp_handler.cc b/src/jdwp/jdwp_handler.cc
index bd50c61..cb13695 100644
--- a/src/jdwp/jdwp_handler.cc
+++ b/src/jdwp/jdwp_handler.cc
@@ -1842,7 +1842,7 @@
* so waitForDebugger() doesn't return if we stall for a bit here.
*/
Dbg::GoActive();
- QuasiAtomic::Swap64(0, &last_activity_time_ms_);
+ QuasiAtomic::Write64(&last_activity_time_ms_, 0);
}
/*
@@ -1912,7 +1912,7 @@
* the initial setup. Only update if this is a non-DDMS packet.
*/
if (pHeader->cmdSet != kJDWPDdmCmdSet) {
- QuasiAtomic::Swap64(MilliTime(), &last_activity_time_ms_);
+ QuasiAtomic::Write64(&last_activity_time_ms_, MilliTime());
}
/* tell the VM that GC is okay again */