Quick compiler, MIPS resource cleanup
MIPS architecture includes internal registers HI and LO.
Similar to condition codes in other architectures, these internal
resouces must be accounted for during instruction scheduling.
Previously, the Quick backend for MIPS dealt with them by defining
rHI and rLO pseudo registers - treating them as actual registers for
def/use masks. This CL changes the handling of these resources to
be in line with how condition codes are used elsewhere - leaving
register definitions to be used for registers.
Change-Id: Idcd77f3107b0c9b081ad05b1aab663fb9f41492d
diff --git a/compiler/dex/quick/mips/int_mips.cc b/compiler/dex/quick/mips/int_mips.cc
index dfe8b35..b7940bb 100644
--- a/compiler/dex/quick/mips/int_mips.cc
+++ b/compiler/dex/quick/mips/int_mips.cc
@@ -229,12 +229,12 @@
RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2,
bool is_div) {
- NewLIR4(kMipsDiv, rHI, rLO, reg1.GetReg(), reg2.GetReg());
+ NewLIR2(kMipsDiv, reg1.GetReg(), reg2.GetReg());
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
if (is_div) {
- NewLIR2(kMipsMflo, rl_result.reg.GetReg(), rLO);
+ NewLIR1(kMipsMflo, rl_result.reg.GetReg());
} else {
- NewLIR2(kMipsMfhi, rl_result.reg.GetReg(), rHI);
+ NewLIR1(kMipsMfhi, rl_result.reg.GetReg());
}
return rl_result;
}
@@ -243,12 +243,12 @@
bool is_div) {
int t_reg = AllocTemp().GetReg();
NewLIR3(kMipsAddiu, t_reg, rZERO, lit);
- NewLIR4(kMipsDiv, rHI, rLO, reg1.GetReg(), t_reg);
+ NewLIR2(kMipsDiv, reg1.GetReg(), t_reg);
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
if (is_div) {
- NewLIR2(kMipsMflo, rl_result.reg.GetReg(), rLO);
+ NewLIR1(kMipsMflo, rl_result.reg.GetReg());
} else {
- NewLIR2(kMipsMfhi, rl_result.reg.GetReg(), rHI);
+ NewLIR1(kMipsMfhi, rl_result.reg.GetReg());
}
FreeTemp(t_reg);
return rl_result;