commit 9ee801f5308aa3c62ae3bedae2658612762ffb91
author Dmitry Petrochenko <dmitry.petrochenko@intel.com> Mon May 12 11:31:37 2014 +0700
committer Dmitry Petrochenko <dmitry.petrochenko@intel.com> Wed May 14 00:40:57 2014 +0700
tree 86ed7ec36fe4a06bcc0b37df6661ac112888c0f6
parent cd6e04f738ee17b3e8ec51c1f14d636fa2a89a55

Add x86_64 code generation support

Utilizes r0..r7 in register allocator, implements spill/unsill
core regs as well as operations with stack pointer.

Change-Id: I973d5a1acb9aa735f6832df3d440185d9e896c67
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>

compiler/compilers.cc

diff --git a/compiler/compilers.cc b/compiler/compilers.cc
index 79a85db..76838d7 100644
--- a/compiler/compilers.cc
+++ b/compiler/compilers.cc
@@ -111,7 +111,7 @@
       mir_to_lir = X86CodeGenerator(cu, cu->mir_graph.get(), &cu->arena);
       break;
     case kX86_64:
-      mir_to_lir = X86CodeGenerator(cu, cu->mir_graph.get(), &cu->arena);
+      mir_to_lir = X86_64CodeGenerator(cu, cu->mir_graph.get(), &cu->arena);
       break;
     default:
       LOG(FATAL) << "Unexpected instruction set: " << cu->instruction_set;