Complete MIPS code generation support
With this CL code generation for MIPS is complete (though untested on
actual hardware). Core and the boot classpath compile without issue.
The primary thrust here was to support expanding of short branch
sequences to long form during assembly if the displacement field overflowed.
That led to a general cleanup of creation on LIR nodes outside of the
normal flow.
Also introduced is a README to describe the state of MIPS support, as well
as memory barrier handling.
Change-Id: I251a2ef8d74bc7183406dce9493464be24a9d7f7
diff --git a/src/compiler/codegen/mips/MipsLIR.h b/src/compiler/codegen/mips/MipsLIR.h
index 5034623..18f06ae 100644
--- a/src/compiler/codegen/mips/MipsLIR.h
+++ b/src/compiler/codegen/mips/MipsLIR.h
@@ -311,9 +311,17 @@
kMipsRor = 0x3
} MipsShiftEncodings;
-// FIXME: Need support for barriers. Adding these defines to allow compile
-#define kST 0
-#define kSY 1
+// MIPS sync kinds (Note: support for kinds other than kSYNC0 may not exist)
+#define kSYNC0 0x00
+#define kSYNC_WMB 0x04
+#define kSYNC_MB 0x01
+#define kSYNC_ACQUIRE 0x11
+#define kSYNC_RELEASE 0x12
+#define kSYNC_RMB 0x13
+
+// TODO: Use smaller hammer when appropriate for target CPU
+#define kST kSYNC0
+#define kSY kSYNC0
#define isPseudoOpcode(opCode) ((int)(opCode) < 0)
@@ -430,6 +438,7 @@
kMipsDeltaHi, /* Pseudo for lui t, high16(<label>-<label>) */
kMipsDeltaLo, /* Pseudo for ori t, s, low16(<label>-<label>) */
kMipsCurrPC, /* jal to .+8 to materialize pc */
+ kMipsSync, /* sync kind [000000] [0000000000000000] s[10..6] [001111] */
kMipsUndefined, /* undefined [011001xxxxxxxxxxxxxxxx] */
kMipsLast
} MipsOpCode;
@@ -463,7 +472,6 @@
kMemStore,
kPCRelFixup,
kRegUseLR,
-// FIXME: add NEEDS_FIXUP to instruction attributes
} MipsOpFeatureFlags;
#define IS_LOAD (1 << kMemLoad)