MIPS: InstructionCodeGeneratorMIPS*::DivRemByPowerOfTwo()
Replace [d]sll+[d]srl with [d]ins on R2+.
Change-Id: I7587e46c47c8ce413d81a5c6c29d91e32a14d855
diff --git a/compiler/optimizing/code_generator_mips.cc b/compiler/optimizing/code_generator_mips.cc
index 9f4c234..c4772ad 100644
--- a/compiler/optimizing/code_generator_mips.cc
+++ b/compiler/optimizing/code_generator_mips.cc
@@ -3774,8 +3774,12 @@
if (IsUint<16>(abs_imm - 1)) {
__ Andi(out, out, abs_imm - 1);
} else {
- __ Sll(out, out, 32 - ctz_imm);
- __ Srl(out, out, 32 - ctz_imm);
+ if (codegen_->GetInstructionSetFeatures().IsMipsIsaRevGreaterThanEqual2()) {
+ __ Ins(out, ZERO, ctz_imm, 32 - ctz_imm);
+ } else {
+ __ Sll(out, out, 32 - ctz_imm);
+ __ Srl(out, out, 32 - ctz_imm);
+ }
}
__ Subu(out, out, TMP);
}
diff --git a/compiler/optimizing/code_generator_mips64.cc b/compiler/optimizing/code_generator_mips64.cc
index eb64f1b..c8891ed 100644
--- a/compiler/optimizing/code_generator_mips64.cc
+++ b/compiler/optimizing/code_generator_mips64.cc
@@ -3311,12 +3311,7 @@
__ Sra(TMP, dividend, 31);
__ Srl(TMP, TMP, 32 - ctz_imm);
__ Addu(out, dividend, TMP);
- if (IsUint<16>(abs_imm - 1)) {
- __ Andi(out, out, abs_imm - 1);
- } else {
- __ Sll(out, out, 32 - ctz_imm);
- __ Srl(out, out, 32 - ctz_imm);
- }
+ __ Ins(out, ZERO, ctz_imm, 32 - ctz_imm);
__ Subu(out, out, TMP);
}
} else {
@@ -3335,17 +3330,7 @@
__ Dsrl32(TMP, TMP, 32 - ctz_imm);
}
__ Daddu(out, dividend, TMP);
- if (IsUint<16>(abs_imm - 1)) {
- __ Andi(out, out, abs_imm - 1);
- } else {
- if (ctz_imm > 32) {
- __ Dsll(out, out, 64 - ctz_imm);
- __ Dsrl(out, out, 64 - ctz_imm);
- } else {
- __ Dsll32(out, out, 32 - ctz_imm);
- __ Dsrl32(out, out, 32 - ctz_imm);
- }
- }
+ __ DblIns(out, ZERO, ctz_imm, 64 - ctz_imm);
__ Dsubu(out, out, TMP);
}
}