Compiler cleanup: remove some old JIT leftovers.
The JIT was designed to allow any code emitter (for any reason)
to decline to complete a codegen request. The outer driver
would then detect if a codegen request wasn't completed and
in that case generate bail-out code to the interpreter or
simply end the trace early.
This was quite useful for the JIT, but has no value in an
ahead-of-time compiler (with the exception of special inline
cases - those are still optional). Codegen requests must succeed or
die. This CL removes some of the bool success reporting from
inherited Gen routines.
Change-Id: I0237bbd82cc2d548f85dda8f7231126337976e8a
diff --git a/src/compiler/codegen/arm/codegen_arm.h b/src/compiler/codegen/arm/codegen_arm.h
index 4dadd6c..9342620 100644
--- a/src/compiler/codegen/arm/codegen_arm.h
+++ b/src/compiler/codegen/arm/codegen_arm.h
@@ -88,7 +88,7 @@
virtual bool IsUnconditionalBranch(LIR* lir);
// Required for target - Dalvik-level generators.
- virtual bool GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+ virtual void GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src1, RegLocation rl_src2);
virtual void GenArrayObjPut(CompilationUnit* cu, int opt_flags, RegLocation rl_array,
RegLocation rl_index, RegLocation rl_src, int scale);
@@ -96,32 +96,32 @@
RegLocation rl_index, RegLocation rl_dest, int scale);
virtual void GenArrayPut(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
RegLocation rl_index, RegLocation rl_src, int scale);
- virtual bool GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
+ virtual void GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_shift);
virtual void GenMulLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
- virtual bool GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+ virtual void GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
- virtual bool GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+ virtual void GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
- virtual bool GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
+ virtual void GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
- virtual bool GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
+ virtual void GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src1, RegLocation rl_src2);
- virtual bool GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+ virtual void GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src1, RegLocation rl_src2);
- virtual bool GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+ virtual void GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src);
virtual bool GenInlinedCas32(CompilationUnit* cu, CallInfo* info, bool need_write_barrier);
virtual bool GenInlinedMinMaxInt(CompilationUnit *cu, CallInfo* info, bool is_min);
virtual bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info);
- virtual bool GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
- virtual bool GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+ virtual void GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
+ virtual void GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
- virtual bool GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+ virtual void GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
- virtual bool GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+ virtual void GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
virtual LIR* GenRegMemCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int base,
int offset, ThrowKind kind);
diff --git a/src/compiler/codegen/arm/fp_arm.cc b/src/compiler/codegen/arm/fp_arm.cc
index 577e0ab..14d766f 100644
--- a/src/compiler/codegen/arm/fp_arm.cc
+++ b/src/compiler/codegen/arm/fp_arm.cc
@@ -21,7 +21,7 @@
namespace art {
-bool ArmCodegen::GenArithOpFloat(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+void ArmCodegen::GenArithOpFloat(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src1, RegLocation rl_src2)
{
int op = kThumbBkpt;
@@ -54,22 +54,21 @@
CallRuntimeHelperRegLocationRegLocation(cu, ENTRYPOINT_OFFSET(pFmodf), rl_src1, rl_src2, false);
rl_result = GetReturn(cu, true);
StoreValue(cu, rl_dest, rl_result);
- return false;
+ return;
case Instruction::NEG_FLOAT:
GenNegFloat(cu, rl_dest, rl_src1);
- return false;
+ return;
default:
- return true;
+ LOG(FATAL) << "Unexpected opcode: " << opcode;
}
rl_src1 = LoadValue(cu, rl_src1, kFPReg);
rl_src2 = LoadValue(cu, rl_src2, kFPReg);
rl_result = EvalLoc(cu, rl_dest, kFPReg, true);
NewLIR3(cu, op, rl_result.low_reg, rl_src1.low_reg, rl_src2.low_reg);
StoreValue(cu, rl_dest, rl_result);
- return false;
}
-bool ArmCodegen::GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
+void ArmCodegen::GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
{
int op = kThumbBkpt;
@@ -98,12 +97,12 @@
CallRuntimeHelperRegLocationRegLocation(cu, ENTRYPOINT_OFFSET(pFmod), rl_src1, rl_src2, false);
rl_result = GetReturnWide(cu, true);
StoreValueWide(cu, rl_dest, rl_result);
- return false;
+ return;
case Instruction::NEG_DOUBLE:
GenNegDouble(cu, rl_dest, rl_src1);
- return false;
+ return;
default:
- return true;
+ LOG(FATAL) << "Unexpected opcode: " << opcode;
}
rl_src1 = LoadValueWide(cu, rl_src1, kFPReg);
@@ -116,10 +115,9 @@
NewLIR3(cu, op, S2d(rl_result.low_reg, rl_result.high_reg), S2d(rl_src1.low_reg, rl_src1.high_reg),
S2d(rl_src2.low_reg, rl_src2.high_reg));
StoreValueWide(cu, rl_dest, rl_result);
- return false;
}
-bool ArmCodegen::GenConversion(CompilationUnit* cu, Instruction::Code opcode,
+void ArmCodegen::GenConversion(CompilationUnit* cu, Instruction::Code opcode,
RegLocation rl_dest, RegLocation rl_src)
{
int op = kThumbBkpt;
@@ -146,15 +144,19 @@
op = kThumb2VcvtDI;
break;
case Instruction::LONG_TO_DOUBLE:
- return GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2d), rl_dest, rl_src);
+ GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2d), rl_dest, rl_src);
+ return;
case Instruction::FLOAT_TO_LONG:
- return GenConversionCall(cu, ENTRYPOINT_OFFSET(pF2l), rl_dest, rl_src);
+ GenConversionCall(cu, ENTRYPOINT_OFFSET(pF2l), rl_dest, rl_src);
+ return;
case Instruction::LONG_TO_FLOAT:
- return GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2f), rl_dest, rl_src);
+ GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2f), rl_dest, rl_src);
+ return;
case Instruction::DOUBLE_TO_LONG:
- return GenConversionCall(cu, ENTRYPOINT_OFFSET(pD2l), rl_dest, rl_src);
+ GenConversionCall(cu, ENTRYPOINT_OFFSET(pD2l), rl_dest, rl_src);
+ return;
default:
- return true;
+ LOG(FATAL) << "Unexpected opcode: " << opcode;
}
if (rl_src.wide) {
rl_src = LoadValueWide(cu, rl_src, kFPReg);
@@ -172,7 +174,6 @@
NewLIR2(cu, op, rl_result.low_reg, src_reg);
StoreValue(cu, rl_dest, rl_result);
}
- return false;
}
void ArmCodegen::GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir, bool gt_bias,
@@ -229,11 +230,11 @@
}
-bool ArmCodegen::GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+void ArmCodegen::GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src1, RegLocation rl_src2)
{
- bool is_double;
- int default_result;
+ bool is_double = false;
+ int default_result = -1;
RegLocation rl_result;
switch (opcode) {
@@ -254,7 +255,7 @@
default_result = 1;
break;
default:
- return true;
+ LOG(FATAL) << "Unexpected opcode: " << opcode;
}
if (is_double) {
rl_src1 = LoadValueWide(cu, rl_src1, kFPReg);
@@ -287,7 +288,6 @@
GenBarrier(cu);
StoreValue(cu, rl_dest, rl_result);
- return false;
}
void ArmCodegen::GenNegFloat(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
diff --git a/src/compiler/codegen/arm/int_arm.cc b/src/compiler/codegen/arm/int_arm.cc
index 5a9786c..857ec93 100644
--- a/src/compiler/codegen/arm/int_arm.cc
+++ b/src/compiler/codegen/arm/int_arm.cc
@@ -567,7 +567,7 @@
#endif
}
-bool ArmCodegen::GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
+void ArmCodegen::GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
{
rl_src = LoadValueWide(cu, rl_src, kCoreReg);
RegLocation rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
@@ -585,7 +585,6 @@
}
FreeTemp(cu, z_reg);
StoreValueWide(cu, rl_dest, rl_result);
- return false;
}
@@ -675,39 +674,34 @@
UnmarkTemp(cu, rARM_LR);
}
-bool ArmCodegen::GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void ArmCodegen::GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2)
{
LOG(FATAL) << "Unexpected use of GenAddLong for Arm";
- return false;
}
-bool ArmCodegen::GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void ArmCodegen::GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2)
{
LOG(FATAL) << "Unexpected use of GenSubLong for Arm";
- return false;
}
-bool ArmCodegen::GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void ArmCodegen::GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2)
{
LOG(FATAL) << "Unexpected use of GenAndLong for Arm";
- return false;
}
-bool ArmCodegen::GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void ArmCodegen::GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2)
{
LOG(FATAL) << "Unexpected use of GenOrLong for Arm";
- return false;
}
-bool ArmCodegen::GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void ArmCodegen::GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2)
{
LOG(FATAL) << "Unexpected use of genXoLong for Arm";
- return false;
}
/*
@@ -949,7 +943,7 @@
MarkGCCard(cu, r_value, r_array);
}
-bool ArmCodegen::GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
+void ArmCodegen::GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
RegLocation rl_dest, RegLocation rl_src, RegLocation rl_shift)
{
rl_src = LoadValueWide(cu, rl_src, kCoreReg);
@@ -957,10 +951,11 @@
int shift_amount = ConstantValue(cu, rl_shift) & 0x3f;
if (shift_amount == 0) {
StoreValueWide(cu, rl_dest, rl_src);
- return false; // TODO: remove useless bool return result.
+ return;
}
if (BadOverlap(cu, rl_src, rl_dest)) {
- return GenShiftOpLong(cu, opcode, rl_dest, rl_src, rl_shift);
+ GenShiftOpLong(cu, opcode, rl_dest, rl_src, rl_shift);
+ return;
}
RegLocation rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
switch(opcode) {
@@ -1018,19 +1013,18 @@
break;
default:
LOG(FATAL) << "Unexpected case";
- return true;
}
StoreValueWide(cu, rl_dest, rl_result);
- return false;
}
-bool ArmCodegen::GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
+void ArmCodegen::GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
{
if ((opcode == Instruction::SUB_LONG_2ADDR) || (opcode == Instruction::SUB_LONG)) {
if (!rl_src2.is_const) {
// Don't bother with special handling for subtract from immediate.
- return GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+ GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+ return;
}
} else {
// Normalize
@@ -1042,7 +1036,8 @@
}
}
if (BadOverlap(cu, rl_src1, rl_dest)) {
- return GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+ GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+ return;
}
DCHECK(rl_src2.is_const);
int64_t val = ConstantValueWide(cu, rl_src2);
@@ -1058,7 +1053,8 @@
case Instruction::SUB_LONG:
case Instruction::SUB_LONG_2ADDR:
if ((mod_imm_lo < 0) || (mod_imm_hi < 0)) {
- return GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+ GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+ return;
}
break;
default:
@@ -1105,7 +1101,6 @@
LOG(FATAL) << "Unexpected opcode " << opcode;
}
StoreValueWide(cu, rl_dest, rl_result);
- return false; // TODO: remove bool return value from all of these Gen routines.
}
} // namespace art