Compiler cleanup: remove some old JIT leftovers.
The JIT was designed to allow any code emitter (for any reason)
to decline to complete a codegen request. The outer driver
would then detect if a codegen request wasn't completed and
in that case generate bail-out code to the interpreter or
simply end the trace early.
This was quite useful for the JIT, but has no value in an
ahead-of-time compiler (with the exception of special inline
cases - those are still optional). Codegen requests must succeed or
die. This CL removes some of the bool success reporting from
inherited Gen routines.
Change-Id: I0237bbd82cc2d548f85dda8f7231126337976e8a
diff --git a/src/compiler/codegen/mips/codegen_mips.h b/src/compiler/codegen/mips/codegen_mips.h
index a4d44d5..eec7b08 100644
--- a/src/compiler/codegen/mips/codegen_mips.h
+++ b/src/compiler/codegen/mips/codegen_mips.h
@@ -89,7 +89,7 @@
virtual bool IsUnconditionalBranch(LIR* lir);
// Required for target - Dalvik-level generators.
- virtual bool GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+ virtual void GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src1, RegLocation rl_src2);
virtual void GenArrayObjPut(CompilationUnit* cu, int opt_flags, RegLocation rl_array,
RegLocation rl_index, RegLocation rl_src, int scale);
@@ -97,32 +97,32 @@
RegLocation rl_index, RegLocation rl_dest, int scale);
virtual void GenArrayPut(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
RegLocation rl_index, RegLocation rl_src, int scale);
- virtual bool GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
+ virtual void GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_shift);
virtual void GenMulLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
- virtual bool GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+ virtual void GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
- virtual bool GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+ virtual void GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
- virtual bool GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
+ virtual void GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
- virtual bool GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
+ virtual void GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src1, RegLocation rl_src2);
- virtual bool GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+ virtual void GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src1, RegLocation rl_src2);
- virtual bool GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+ virtual void GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src);
virtual bool GenInlinedCas32(CompilationUnit* cu, CallInfo* info, bool need_write_barrier);
virtual bool GenInlinedMinMaxInt(CompilationUnit *cu, CallInfo* info, bool is_min);
virtual bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info);
- virtual bool GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
- virtual bool GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+ virtual void GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
+ virtual void GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
- virtual bool GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+ virtual void GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
- virtual bool GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+ virtual void GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2);
virtual LIR* GenRegMemCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int base,
int offset, ThrowKind kind);
diff --git a/src/compiler/codegen/mips/fp_mips.cc b/src/compiler/codegen/mips/fp_mips.cc
index e7b106e..0c4653d 100644
--- a/src/compiler/codegen/mips/fp_mips.cc
+++ b/src/compiler/codegen/mips/fp_mips.cc
@@ -22,7 +22,7 @@
namespace art {
-bool MipsCodegen::GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode,
+void MipsCodegen::GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode,
RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
{
int op = kMipsNop;
@@ -55,23 +55,21 @@
CallRuntimeHelperRegLocationRegLocation(cu, ENTRYPOINT_OFFSET(pFmodf), rl_src1, rl_src2, false);
rl_result = GetReturn(cu, true);
StoreValue(cu, rl_dest, rl_result);
- return false;
+ return;
case Instruction::NEG_FLOAT:
GenNegFloat(cu, rl_dest, rl_src1);
- return false;
+ return;
default:
- return true;
+ LOG(FATAL) << "Unexpected opcode: " << opcode;
}
rl_src1 = LoadValue(cu, rl_src1, kFPReg);
rl_src2 = LoadValue(cu, rl_src2, kFPReg);
rl_result = EvalLoc(cu, rl_dest, kFPReg, true);
NewLIR3(cu, op, rl_result.low_reg, rl_src1.low_reg, rl_src2.low_reg);
StoreValue(cu, rl_dest, rl_result);
-
- return false;
}
-bool MipsCodegen::GenArithOpDouble(CompilationUnit *cu, Instruction::Code opcode,
+void MipsCodegen::GenArithOpDouble(CompilationUnit *cu, Instruction::Code opcode,
RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
{
int op = kMipsNop;
@@ -100,12 +98,12 @@
CallRuntimeHelperRegLocationRegLocation(cu, ENTRYPOINT_OFFSET(pFmod), rl_src1, rl_src2, false);
rl_result = GetReturnWide(cu, true);
StoreValueWide(cu, rl_dest, rl_result);
- return false;
+ return;
case Instruction::NEG_DOUBLE:
GenNegDouble(cu, rl_dest, rl_src1);
- return false;
+ return;
default:
- return true;
+ LOG(FATAL) << "Unpexpected opcode: " << opcode;
}
rl_src1 = LoadValueWide(cu, rl_src1, kFPReg);
DCHECK(rl_src1.wide);
@@ -117,10 +115,9 @@
NewLIR3(cu, op, S2d(rl_result.low_reg, rl_result.high_reg), S2d(rl_src1.low_reg, rl_src1.high_reg),
S2d(rl_src2.low_reg, rl_src2.high_reg));
StoreValueWide(cu, rl_dest, rl_result);
- return false;
}
-bool MipsCodegen::GenConversion(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
+void MipsCodegen::GenConversion(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src)
{
int op = kMipsNop;
@@ -140,19 +137,25 @@
op = kMipsFcvtdw;
break;
case Instruction::FLOAT_TO_INT:
- return GenConversionCall(cu, ENTRYPOINT_OFFSET(pF2iz), rl_dest, rl_src);
+ GenConversionCall(cu, ENTRYPOINT_OFFSET(pF2iz), rl_dest, rl_src);
+ return;
case Instruction::DOUBLE_TO_INT:
- return GenConversionCall(cu, ENTRYPOINT_OFFSET(pD2iz), rl_dest, rl_src);
+ GenConversionCall(cu, ENTRYPOINT_OFFSET(pD2iz), rl_dest, rl_src);
+ return;
case Instruction::LONG_TO_DOUBLE:
- return GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2d), rl_dest, rl_src);
+ GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2d), rl_dest, rl_src);
+ return;
case Instruction::FLOAT_TO_LONG:
- return GenConversionCall(cu, ENTRYPOINT_OFFSET(pF2l), rl_dest, rl_src);
+ GenConversionCall(cu, ENTRYPOINT_OFFSET(pF2l), rl_dest, rl_src);
+ return;
case Instruction::LONG_TO_FLOAT:
- return GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2f), rl_dest, rl_src);
+ GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2f), rl_dest, rl_src);
+ return;
case Instruction::DOUBLE_TO_LONG:
- return GenConversionCall(cu, ENTRYPOINT_OFFSET(pD2l), rl_dest, rl_src);
+ GenConversionCall(cu, ENTRYPOINT_OFFSET(pD2l), rl_dest, rl_src);
+ return;
default:
- return true;
+ LOG(FATAL) << "Unexpected opcode: " << opcode;
}
if (rl_src.wide) {
rl_src = LoadValueWide(cu, rl_src, kFPReg);
@@ -170,14 +173,13 @@
NewLIR2(cu, op, rl_result.low_reg, src_reg);
StoreValue(cu, rl_dest, rl_result);
}
- return false;
}
-bool MipsCodegen::GenCmpFP(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
+void MipsCodegen::GenCmpFP(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src1, RegLocation rl_src2)
{
bool wide = true;
- int offset;
+ int offset = -1; // Make gcc happy.
switch (opcode) {
case Instruction::CMPL_FLOAT:
@@ -195,7 +197,7 @@
offset = ENTRYPOINT_OFFSET(pCmpgDouble);
break;
default:
- return true;
+ LOG(FATAL) << "Unexpected opcode: " << opcode;
}
FlushAllRegs(cu);
LockCallTemps(cu);
@@ -211,7 +213,6 @@
OpReg(cu, kOpBlx, r_tgt);
RegLocation rl_result = GetReturn(cu, false);
StoreValue(cu, rl_dest, rl_result);
- return false;
}
void MipsCodegen::GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir,
diff --git a/src/compiler/codegen/mips/int_mips.cc b/src/compiler/codegen/mips/int_mips.cc
index 675cf8d..31c13f2 100644
--- a/src/compiler/codegen/mips/int_mips.cc
+++ b/src/compiler/codegen/mips/int_mips.cc
@@ -345,10 +345,9 @@
RegLocation rl_src2)
{
LOG(FATAL) << "Unexpected use of GenMulLong for Mips";
- return;
}
-bool MipsCodegen::GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void MipsCodegen::GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2)
{
rl_src1 = LoadValueWide(cu, rl_src1, kCoreReg);
@@ -369,10 +368,9 @@
OpRegRegReg(cu, kOpAdd, rl_result.high_reg, rl_result.high_reg, t_reg);
FreeTemp(cu, t_reg);
StoreValueWide(cu, rl_dest, rl_result);
- return false;
}
-bool MipsCodegen::GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void MipsCodegen::GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2)
{
rl_src1 = LoadValueWide(cu, rl_src1, kCoreReg);
@@ -393,10 +391,9 @@
OpRegRegReg(cu, kOpSub, rl_result.high_reg, rl_result.high_reg, t_reg);
FreeTemp(cu, t_reg);
StoreValueWide(cu, rl_dest, rl_result);
- return false;
}
-bool MipsCodegen::GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
+void MipsCodegen::GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
{
rl_src = LoadValueWide(cu, rl_src, kCoreReg);
RegLocation rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
@@ -415,28 +412,24 @@
OpRegRegReg(cu, kOpSub, rl_result.high_reg, rl_result.high_reg, t_reg);
FreeTemp(cu, t_reg);
StoreValueWide(cu, rl_dest, rl_result);
- return false;
}
-bool MipsCodegen::GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void MipsCodegen::GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2)
{
LOG(FATAL) << "Unexpected use of GenAndLong for Mips";
- return false;
}
-bool MipsCodegen::GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void MipsCodegen::GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2)
{
LOG(FATAL) << "Unexpected use of GenOrLong for Mips";
- return false;
}
-bool MipsCodegen::GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void MipsCodegen::GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
RegLocation rl_src2)
{
LOG(FATAL) << "Unexpected use of GenXorLong for Mips";
- return false;
}
/*
@@ -642,18 +635,18 @@
MarkGCCard(cu, r_value, r_array);
}
-bool MipsCodegen::GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+void MipsCodegen::GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src1, RegLocation rl_shift)
{
// Default implementation is just to ignore the constant case.
- return GenShiftOpLong(cu, opcode, rl_dest, rl_src1, rl_shift);
+ GenShiftOpLong(cu, opcode, rl_dest, rl_src1, rl_shift);
}
-bool MipsCodegen::GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
+void MipsCodegen::GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
{
// Default - bail to non-const handler.
- return GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+ GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
}
} // namespace art