diff --git a/src/compiler/codegen/arm/codegen_arm.h b/src/compiler/codegen/arm/codegen_arm.h
index 4dadd6c..9342620 100644
--- a/src/compiler/codegen/arm/codegen_arm.h
+++ b/src/compiler/codegen/arm/codegen_arm.h
@@ -88,7 +88,7 @@
     virtual bool IsUnconditionalBranch(LIR* lir);
 
     // Required for target - Dalvik-level generators.
-    virtual bool GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                                    RegLocation rl_src1, RegLocation rl_src2);
     virtual void GenArrayObjPut(CompilationUnit* cu, int opt_flags, RegLocation rl_array,
                                 RegLocation rl_index, RegLocation rl_src, int scale);
@@ -96,32 +96,32 @@
                              RegLocation rl_index, RegLocation rl_dest, int scale);
     virtual void GenArrayPut(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
                              RegLocation rl_index, RegLocation rl_src, int scale);
-    virtual bool GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
+    virtual void GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
                                    RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_shift);
     virtual void GenMulLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
-    virtual bool GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
-    virtual bool GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
-    virtual bool GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
+    virtual void GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
                                   RegLocation rl_dest, RegLocation rl_src1,
                                   RegLocation rl_src2);
-    virtual bool GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
                                  RegLocation rl_src1, RegLocation rl_src2);
-    virtual bool GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                           RegLocation rl_src1, RegLocation rl_src2);
-    virtual bool GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                                RegLocation rl_src);
     virtual bool GenInlinedCas32(CompilationUnit* cu, CallInfo* info, bool need_write_barrier);
     virtual bool GenInlinedMinMaxInt(CompilationUnit *cu, CallInfo* info, bool is_min);
     virtual bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info);
-    virtual bool GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
-    virtual bool GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
+    virtual void GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                            RegLocation rl_src2);
-    virtual bool GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
-    virtual bool GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
     virtual LIR* GenRegMemCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int base,
                                 int offset, ThrowKind kind);
diff --git a/src/compiler/codegen/arm/fp_arm.cc b/src/compiler/codegen/arm/fp_arm.cc
index 577e0ab..14d766f 100644
--- a/src/compiler/codegen/arm/fp_arm.cc
+++ b/src/compiler/codegen/arm/fp_arm.cc
@@ -21,7 +21,7 @@
 
 namespace art {
 
-bool ArmCodegen::GenArithOpFloat(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+void ArmCodegen::GenArithOpFloat(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                                  RegLocation rl_src1, RegLocation rl_src2)
 {
   int op = kThumbBkpt;
@@ -54,22 +54,21 @@
       CallRuntimeHelperRegLocationRegLocation(cu, ENTRYPOINT_OFFSET(pFmodf), rl_src1, rl_src2, false);
       rl_result = GetReturn(cu, true);
       StoreValue(cu, rl_dest, rl_result);
-      return false;
+      return;
     case Instruction::NEG_FLOAT:
       GenNegFloat(cu, rl_dest, rl_src1);
-      return false;
+      return;
     default:
-      return true;
+      LOG(FATAL) << "Unexpected opcode: " << opcode;
   }
   rl_src1 = LoadValue(cu, rl_src1, kFPReg);
   rl_src2 = LoadValue(cu, rl_src2, kFPReg);
   rl_result = EvalLoc(cu, rl_dest, kFPReg, true);
   NewLIR3(cu, op, rl_result.low_reg, rl_src1.low_reg, rl_src2.low_reg);
   StoreValue(cu, rl_dest, rl_result);
-  return false;
 }
 
-bool ArmCodegen::GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
+void ArmCodegen::GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
                                   RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
 {
   int op = kThumbBkpt;
@@ -98,12 +97,12 @@
       CallRuntimeHelperRegLocationRegLocation(cu, ENTRYPOINT_OFFSET(pFmod), rl_src1, rl_src2, false);
       rl_result = GetReturnWide(cu, true);
       StoreValueWide(cu, rl_dest, rl_result);
-      return false;
+      return;
     case Instruction::NEG_DOUBLE:
       GenNegDouble(cu, rl_dest, rl_src1);
-      return false;
+      return;
     default:
-      return true;
+      LOG(FATAL) << "Unexpected opcode: " << opcode;
   }
 
   rl_src1 = LoadValueWide(cu, rl_src1, kFPReg);
@@ -116,10 +115,9 @@
   NewLIR3(cu, op, S2d(rl_result.low_reg, rl_result.high_reg), S2d(rl_src1.low_reg, rl_src1.high_reg),
           S2d(rl_src2.low_reg, rl_src2.high_reg));
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
-bool ArmCodegen::GenConversion(CompilationUnit* cu, Instruction::Code opcode,
+void ArmCodegen::GenConversion(CompilationUnit* cu, Instruction::Code opcode,
                                RegLocation rl_dest, RegLocation rl_src)
 {
   int op = kThumbBkpt;
@@ -146,15 +144,19 @@
       op = kThumb2VcvtDI;
       break;
     case Instruction::LONG_TO_DOUBLE:
-      return GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2d), rl_dest, rl_src);
+      GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2d), rl_dest, rl_src);
+      return;
     case Instruction::FLOAT_TO_LONG:
-      return GenConversionCall(cu, ENTRYPOINT_OFFSET(pF2l), rl_dest, rl_src);
+      GenConversionCall(cu, ENTRYPOINT_OFFSET(pF2l), rl_dest, rl_src);
+      return;
     case Instruction::LONG_TO_FLOAT:
-      return GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2f), rl_dest, rl_src);
+      GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2f), rl_dest, rl_src);
+      return;
     case Instruction::DOUBLE_TO_LONG:
-      return GenConversionCall(cu, ENTRYPOINT_OFFSET(pD2l), rl_dest, rl_src);
+      GenConversionCall(cu, ENTRYPOINT_OFFSET(pD2l), rl_dest, rl_src);
+      return;
     default:
-      return true;
+      LOG(FATAL) << "Unexpected opcode: " << opcode;
   }
   if (rl_src.wide) {
     rl_src = LoadValueWide(cu, rl_src, kFPReg);
@@ -172,7 +174,6 @@
     NewLIR2(cu, op, rl_result.low_reg, src_reg);
     StoreValue(cu, rl_dest, rl_result);
   }
-  return false;
 }
 
 void ArmCodegen::GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir, bool gt_bias,
@@ -229,11 +230,11 @@
 }
 
 
-bool ArmCodegen::GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+void ArmCodegen::GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                           RegLocation rl_src1, RegLocation rl_src2)
 {
-  bool is_double;
-  int default_result;
+  bool is_double = false;
+  int default_result = -1;
   RegLocation rl_result;
 
   switch (opcode) {
@@ -254,7 +255,7 @@
       default_result = 1;
       break;
     default:
-      return true;
+      LOG(FATAL) << "Unexpected opcode: " << opcode;
   }
   if (is_double) {
     rl_src1 = LoadValueWide(cu, rl_src1, kFPReg);
@@ -287,7 +288,6 @@
   GenBarrier(cu);
 
   StoreValue(cu, rl_dest, rl_result);
-  return false;
 }
 
 void ArmCodegen::GenNegFloat(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
diff --git a/src/compiler/codegen/arm/int_arm.cc b/src/compiler/codegen/arm/int_arm.cc
index 5a9786c..857ec93 100644
--- a/src/compiler/codegen/arm/int_arm.cc
+++ b/src/compiler/codegen/arm/int_arm.cc
@@ -567,7 +567,7 @@
 #endif
 }
 
-bool ArmCodegen::GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
+void ArmCodegen::GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
 {
   rl_src = LoadValueWide(cu, rl_src, kCoreReg);
   RegLocation rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
@@ -585,7 +585,6 @@
   }
   FreeTemp(cu, z_reg);
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
 
@@ -675,39 +674,34 @@
     UnmarkTemp(cu, rARM_LR);
 }
 
-bool ArmCodegen::GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void ArmCodegen::GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2)
 {
   LOG(FATAL) << "Unexpected use of GenAddLong for Arm";
-  return false;
 }
 
-bool ArmCodegen::GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void ArmCodegen::GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2)
 {
   LOG(FATAL) << "Unexpected use of GenSubLong for Arm";
-  return false;
 }
 
-bool ArmCodegen::GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void ArmCodegen::GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2)
 {
   LOG(FATAL) << "Unexpected use of GenAndLong for Arm";
-  return false;
 }
 
-bool ArmCodegen::GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void ArmCodegen::GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                            RegLocation rl_src2)
 {
   LOG(FATAL) << "Unexpected use of GenOrLong for Arm";
-  return false;
 }
 
-bool ArmCodegen::GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void ArmCodegen::GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2)
 {
   LOG(FATAL) << "Unexpected use of genXoLong for Arm";
-  return false;
 }
 
 /*
@@ -949,7 +943,7 @@
   MarkGCCard(cu, r_value, r_array);
 }
 
-bool ArmCodegen::GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
+void ArmCodegen::GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
                                    RegLocation rl_dest, RegLocation rl_src, RegLocation rl_shift)
 {
   rl_src = LoadValueWide(cu, rl_src, kCoreReg);
@@ -957,10 +951,11 @@
   int shift_amount = ConstantValue(cu, rl_shift) & 0x3f;
   if (shift_amount == 0) {
     StoreValueWide(cu, rl_dest, rl_src);
-    return false; // TODO: remove useless bool return result.
+    return;
   }
   if (BadOverlap(cu, rl_src, rl_dest)) {
-    return GenShiftOpLong(cu, opcode, rl_dest, rl_src, rl_shift);
+    GenShiftOpLong(cu, opcode, rl_dest, rl_src, rl_shift);
+    return;
   }
   RegLocation rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
   switch(opcode) {
@@ -1018,19 +1013,18 @@
       break;
     default:
       LOG(FATAL) << "Unexpected case";
-      return true;
   }
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
-bool ArmCodegen::GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
+void ArmCodegen::GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
                                    RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
 {
   if ((opcode == Instruction::SUB_LONG_2ADDR) || (opcode == Instruction::SUB_LONG)) {
     if (!rl_src2.is_const) {
       // Don't bother with special handling for subtract from immediate.
-      return GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+      GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+      return;
     }
   } else {
     // Normalize
@@ -1042,7 +1036,8 @@
     }
   }
   if (BadOverlap(cu, rl_src1, rl_dest)) {
-    return GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+    GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+    return;
   }
   DCHECK(rl_src2.is_const);
   int64_t val = ConstantValueWide(cu, rl_src2);
@@ -1058,7 +1053,8 @@
     case Instruction::SUB_LONG:
     case Instruction::SUB_LONG_2ADDR:
       if ((mod_imm_lo < 0) || (mod_imm_hi < 0)) {
-        return GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+        GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+        return;
       }
       break;
     default:
@@ -1105,7 +1101,6 @@
       LOG(FATAL) << "Unexpected opcode " << opcode;
   }
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;  // TODO: remove bool return value from all of these Gen routines.
 }
 
 }  // namespace art
diff --git a/src/compiler/codegen/codegen.h b/src/compiler/codegen/codegen.h
index 901e5da..089c61c 100644
--- a/src/compiler/codegen/codegen.h
+++ b/src/compiler/codegen/codegen.h
@@ -136,15 +136,15 @@
     void GenCheckCast(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_src);
     void GenLong3Addr(CompilationUnit* cu, OpKind first_op, OpKind second_op, RegLocation rl_dest,
                       RegLocation rl_src1, RegLocation rl_src2);
-    bool GenShiftOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    void GenShiftOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                         RegLocation rl_src1, RegLocation rl_shift);
-    bool GenArithOpInt(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    void GenArithOpInt(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                        RegLocation rl_src1, RegLocation rl_src2);
-    bool GenArithOpIntLit(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    void GenArithOpIntLit(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                           RegLocation rl_src, int lit);
-    bool GenArithOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    void GenArithOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                         RegLocation rl_src1, RegLocation rl_src2);
-    bool GenConversionCall(CompilationUnit* cu, int func_offset, RegLocation rl_dest,
+    void GenConversionCall(CompilationUnit* cu, int func_offset, RegLocation rl_dest,
                            RegLocation rl_src);
     void GenSuspendTest(CompilationUnit* cu, int opt_flags);
     void GenSuspendTestAndBranch(CompilationUnit* cu, int opt_flags, LIR* target);
@@ -288,32 +288,32 @@
     virtual bool IsUnconditionalBranch(LIR* lir) = 0;
 
     // Required for target - Dalvik-level generators.
-    virtual bool GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                                    RegLocation rl_src1, RegLocation rl_src2) = 0;
     virtual void GenMulLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2) = 0;
-    virtual bool GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2) = 0;
-    virtual bool GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2) = 0;
-    virtual bool GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
+    virtual void GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
                                   RegLocation rl_dest, RegLocation rl_src1,
                                   RegLocation rl_src2) = 0;
-    virtual bool GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
                                  RegLocation rl_src1, RegLocation rl_src2) = 0;
-    virtual bool GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                           RegLocation rl_src1, RegLocation rl_src2) = 0;
-    virtual bool GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                                RegLocation rl_src) = 0;
     virtual bool GenInlinedCas32(CompilationUnit* cu, CallInfo* info, bool need_write_barrier) = 0;
     virtual bool GenInlinedMinMaxInt(CompilationUnit *cu, CallInfo* info, bool is_min) = 0;
     virtual bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info) = 0;
-    virtual bool GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src) = 0;
-    virtual bool GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src) = 0;
+    virtual void GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                            RegLocation rl_src2) = 0;
-    virtual bool GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2) = 0;
-    virtual bool GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2) = 0;
     virtual LIR* GenRegMemCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int base,
                                 int offset, ThrowKind kind) = 0;
@@ -353,7 +353,7 @@
                              RegLocation rl_index, RegLocation rl_dest, int scale) = 0;
     virtual void GenArrayPut(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
                      RegLocation rl_index, RegLocation rl_src, int scale) = 0;
-    virtual bool GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
+    virtual void GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
                                    RegLocation rl_dest, RegLocation rl_src1,
                                    RegLocation rl_shift) = 0;
 
diff --git a/src/compiler/codegen/gen_common.cc b/src/compiler/codegen/gen_common.cc
index a4c8d0c..1ed6f9d 100644
--- a/src/compiler/codegen/gen_common.cc
+++ b/src/compiler/codegen/gen_common.cc
@@ -1119,10 +1119,10 @@
 }
 
 
-bool Codegen::GenShiftOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+void Codegen::GenShiftOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                              RegLocation rl_src1, RegLocation rl_shift)
 {
-  int func_offset;
+  int func_offset = -1; // Make gcc happy
 
   switch (opcode) {
     case Instruction::SHL_LONG:
@@ -1139,17 +1139,15 @@
       break;
     default:
       LOG(FATAL) << "Unexpected case";
-      return true;
   }
   FlushAllRegs(cu);   /* Send everything to home location */
   CallRuntimeHelperRegLocationRegLocation(cu, func_offset, rl_src1, rl_shift, false);
   RegLocation rl_result = GetReturnWide(cu, false);
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
 
-bool Codegen::GenArithOpInt(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+void Codegen::GenArithOpInt(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                             RegLocation rl_src1, RegLocation rl_src2)
 {
   OpKind op = kOpBkpt;
@@ -1277,7 +1275,6 @@
     }
     StoreValue(cu, rl_dest, rl_result);
   }
-  return false;
 }
 
 /*
@@ -1411,7 +1408,7 @@
   return true;
 }
 
-bool Codegen::GenArithOpIntLit(CompilationUnit* cu, Instruction::Code opcode,
+void Codegen::GenArithOpIntLit(CompilationUnit* cu, Instruction::Code opcode,
                                RegLocation rl_dest, RegLocation rl_src, int lit)
 {
   RegLocation rl_result;
@@ -1430,8 +1427,7 @@
       rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
       OpRegRegReg(cu, kOpSub, rl_result.low_reg, t_reg, rl_src.low_reg);
       StoreValue(cu, rl_dest, rl_result);
-      return false;
-      break;
+      return;
     }
 
     case Instruction::SUB_INT:
@@ -1449,7 +1445,7 @@
     case Instruction::MUL_INT_LIT8:
     case Instruction::MUL_INT_LIT16: {
       if (HandleEasyMultiply(cu, rl_src, rl_dest, lit)) {
-        return false;
+        return;
       }
       op = kOpMul;
       break;
@@ -1504,10 +1500,10 @@
     case Instruction::REM_INT_LIT16: {
       if (lit == 0) {
         GenImmedCheck(cu, kCondAl, 0, 0, kThrowDivZero);
-        return false;
+        return;
       }
       if (HandleEasyDivide(cu, opcode, rl_src, rl_dest, lit)) {
-        return false;
+        return;
       }
       if ((opcode == Instruction::DIV_INT_LIT8) ||
           (opcode == Instruction::DIV_INT) ||
@@ -1532,8 +1528,7 @@
           rl_result = GetReturnAlt(cu);
       }
       StoreValue(cu, rl_dest, rl_result);
-      return false;
-      break;
+      return;
     }
     default:
       LOG(FATAL) << "Unexpected opcode " << opcode;
@@ -1547,10 +1542,9 @@
     OpRegRegImm(cu, op, rl_result.low_reg, rl_src.low_reg, lit);
   }
   StoreValue(cu, rl_dest, rl_result);
-  return false;
 }
 
-bool Codegen::GenArithOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+void Codegen::GenArithOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                              RegLocation rl_src1, RegLocation rl_src2)
 {
   RegLocation rl_result;
@@ -1577,12 +1571,12 @@
         OpRegReg(cu, kOpMvn, rl_result.high_reg, rl_src2.high_reg);
       }
       StoreValueWide(cu, rl_dest, rl_result);
-      return false;
-      break;
+      return;
     case Instruction::ADD_LONG:
     case Instruction::ADD_LONG_2ADDR:
       if (cu->instruction_set != kThumb2) {
-        return GenAddLong(cu, rl_dest, rl_src1, rl_src2);
+        GenAddLong(cu, rl_dest, rl_src1, rl_src2);
+        return;
       }
       first_op = kOpAdd;
       second_op = kOpAdc;
@@ -1590,7 +1584,8 @@
     case Instruction::SUB_LONG:
     case Instruction::SUB_LONG_2ADDR:
       if (cu->instruction_set != kThumb2) {
-        return GenSubLong(cu, rl_dest, rl_src1, rl_src2);
+        GenSubLong(cu, rl_dest, rl_src1, rl_src2);
+        return;
       }
       first_op = kOpSub;
       second_op = kOpSbc;
@@ -1599,7 +1594,7 @@
     case Instruction::MUL_LONG_2ADDR:
       if (cu->instruction_set == kThumb2) {
         GenMulLong(cu, rl_dest, rl_src1, rl_src2);
-        return false;
+        return;
       } else {
         call_out = true;
         ret_reg = TargetReg(kRet0);
@@ -1632,7 +1627,8 @@
     case Instruction::OR_LONG:
     case Instruction::OR_LONG_2ADDR:
       if (cu->instruction_set == kX86) {
-        return GenOrLong(cu, rl_dest, rl_src1, rl_src2);
+        GenOrLong(cu, rl_dest, rl_src1, rl_src2);
+        return;
       }
       first_op = kOpOr;
       second_op = kOpOr;
@@ -1640,13 +1636,15 @@
     case Instruction::XOR_LONG:
     case Instruction::XOR_LONG_2ADDR:
       if (cu->instruction_set == kX86) {
-        return GenXorLong(cu, rl_dest, rl_src1, rl_src2);
+        GenXorLong(cu, rl_dest, rl_src1, rl_src2);
+        return;
       }
       first_op = kOpXor;
       second_op = kOpXor;
       break;
     case Instruction::NEG_LONG: {
-      return GenNegLong(cu, rl_dest, rl_src2);
+      GenNegLong(cu, rl_dest, rl_src2);
+      return;
     }
     default:
       LOG(FATAL) << "Invalid long arith op";
@@ -1673,10 +1671,9 @@
       rl_result = GetReturnWideAlt(cu);
     StoreValueWide(cu, rl_dest, rl_result);
   }
-  return false;
 }
 
-bool Codegen::GenConversionCall(CompilationUnit* cu, int func_offset,
+void Codegen::GenConversionCall(CompilationUnit* cu, int func_offset,
                                 RegLocation rl_dest, RegLocation rl_src)
 {
   /*
@@ -1700,7 +1697,6 @@
     rl_result = GetReturn(cu, rl_dest.fp);
     StoreValue(cu, rl_dest, rl_result);
   }
-  return false;
 }
 
 /* Check if we need to check for pending suspend request */
diff --git a/src/compiler/codegen/mips/codegen_mips.h b/src/compiler/codegen/mips/codegen_mips.h
index a4d44d5..eec7b08 100644
--- a/src/compiler/codegen/mips/codegen_mips.h
+++ b/src/compiler/codegen/mips/codegen_mips.h
@@ -89,7 +89,7 @@
     virtual bool IsUnconditionalBranch(LIR* lir);
 
     // Required for target - Dalvik-level generators.
-    virtual bool GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                                    RegLocation rl_src1, RegLocation rl_src2);
     virtual void GenArrayObjPut(CompilationUnit* cu, int opt_flags, RegLocation rl_array,
                                 RegLocation rl_index, RegLocation rl_src, int scale);
@@ -97,32 +97,32 @@
                              RegLocation rl_index, RegLocation rl_dest, int scale);
     virtual void GenArrayPut(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
                              RegLocation rl_index, RegLocation rl_src, int scale);
-    virtual bool GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
+    virtual void GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
                                    RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_shift);
     virtual void GenMulLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
-    virtual bool GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
-    virtual bool GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
-    virtual bool GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
+    virtual void GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
                                   RegLocation rl_dest, RegLocation rl_src1,
                                   RegLocation rl_src2);
-    virtual bool GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
                                  RegLocation rl_src1, RegLocation rl_src2);
-    virtual bool GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                           RegLocation rl_src1, RegLocation rl_src2);
-    virtual bool GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                                RegLocation rl_src);
     virtual bool GenInlinedCas32(CompilationUnit* cu, CallInfo* info, bool need_write_barrier);
     virtual bool GenInlinedMinMaxInt(CompilationUnit *cu, CallInfo* info, bool is_min);
     virtual bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info);
-    virtual bool GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
-    virtual bool GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
+    virtual void GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                            RegLocation rl_src2);
-    virtual bool GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
-    virtual bool GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
     virtual LIR* GenRegMemCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int base,
                                 int offset, ThrowKind kind);
diff --git a/src/compiler/codegen/mips/fp_mips.cc b/src/compiler/codegen/mips/fp_mips.cc
index e7b106e..0c4653d 100644
--- a/src/compiler/codegen/mips/fp_mips.cc
+++ b/src/compiler/codegen/mips/fp_mips.cc
@@ -22,7 +22,7 @@
 
 namespace art {
 
-bool MipsCodegen::GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode,
+void MipsCodegen::GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode,
                                   RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
 {
   int op = kMipsNop;
@@ -55,23 +55,21 @@
       CallRuntimeHelperRegLocationRegLocation(cu, ENTRYPOINT_OFFSET(pFmodf), rl_src1, rl_src2, false);
       rl_result = GetReturn(cu, true);
       StoreValue(cu, rl_dest, rl_result);
-      return false;
+      return;
     case Instruction::NEG_FLOAT:
       GenNegFloat(cu, rl_dest, rl_src1);
-      return false;
+      return;
     default:
-      return true;
+      LOG(FATAL) << "Unexpected opcode: " << opcode;
   }
   rl_src1 = LoadValue(cu, rl_src1, kFPReg);
   rl_src2 = LoadValue(cu, rl_src2, kFPReg);
   rl_result = EvalLoc(cu, rl_dest, kFPReg, true);
   NewLIR3(cu, op, rl_result.low_reg, rl_src1.low_reg, rl_src2.low_reg);
   StoreValue(cu, rl_dest, rl_result);
-
-  return false;
 }
 
-bool MipsCodegen::GenArithOpDouble(CompilationUnit *cu, Instruction::Code opcode,
+void MipsCodegen::GenArithOpDouble(CompilationUnit *cu, Instruction::Code opcode,
                                    RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
 {
   int op = kMipsNop;
@@ -100,12 +98,12 @@
       CallRuntimeHelperRegLocationRegLocation(cu, ENTRYPOINT_OFFSET(pFmod), rl_src1, rl_src2, false);
       rl_result = GetReturnWide(cu, true);
       StoreValueWide(cu, rl_dest, rl_result);
-      return false;
+      return;
     case Instruction::NEG_DOUBLE:
       GenNegDouble(cu, rl_dest, rl_src1);
-      return false;
+      return;
     default:
-      return true;
+      LOG(FATAL) << "Unpexpected opcode: " << opcode;
   }
   rl_src1 = LoadValueWide(cu, rl_src1, kFPReg);
   DCHECK(rl_src1.wide);
@@ -117,10 +115,9 @@
   NewLIR3(cu, op, S2d(rl_result.low_reg, rl_result.high_reg), S2d(rl_src1.low_reg, rl_src1.high_reg),
           S2d(rl_src2.low_reg, rl_src2.high_reg));
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
-bool MipsCodegen::GenConversion(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
+void MipsCodegen::GenConversion(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
                                 RegLocation rl_src)
 {
   int op = kMipsNop;
@@ -140,19 +137,25 @@
       op = kMipsFcvtdw;
       break;
     case Instruction::FLOAT_TO_INT:
-      return GenConversionCall(cu, ENTRYPOINT_OFFSET(pF2iz), rl_dest, rl_src);
+      GenConversionCall(cu, ENTRYPOINT_OFFSET(pF2iz), rl_dest, rl_src);
+      return;
     case Instruction::DOUBLE_TO_INT:
-      return GenConversionCall(cu, ENTRYPOINT_OFFSET(pD2iz), rl_dest, rl_src);
+      GenConversionCall(cu, ENTRYPOINT_OFFSET(pD2iz), rl_dest, rl_src);
+      return;
     case Instruction::LONG_TO_DOUBLE:
-      return GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2d), rl_dest, rl_src);
+      GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2d), rl_dest, rl_src);
+      return;
     case Instruction::FLOAT_TO_LONG:
-      return GenConversionCall(cu, ENTRYPOINT_OFFSET(pF2l), rl_dest, rl_src);
+      GenConversionCall(cu, ENTRYPOINT_OFFSET(pF2l), rl_dest, rl_src);
+      return;
     case Instruction::LONG_TO_FLOAT:
-      return GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2f), rl_dest, rl_src);
+      GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2f), rl_dest, rl_src);
+      return;
     case Instruction::DOUBLE_TO_LONG:
-      return GenConversionCall(cu, ENTRYPOINT_OFFSET(pD2l), rl_dest, rl_src);
+      GenConversionCall(cu, ENTRYPOINT_OFFSET(pD2l), rl_dest, rl_src);
+      return;
     default:
-      return true;
+      LOG(FATAL) << "Unexpected opcode: " << opcode;
   }
   if (rl_src.wide) {
     rl_src = LoadValueWide(cu, rl_src, kFPReg);
@@ -170,14 +173,13 @@
     NewLIR2(cu, op, rl_result.low_reg, src_reg);
     StoreValue(cu, rl_dest, rl_result);
   }
-  return false;
 }
 
-bool MipsCodegen::GenCmpFP(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
+void MipsCodegen::GenCmpFP(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
                            RegLocation rl_src1, RegLocation rl_src2)
 {
   bool wide = true;
-  int offset;
+  int offset = -1; // Make gcc happy.
 
   switch (opcode) {
     case Instruction::CMPL_FLOAT:
@@ -195,7 +197,7 @@
       offset = ENTRYPOINT_OFFSET(pCmpgDouble);
       break;
     default:
-      return true;
+      LOG(FATAL) << "Unexpected opcode: " << opcode;
   }
   FlushAllRegs(cu);
   LockCallTemps(cu);
@@ -211,7 +213,6 @@
   OpReg(cu, kOpBlx, r_tgt);
   RegLocation rl_result = GetReturn(cu, false);
   StoreValue(cu, rl_dest, rl_result);
-  return false;
 }
 
 void MipsCodegen::GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir,
diff --git a/src/compiler/codegen/mips/int_mips.cc b/src/compiler/codegen/mips/int_mips.cc
index 675cf8d..31c13f2 100644
--- a/src/compiler/codegen/mips/int_mips.cc
+++ b/src/compiler/codegen/mips/int_mips.cc
@@ -345,10 +345,9 @@
                              RegLocation rl_src2)
 {
   LOG(FATAL) << "Unexpected use of GenMulLong for Mips";
-  return;
 }
 
-bool MipsCodegen::GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void MipsCodegen::GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                              RegLocation rl_src2)
 {
   rl_src1 = LoadValueWide(cu, rl_src1, kCoreReg);
@@ -369,10 +368,9 @@
   OpRegRegReg(cu, kOpAdd, rl_result.high_reg, rl_result.high_reg, t_reg);
   FreeTemp(cu, t_reg);
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
-bool MipsCodegen::GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void MipsCodegen::GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                              RegLocation rl_src2)
 {
   rl_src1 = LoadValueWide(cu, rl_src1, kCoreReg);
@@ -393,10 +391,9 @@
   OpRegRegReg(cu, kOpSub, rl_result.high_reg, rl_result.high_reg, t_reg);
   FreeTemp(cu, t_reg);
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
-bool MipsCodegen::GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
+void MipsCodegen::GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
 {
   rl_src = LoadValueWide(cu, rl_src, kCoreReg);
   RegLocation rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
@@ -415,28 +412,24 @@
   OpRegRegReg(cu, kOpSub, rl_result.high_reg, rl_result.high_reg, t_reg);
   FreeTemp(cu, t_reg);
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
-bool MipsCodegen::GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void MipsCodegen::GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                              RegLocation rl_src2)
 {
   LOG(FATAL) << "Unexpected use of GenAndLong for Mips";
-  return false;
 }
 
-bool MipsCodegen::GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void MipsCodegen::GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2)
 {
   LOG(FATAL) << "Unexpected use of GenOrLong for Mips";
-  return false;
 }
 
-bool MipsCodegen::GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void MipsCodegen::GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                              RegLocation rl_src2)
 {
   LOG(FATAL) << "Unexpected use of GenXorLong for Mips";
-  return false;
 }
 
 /*
@@ -642,18 +635,18 @@
   MarkGCCard(cu, r_value, r_array);
 }
 
-bool MipsCodegen::GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+void MipsCodegen::GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                                     RegLocation rl_src1, RegLocation rl_shift)
 {
   // Default implementation is just to ignore the constant case.
-  return GenShiftOpLong(cu, opcode, rl_dest, rl_src1, rl_shift);
+  GenShiftOpLong(cu, opcode, rl_dest, rl_src1, rl_shift);
 }
 
-bool MipsCodegen::GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
+void MipsCodegen::GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
                                     RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
 {
   // Default - bail to non-const handler.
-  return GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+  GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
 }
 
 }  // namespace art
diff --git a/src/compiler/codegen/mir_to_lir.cc b/src/compiler/codegen/mir_to_lir.cc
index 96de65e..23c3fe7 100644
--- a/src/compiler/codegen/mir_to_lir.cc
+++ b/src/compiler/codegen/mir_to_lir.cc
@@ -28,11 +28,10 @@
  * load/store utilities here, or target-dependent genXX() handlers
  * when necessary.
  */
-static bool CompileDalvikInstruction(CompilationUnit* cu, MIR* mir, BasicBlock* bb,
+static void CompileDalvikInstruction(CompilationUnit* cu, MIR* mir, BasicBlock* bb,
                                      LIR* label_list)
 {
   Codegen* cg = cu->cg.get();
-  bool res = false;   // Assume success
   RegLocation rl_src[3];
   RegLocation rl_dest = GetBadLoc();
   RegLocation rl_result = GetBadLoc();
@@ -265,7 +264,7 @@
     case Instruction::CMPG_FLOAT:
     case Instruction::CMPL_DOUBLE:
     case Instruction::CMPG_DOUBLE:
-      res = cg->GenCmpFP(cu, opcode, rl_dest, rl_src[0], rl_src[1]);
+      cg->GenCmpFP(cu, opcode, rl_dest, rl_src[0], rl_src[1]);
       break;
 
     case Instruction::CMP_LONG:
@@ -484,20 +483,20 @@
 
     case Instruction::NEG_INT:
     case Instruction::NOT_INT:
-      res = cg->GenArithOpInt(cu, opcode, rl_dest, rl_src[0], rl_src[0]);
+      cg->GenArithOpInt(cu, opcode, rl_dest, rl_src[0], rl_src[0]);
       break;
 
     case Instruction::NEG_LONG:
     case Instruction::NOT_LONG:
-      res = cg->GenArithOpLong(cu, opcode, rl_dest, rl_src[0], rl_src[0]);
+      cg->GenArithOpLong(cu, opcode, rl_dest, rl_src[0], rl_src[0]);
       break;
 
     case Instruction::NEG_FLOAT:
-      res = cg->GenArithOpFloat(cu, opcode, rl_dest, rl_src[0], rl_src[0]);
+      cg->GenArithOpFloat(cu, opcode, rl_dest, rl_src[0], rl_src[0]);
       break;
 
     case Instruction::NEG_DOUBLE:
-      res = cg->GenArithOpDouble(cu, opcode, rl_dest, rl_src[0], rl_src[0]);
+      cg->GenArithOpDouble(cu, opcode, rl_dest, rl_src[0], rl_src[0]);
       break;
 
     case Instruction::INT_TO_LONG:
@@ -660,9 +659,8 @@
       break;
 
     default:
-      res = true;
+      LOG(FATAL) << "Unexpected opcode: " << opcode;
   }
-  return res;
 }
 
 // Process extended MIR instructions
@@ -780,12 +778,7 @@
       continue;
     }
 
-    bool not_handled = CompileDalvikInstruction(cu, mir, bb, label_list);
-    if (not_handled) {
-      LOG(FATAL) << StringPrintf("%#06x: Opcode %#x (%s)",
-                                 mir->offset, opcode,
-                                 Instruction::Name(mir->dalvikInsn.opcode));
-    }
+    CompileDalvikInstruction(cu, mir, bb, label_list);
   }
 
   if (head_lir) {
diff --git a/src/compiler/codegen/x86/codegen_x86.h b/src/compiler/codegen/x86/codegen_x86.h
index 9cc17f1..15a4662 100644
--- a/src/compiler/codegen/x86/codegen_x86.h
+++ b/src/compiler/codegen/x86/codegen_x86.h
@@ -89,7 +89,7 @@
     virtual bool IsUnconditionalBranch(LIR* lir);
 
     // Required for target - Dalvik-level generators.
-    virtual bool GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                                    RegLocation rl_src1, RegLocation rl_src2);
     virtual void GenArrayObjPut(CompilationUnit* cu, int opt_flags, RegLocation rl_array,
                                 RegLocation rl_index, RegLocation rl_src, int scale);
@@ -97,32 +97,32 @@
                              RegLocation rl_index, RegLocation rl_dest, int scale);
     virtual void GenArrayPut(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
                              RegLocation rl_index, RegLocation rl_src, int scale);
-    virtual bool GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
+    virtual void GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
                                    RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_shift);
     virtual void GenMulLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
-    virtual bool GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
-    virtual bool GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
-    virtual bool GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
+    virtual void GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
                                   RegLocation rl_dest, RegLocation rl_src1,
                                   RegLocation rl_src2);
-    virtual bool GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
                                  RegLocation rl_src1, RegLocation rl_src2);
-    virtual bool GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                           RegLocation rl_src1, RegLocation rl_src2);
-    virtual bool GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+    virtual void GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                                RegLocation rl_src);
     virtual bool GenInlinedCas32(CompilationUnit* cu, CallInfo* info, bool need_write_barrier);
     virtual bool GenInlinedMinMaxInt(CompilationUnit *cu, CallInfo* info, bool is_min);
     virtual bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info);
-    virtual bool GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
-    virtual bool GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
+    virtual void GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                            RegLocation rl_src2);
-    virtual bool GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
-    virtual bool GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+    virtual void GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2);
     virtual LIR* GenRegMemCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int base,
                                 int offset, ThrowKind kind);
diff --git a/src/compiler/codegen/x86/fp_x86.cc b/src/compiler/codegen/x86/fp_x86.cc
index 00c2f53..0432587 100644
--- a/src/compiler/codegen/x86/fp_x86.cc
+++ b/src/compiler/codegen/x86/fp_x86.cc
@@ -21,7 +21,7 @@
 
 namespace art {
 
-bool X86Codegen::GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode,
+void X86Codegen::GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode,
                                  RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
   X86OpCode op = kX86Nop;
   RegLocation rl_result;
@@ -53,12 +53,12 @@
       CallRuntimeHelperRegLocationRegLocation(cu, ENTRYPOINT_OFFSET(pFmodf), rl_src1, rl_src2, false);
       rl_result = GetReturn(cu, true);
       StoreValue(cu, rl_dest, rl_result);
-      return false;
+      return;
     case Instruction::NEG_FLOAT:
       GenNegFloat(cu, rl_dest, rl_src1);
-      return false;
+      return;
     default:
-      return true;
+      LOG(FATAL) << "Unexpected opcode: " << opcode;
   }
   rl_src1 = LoadValue(cu, rl_src1, kFPReg);
   rl_src2 = LoadValue(cu, rl_src2, kFPReg);
@@ -73,11 +73,9 @@
   OpRegCopy(cu, r_dest, r_src1);
   NewLIR2(cu, op, r_dest, r_src2);
   StoreValue(cu, rl_dest, rl_result);
-
-  return false;
 }
 
-bool X86Codegen::GenArithOpDouble(CompilationUnit *cu, Instruction::Code opcode,
+void X86Codegen::GenArithOpDouble(CompilationUnit *cu, Instruction::Code opcode,
                                   RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
   X86OpCode op = kX86Nop;
   RegLocation rl_result;
@@ -105,12 +103,12 @@
       CallRuntimeHelperRegLocationRegLocation(cu, ENTRYPOINT_OFFSET(pFmod), rl_src1, rl_src2, false);
       rl_result = GetReturnWide(cu, true);
       StoreValueWide(cu, rl_dest, rl_result);
-      return false;
+      return;
     case Instruction::NEG_DOUBLE:
       GenNegDouble(cu, rl_dest, rl_src1);
-      return false;
+      return;
     default:
-      return true;
+      LOG(FATAL) << "Unexpected opcode: " << opcode;
   }
   rl_src1 = LoadValueWide(cu, rl_src1, kFPReg);
   DCHECK(rl_src1.wide);
@@ -129,10 +127,9 @@
   OpRegCopy(cu, r_dest, r_src1);
   NewLIR2(cu, op, r_dest, r_src2);
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
-bool X86Codegen::GenConversion(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
+void X86Codegen::GenConversion(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
                                RegLocation rl_src) {
   RegisterClass rcSrc = kFPReg;
   X86OpCode op = kX86Nop;
@@ -175,7 +172,7 @@
       branch_pos_overflow->target = NewLIR0(cu, kPseudoTargetLabel);
       branch_normal->target = NewLIR0(cu, kPseudoTargetLabel);
       StoreValue(cu, rl_dest, rl_result);
-      return false;
+      return;
     }
     case Instruction::DOUBLE_TO_INT: {
       rl_src = LoadValueWide(cu, rl_src, kFPReg);
@@ -197,19 +194,23 @@
       branch_pos_overflow->target = NewLIR0(cu, kPseudoTargetLabel);
       branch_normal->target = NewLIR0(cu, kPseudoTargetLabel);
       StoreValue(cu, rl_dest, rl_result);
-      return false;
+      return;
     }
     case Instruction::LONG_TO_DOUBLE:
-      return GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2d), rl_dest, rl_src);
+      GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2d), rl_dest, rl_src);
+      return;
     case Instruction::LONG_TO_FLOAT:
       // TODO: inline by using memory as a 64-bit source. Be careful about promoted registers.
-      return GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2f), rl_dest, rl_src);
+      GenConversionCall(cu, ENTRYPOINT_OFFSET(pL2f), rl_dest, rl_src);
+      return;
     case Instruction::FLOAT_TO_LONG:
-      return GenConversionCall(cu, ENTRYPOINT_OFFSET(pF2l), rl_dest, rl_src);
+      GenConversionCall(cu, ENTRYPOINT_OFFSET(pF2l), rl_dest, rl_src);
+      return;
     case Instruction::DOUBLE_TO_LONG:
-      return GenConversionCall(cu, ENTRYPOINT_OFFSET(pD2l), rl_dest, rl_src);
+      GenConversionCall(cu, ENTRYPOINT_OFFSET(pD2l), rl_dest, rl_src);
+      return;
     default:
-      return true;
+      LOG(INFO) << "Unexpected opcode: " << opcode;
   }
   if (rl_src.wide) {
     rl_src = LoadValueWide(cu, rl_src, rcSrc);
@@ -227,10 +228,9 @@
     NewLIR2(cu, op, rl_result.low_reg, src_reg);
     StoreValue(cu, rl_dest, rl_result);
   }
-  return false;
 }
 
-bool X86Codegen::GenCmpFP(CompilationUnit *cu, Instruction::Code code, RegLocation rl_dest,
+void X86Codegen::GenCmpFP(CompilationUnit *cu, Instruction::Code code, RegLocation rl_dest,
                           RegLocation rl_src1, RegLocation rl_src2) {
   bool single = (code == Instruction::CMPL_FLOAT) || (code == Instruction::CMPG_FLOAT);
   bool unordered_gt = (code == Instruction::CMPG_DOUBLE) || (code == Instruction::CMPG_FLOAT);
@@ -279,7 +279,6 @@
     branch->target = NewLIR0(cu, kPseudoTargetLabel);
   }
   StoreValue(cu, rl_dest, rl_result);
-  return false;
 }
 
 void X86Codegen::GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir, bool gt_bias,
diff --git a/src/compiler/codegen/x86/int_x86.cc b/src/compiler/codegen/x86/int_x86.cc
index d4a34f7..4dff95a 100644
--- a/src/compiler/codegen/x86/int_x86.cc
+++ b/src/compiler/codegen/x86/int_x86.cc
@@ -327,9 +327,8 @@
                             RegLocation rl_src2)
 {
   LOG(FATAL) << "Unexpected use of GenX86Long for x86";
-  return;
 }
-bool X86Codegen::GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void X86Codegen::GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                          RegLocation rl_src2)
 {
   // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
@@ -344,10 +343,9 @@
   RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1,
                           INVALID_SREG, INVALID_SREG};
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
-bool X86Codegen::GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void X86Codegen::GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2)
 {
   // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
@@ -362,10 +360,9 @@
   RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1,
                           INVALID_SREG, INVALID_SREG};
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
-bool X86Codegen::GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
+void X86Codegen::GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
                             RegLocation rl_src2)
 {
   // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
@@ -380,10 +377,9 @@
   RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1,
                           INVALID_SREG, INVALID_SREG};
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
-bool X86Codegen::GenOrLong(CompilationUnit* cu, RegLocation rl_dest,
+void X86Codegen::GenOrLong(CompilationUnit* cu, RegLocation rl_dest,
                            RegLocation rl_src1, RegLocation rl_src2)
 {
   // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
@@ -398,10 +394,9 @@
   RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1,
                           INVALID_SREG, INVALID_SREG};
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
-bool X86Codegen::GenXorLong(CompilationUnit* cu, RegLocation rl_dest,
+void X86Codegen::GenXorLong(CompilationUnit* cu, RegLocation rl_dest,
                             RegLocation rl_src1, RegLocation rl_src2)
 {
   // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
@@ -416,10 +411,9 @@
   RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1,
                           INVALID_SREG, INVALID_SREG};
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
-bool X86Codegen::GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
+void X86Codegen::GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src)
 {
   FlushAllRegs(cu);
   LockCallTemps(cu);  // Prepare for explicit register usage
@@ -431,7 +425,6 @@
   RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1,
                           INVALID_SREG, INVALID_SREG};
   StoreValueWide(cu, rl_dest, rl_result);
-  return false;
 }
 
 void X86Codegen::OpRegThreadMem(CompilationUnit* cu, OpKind op, int r_dest, int thread_offset) {
@@ -590,18 +583,18 @@
   MarkGCCard(cu, r_value, r_array);
 }
 
-bool X86Codegen::GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
+void X86Codegen::GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
                                    RegLocation rl_src1, RegLocation rl_shift)
 {
   // Default implementation is just to ignore the constant case.
-  return GenShiftOpLong(cu, opcode, rl_dest, rl_src1, rl_shift);
+  GenShiftOpLong(cu, opcode, rl_dest, rl_src1, rl_shift);
 }
 
-bool X86Codegen::GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
+void X86Codegen::GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
                                    RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
 {
   // Default - bail to non-const handler.
-  return GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
+  GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2);
 }
 
 }  // namespace art