X86_64: Fix core.oat compilation issues
Fix neg-long and X86Mir2Lir::GenInstanceofFinal
Change-Id: I7fbcc1a89857cc461f74b55573ac6cb7c8e64561
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
diff --git a/compiler/dex/quick/x86/assemble_x86.cc b/compiler/dex/quick/x86/assemble_x86.cc
index c383296..b52a4b7 100644
--- a/compiler/dex/quick/x86/assemble_x86.cc
+++ b/compiler/dex/quick/x86/assemble_x86.cc
@@ -896,7 +896,7 @@
}
void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) {
- EmitPrefixAndOpcode(entry, reg, NO_REG, NO_REG);
+ EmitPrefixAndOpcode(entry, NO_REG, NO_REG, reg);
reg = LowRegisterBits(reg);
// There's no 3-byte instruction with +rd
DCHECK(entry->skeleton.opcode != 0x0F ||
@@ -909,7 +909,7 @@
}
void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) {
- EmitPrefixAndOpcode(entry, reg, NO_REG, NO_REG);
+ EmitPrefixAndOpcode(entry, NO_REG, NO_REG, reg);
reg = LowRegisterBits(reg);
if (RegStorage::RegNum(reg) >= 4) {
DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " "
diff --git a/compiler/dex/quick/x86/int_x86.cc b/compiler/dex/quick/x86/int_x86.cc
index d214b8d..b110793 100644
--- a/compiler/dex/quick/x86/int_x86.cc
+++ b/compiler/dex/quick/x86/int_x86.cc
@@ -2154,7 +2154,12 @@
LoadConstant(result_reg, 0);
LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL);
- RegStorage check_class = AllocTypedTemp(false, kRefReg);
+ // We will use this register to compare to memory below.
+ // References are 32 bit in memory, and 64 bit in registers (in 64 bit mode).
+ // For this reason, force allocation of a 32 bit register to use, so that the
+ // compare to memory will be done using a 32 bit comparision.
+ // The LoadRefDisp(s) below will work normally, even in 64 bit mode.
+ RegStorage check_class = AllocTemp();
// If Method* is already in a register, we can save a copy.
RegLocation rl_method = mir_graph_->GetMethodLoc();