Fix cpplint whitespace/comma issues
Change-Id: I456fc8d80371d6dfc07e6d109b7f478c25602b65
diff --git a/compiler/dex/quick/arm/arm_lir.h b/compiler/dex/quick/arm/arm_lir.h
index fca17a1..93fee05 100644
--- a/compiler/dex/quick/arm/arm_lir.h
+++ b/compiler/dex/quick/arm/arm_lir.h
@@ -113,12 +113,12 @@
* rework is done in this area. Also, it is a good reminder in the calling
* code that reg locations always describe doubles as a pair of singles.
*/
-#define ARM_S2D(x,y) ((x) | ARM_FP_DOUBLE)
+#define ARM_S2D(x, y) ((x) | ARM_FP_DOUBLE)
// Mask to strip off fp flags.
#define ARM_FP_REG_MASK (ARM_FP_REG_OFFSET-1)
// RegisterLocation templates return values (r0, or r0/r1).
-#define ARM_LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r0, INVALID_REG,\
+#define ARM_LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r0, INVALID_REG, \
INVALID_SREG, INVALID_SREG}
#define ARM_LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1, \
INVALID_SREG, INVALID_SREG}
diff --git a/compiler/dex/quick/arm/assemble_arm.cc b/compiler/dex/quick/arm/assemble_arm.cc
index 9e14457..f4aa1f3 100644
--- a/compiler/dex/quick/arm/assemble_arm.cc
+++ b/compiler/dex/quick/arm/assemble_arm.cc
@@ -875,7 +875,7 @@
ENCODING_MAP(kThumb2Dmb, 0xf3bf8f50,
kFmtBitBlt, 3, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_UNARY_OP,
- "dmb","#!0B",4),
+ "dmb", "#!0B", 4),
ENCODING_MAP(kThumb2LdrPcReln12, 0xf85f0000,
kFmtBitBlt, 15, 12, kFmtBitBlt, 11, 0, kFmtUnused, -1, -1,
kFmtUnused, -1, -1,
diff --git a/compiler/dex/quick/arm/int_arm.cc b/compiler/dex/quick/arm/int_arm.cc
index ee2d76c..e12df6c 100644
--- a/compiler/dex/quick/arm/int_arm.cc
+++ b/compiler/dex/quick/arm/int_arm.cc
@@ -183,7 +183,7 @@
int dest_sreg = mir->ssa_rep->defs[0];
if ((dest_sreg < 0) || (dest_sreg >= mir_graph_->GetNumSSARegs())) {
LOG(INFO) << "Bad target sreg: " << dest_sreg << ", in "
- << PrettyMethod(cu_->method_idx,*cu_->dex_file);
+ << PrettyMethod(cu_->method_idx, *cu_->dex_file);
LOG(INFO) << "at dex offset 0x" << std::hex << mir->offset;
LOG(INFO) << "vreg = " << mir_graph_->SRegToVReg(dest_sreg);
LOG(INFO) << "num uses = " << mir->ssa_rep->num_uses;
diff --git a/compiler/dex/quick/arm/target_arm.cc b/compiler/dex/quick/arm/target_arm.cc
index 7021593..441445d 100644
--- a/compiler/dex/quick/arm/target_arm.cc
+++ b/compiler/dex/quick/arm/target_arm.cc
@@ -272,7 +272,7 @@
static char* DecodeFPCSRegList(int count, int base, char* buf) {
sprintf(buf, "s%d", base);
for (int i = 1; i < count; i++) {
- sprintf(buf + strlen(buf), ", s%d",base + i);
+ sprintf(buf + strlen(buf), ", s%d", base + i);
}
return buf;
}
@@ -296,8 +296,8 @@
return bits >> (((value & 0xf80) >> 7) - 8);
}
-const char* cc_names[] = {"eq","ne","cs","cc","mi","pl","vs","vc",
- "hi","ls","ge","lt","gt","le","al","nv"};
+const char* cc_names[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
+ "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"};
/*
* Interpret a format string and build a string no longer than size
* See format key in Assemble.c.
@@ -324,9 +324,9 @@
switch (*fmt++) {
case 'H':
if (operand != 0) {
- sprintf(tbuf, ", %s %d",shift_names[operand & 0x3], operand >> 2);
+ sprintf(tbuf, ", %s %d", shift_names[operand & 0x3], operand >> 2);
} else {
- strcpy(tbuf,"");
+ strcpy(tbuf, "");
}
break;
case 'B':
@@ -356,7 +356,7 @@
strcpy(tbuf, name);
break;
case 'b':
- strcpy(tbuf,"0000");
+ strcpy(tbuf, "0000");
for (i=3; i>= 0; i--) {
tbuf[i] += operand & 1;
operand >>= 1;
@@ -364,41 +364,41 @@
break;
case 'n':
operand = ~ExpandImmediate(operand);
- sprintf(tbuf,"%d [%#x]", operand, operand);
+ sprintf(tbuf, "%d [%#x]", operand, operand);
break;
case 'm':
operand = ExpandImmediate(operand);
- sprintf(tbuf,"%d [%#x]", operand, operand);
+ sprintf(tbuf, "%d [%#x]", operand, operand);
break;
case 's':
- sprintf(tbuf,"s%d",operand & ARM_FP_REG_MASK);
+ sprintf(tbuf, "s%d", operand & ARM_FP_REG_MASK);
break;
case 'S':
- sprintf(tbuf,"d%d",(operand & ARM_FP_REG_MASK) >> 1);
+ sprintf(tbuf, "d%d", (operand & ARM_FP_REG_MASK) >> 1);
break;
case 'h':
- sprintf(tbuf,"%04x", operand);
+ sprintf(tbuf, "%04x", operand);
break;
case 'M':
case 'd':
- sprintf(tbuf,"%d", operand);
+ sprintf(tbuf, "%d", operand);
break;
case 'C':
DCHECK_LT(operand, static_cast<int>(
sizeof(core_reg_names)/sizeof(core_reg_names[0])));
- sprintf(tbuf,"%s",core_reg_names[operand]);
+ sprintf(tbuf, "%s", core_reg_names[operand]);
break;
case 'E':
- sprintf(tbuf,"%d", operand*4);
+ sprintf(tbuf, "%d", operand*4);
break;
case 'F':
- sprintf(tbuf,"%d", operand*2);
+ sprintf(tbuf, "%d", operand*2);
break;
case 'c':
strcpy(tbuf, cc_names[operand]);
break;
case 't':
- sprintf(tbuf,"0x%08x (L%p)",
+ sprintf(tbuf, "0x%08x (L%p)",
reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4 +
(operand << 1),
lir->target);
@@ -428,7 +428,7 @@
DecodeFPCSRegList(operand, 0, tbuf);
break;
default:
- strcpy(tbuf,"DecodeError1");
+ strcpy(tbuf, "DecodeError1");
break;
}
buf += tbuf;