Fix cpplint's whitespace complaints.
Change-Id: I11fd2db2badf7bd98e7866ca2155d8ef1e112408
diff --git a/src/compiler/codegen/CodegenUtil.cc b/src/compiler/codegen/CodegenUtil.cc
index 2318a04..20eb47f 100644
--- a/src/compiler/codegen/CodegenUtil.cc
+++ b/src/compiler/codegen/CodegenUtil.cc
@@ -29,7 +29,7 @@
/* Clear out the memref flags */
*maskPtr &= ~mask;
/* ..and then add back the one we need */
- switch(memType) {
+ switch (memType) {
case kLiteral:
DCHECK(isLoad);
*maskPtr |= ENCODE_LITERAL;
@@ -255,7 +255,7 @@
const bool dumpNop = (cUnit->enableDebug & (1 << kDebugShowNops));
/* Handle pseudo-ops individually, and all regular insns as a group */
- switch(lir->opcode) {
+ switch (lir->opcode) {
case kPseudoMethodEntry:
LOG(INFO) << "-------- method entry " <<
PrettyMethod(cUnit->method_idx, *cUnit->dex_file);
diff --git a/src/compiler/codegen/GenCommon.cc b/src/compiler/codegen/GenCommon.cc
index 0ef1641..0b0d100 100644
--- a/src/compiler/codegen/GenCommon.cc
+++ b/src/compiler/codegen/GenCommon.cc
@@ -367,7 +367,7 @@
rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
Instruction::Code opcode = mir->dalvikInsn.opcode;
- switch(opcode) {
+ switch (opcode) {
case Instruction::IF_EQ:
cond = kCondEq;
break;
@@ -406,7 +406,7 @@
ConditionCode cond;
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
Instruction::Code opcode = mir->dalvikInsn.opcode;
- switch(opcode) {
+ switch (opcode) {
case Instruction::IF_EQZ:
cond = kCondEq;
break;
@@ -458,7 +458,7 @@
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
OpKind op = kOpInvalid;
- switch(mir->dalvikInsn.opcode) {
+ switch (mir->dalvikInsn.opcode) {
case Instruction::INT_TO_BYTE:
op = kOp2Byte;
break;
@@ -887,7 +887,7 @@
int funcOffset = 0;
int v1 = lab->operands[2];
int v2 = lab->operands[3];
- switch(lab->operands[0]) {
+ switch (lab->operands[0]) {
case kThrowNullPointer:
funcOffset = OFFSETOF_MEMBER(Thread, pThrowNullPointerFromCode);
break;
@@ -1722,7 +1722,7 @@
{
int funcOffset;
- switch( mir->dalvikInsn.opcode) {
+ switch (mir->dalvikInsn.opcode) {
case Instruction::SHL_LONG:
case Instruction::SHL_LONG_2ADDR:
funcOffset = OFFSETOF_MEMBER(Thread, pShlLong);
diff --git a/src/compiler/codegen/GenInvoke.cc b/src/compiler/codegen/GenInvoke.cc
index ba027f0..e4feb4d 100644
--- a/src/compiler/codegen/GenInvoke.cc
+++ b/src/compiler/codegen/GenInvoke.cc
@@ -141,7 +141,7 @@
directMethod = 0;
#endif
if (directCode != 0 && directMethod != 0) {
- switch(state) {
+ switch (state) {
case 0: // Get the current Method* [sets rARG0]
if (directCode != (uintptr_t)-1) {
loadConstant(cUnit, rINVOKE_TGT, directCode);
@@ -180,7 +180,7 @@
return -1;
}
} else {
- switch(state) {
+ switch (state) {
case 0: // Get the current Method* [sets rARG0]
// TUNING: we can save a reg copy if Method* has been promoted
loadCurrMethodDirect(cUnit, rARG0);
@@ -245,7 +245,7 @@
* This is the fast path in which the target virtual method is
* fully resolved at compile time.
*/
- switch(state) {
+ switch (state) {
case 0: // Get "this" [set rARG1]
rlArg = oatGetSrc(cUnit, mir, 0);
loadValueDirectFixed(cUnit, rlArg, rARG1);
diff --git a/src/compiler/codegen/LocalOptimizations.cc b/src/compiler/codegen/LocalOptimizations.cc
index 3bed72f..b7a7e57 100644
--- a/src/compiler/codegen/LocalOptimizations.cc
+++ b/src/compiler/codegen/LocalOptimizations.cc
@@ -147,7 +147,7 @@
IS_STORE));
/* Same value && same register type */
if (checkLIR->aliasInfo == thisLIR->aliasInfo &&
- REGTYPE(checkLIR->operands[0]) == REGTYPE(nativeRegId)){
+ REGTYPE(checkLIR->operands[0]) == REGTYPE(nativeRegId)) {
/*
* Different destination register - insert
* a move
diff --git a/src/compiler/codegen/MethodCodegenDriver.cc b/src/compiler/codegen/MethodCodegenDriver.cc
index 87a86eb..d753fcc 100644
--- a/src/compiler/codegen/MethodCodegenDriver.cc
+++ b/src/compiler/codegen/MethodCodegenDriver.cc
@@ -186,7 +186,7 @@
rlDest = oatGetDestWide(cUnit, mir, 0, 1);
}
- switch(opcode) {
+ switch (opcode) {
case Instruction::NOP:
break;
diff --git a/src/compiler/codegen/RallocUtil.cc b/src/compiler/codegen/RallocUtil.cc
index 5f1f62d..6a98d60 100644
--- a/src/compiler/codegen/RallocUtil.cc
+++ b/src/compiler/codegen/RallocUtil.cc
@@ -79,7 +79,7 @@
void dumpRegPool(RegisterInfo* p, int numRegs)
{
LOG(INFO) << "================================================";
- for (int i = 0; i < numRegs; i++){
+ for (int i = 0; i < numRegs; i++) {
LOG(INFO) << StringPrintf(
"R[%d]: T:%d, U:%d, P:%d, p:%d, LV:%d, D:%d, SR:%d, ST:%x, EN:%x",
p[i].reg, p[i].isTemp, p[i].inUse, p[i].pair, p[i].partner,
@@ -434,7 +434,7 @@
RegisterInfo* allocLive(CompilationUnit* cUnit, int sReg, int regClass)
{
RegisterInfo* res = NULL;
- switch(regClass) {
+ switch (regClass) {
case kAnyReg:
res = allocLiveBody(cUnit->regPool->FPRegs,
cUnit->regPool->numFPRegs, sReg);
diff --git a/src/compiler/codegen/arm/ArchUtility.cc b/src/compiler/codegen/arm/ArchUtility.cc
index be6b44d..4346bda 100644
--- a/src/compiler/codegen/arm/ArchUtility.cc
+++ b/src/compiler/codegen/arm/ArchUtility.cc
@@ -25,7 +25,7 @@
ArmConditionCode oatArmConditionEncoding(ConditionCode code)
{
ArmConditionCode res;
- switch(code) {
+ switch (code) {
case kCondEq: res = kArmCondEq; break;
case kCondNe: res = kArmCondNe; break;
case kCondCs: res = kArmCondCs; break;
@@ -113,7 +113,7 @@
{
int mode = (value & 0xf00) >> 8;
u4 bits = value & 0xff;
- switch(mode) {
+ switch (mode) {
case 0:
return bits;
case 1:
@@ -156,7 +156,7 @@
DCHECK_LT(fmt, fmtEnd);
DCHECK_LT((unsigned)(nc-'0'), 4U);
operand = lir->operands[nc-'0'];
- switch(*fmt++) {
+ switch (*fmt++) {
case 'H':
if (operand != 0) {
sprintf(tbuf, ", %s %d",shiftNames[operand & 0x3],
diff --git a/src/compiler/codegen/arm/Assemble.cc b/src/compiler/codegen/arm/Assemble.cc
index 8901bf3..1b7dc29 100644
--- a/src/compiler/codegen/arm/Assemble.cc
+++ b/src/compiler/codegen/arm/Assemble.cc
@@ -1256,7 +1256,7 @@
u4 operand;
u4 value;
operand = lir->operands[i];
- switch(encoder->fieldLoc[i].kind) {
+ switch (encoder->fieldLoc[i].kind) {
case kFmtUnused:
break;
case kFmtFPImm:
diff --git a/src/compiler/codegen/arm/FP/Thumb2VFP.cc b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
index 7f372aa..72b4fec 100644
--- a/src/compiler/codegen/arm/FP/Thumb2VFP.cc
+++ b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
@@ -189,7 +189,7 @@
int defaultResult;
RegLocation rlResult;
- switch(mir->dalvikInsn.opcode) {
+ switch (mir->dalvikInsn.opcode) {
case Instruction::CMPL_FLOAT:
isDouble = false;
defaultResult = -1;
diff --git a/src/compiler/codegen/arm/Thumb2/Factory.cc b/src/compiler/codegen/arm/Thumb2/Factory.cc
index 11d5bf4..e065a2f 100644
--- a/src/compiler/codegen/arm/Thumb2/Factory.cc
+++ b/src/compiler/codegen/arm/Thumb2/Factory.cc
@@ -418,7 +418,7 @@
int modImm = modifiedImmediate(value);
int modImmNeg = modifiedImmediate(-value);
- switch(op) {
+ switch (op) {
case kOpLsl:
if (allLowRegs)
return newLIR3(cUnit, kThumbLslRRI5, rDest, rSrc1, value);
diff --git a/src/compiler/codegen/arm/Thumb2/Gen.cc b/src/compiler/codegen/arm/Thumb2/Gen.cc
index 1938960..d5a4efc 100644
--- a/src/compiler/codegen/arm/Thumb2/Gen.cc
+++ b/src/compiler/codegen/arm/Thumb2/Gen.cc
@@ -251,7 +251,7 @@
{
cUnit->currentDalvikOffset = mir->offset;
MIR* nextMir = NULL;
- switch(specialCase) {
+ switch (specialCase) {
case kNullMethod:
DCHECK(mir->dalvikInsn.opcode == Instruction::RETURN_VOID);
nextMir = mir;
@@ -341,7 +341,7 @@
int mask1 = 0;
//Note: case fallthroughs intentional
- switch(strlen(guide)) {
+ switch (strlen(guide)) {
case 3:
mask1 = (guide[2] == 'T') ? condBit : altBit;
case 2:
diff --git a/src/compiler/codegen/mips/ArchUtility.cc b/src/compiler/codegen/mips/ArchUtility.cc
index 40188ce..4252d50 100644
--- a/src/compiler/codegen/mips/ArchUtility.cc
+++ b/src/compiler/codegen/mips/ArchUtility.cc
@@ -54,7 +54,7 @@
DCHECK_LT(fmt, fmtEnd);
DCHECK_LT((unsigned)(nc-'0'), 4u);
operand = lir->operands[nc-'0'];
- switch(*fmt++) {
+ switch (*fmt++) {
case 'b':
strcpy(tbuf,"0000");
for (i=3; i>= 0; i--) {
diff --git a/src/compiler/codegen/mips/Assemble.cc b/src/compiler/codegen/mips/Assemble.cc
index 07a9975..1d629be 100644
--- a/src/compiler/codegen/mips/Assemble.cc
+++ b/src/compiler/codegen/mips/Assemble.cc
@@ -467,7 +467,7 @@
bool unconditional = false;
int opcode = lir->opcode;
int dalvikOffset = lir->dalvikOffset;
- switch(opcode) {
+ switch (opcode) {
case kMipsBal:
LOG(FATAL) << "long branch and link unsupported";
case kMipsB:
@@ -656,7 +656,7 @@
u4 operand;
u4 value;
operand = lir->operands[i];
- switch(encoder->fieldLoc[i].kind) {
+ switch (encoder->fieldLoc[i].kind) {
case kFmtUnused:
break;
case kFmtBitBlt:
diff --git a/src/compiler/codegen/mips/FP/MipsFP.cc b/src/compiler/codegen/mips/FP/MipsFP.cc
index d8ca0a1..6524641 100644
--- a/src/compiler/codegen/mips/FP/MipsFP.cc
+++ b/src/compiler/codegen/mips/FP/MipsFP.cc
@@ -189,7 +189,7 @@
bool wide = true;
int offset;
- switch(mir->dalvikInsn.opcode) {
+ switch (mir->dalvikInsn.opcode) {
case Instruction::CMPL_FLOAT:
offset = OFFSETOF_MEMBER(Thread, pCmplFloat);
wide = false;
diff --git a/src/compiler/codegen/mips/Mips32/Factory.cc b/src/compiler/codegen/mips/Mips32/Factory.cc
index 0ee936e..1162702 100644
--- a/src/compiler/codegen/mips/Mips32/Factory.cc
+++ b/src/compiler/codegen/mips/Mips32/Factory.cc
@@ -235,7 +235,7 @@
MipsOpCode opcode = kMipsNop;
bool shortForm = true;
- switch(op) {
+ switch (op) {
case kOpAdd:
if (IS_SIMM16(value)) {
opcode = kMipsAddiu;
diff --git a/src/compiler/codegen/mips/Mips32/Gen.cc b/src/compiler/codegen/mips/Mips32/Gen.cc
index 4530517..bf65ba6 100644
--- a/src/compiler/codegen/mips/Mips32/Gen.cc
+++ b/src/compiler/codegen/mips/Mips32/Gen.cc
@@ -357,7 +357,7 @@
MipsOpCode brOp;
bool cmpZero = false;
bool swapped = false;
- switch(cond) {
+ switch (cond) {
case kCondEq:
brOp = kMipsBeq;
cmpZero = true;
@@ -430,7 +430,7 @@
return branch;
}
MipsOpCode opc;
- switch(cond) {
+ switch (cond) {
case kCondEq: opc = kMipsBeqz; break;
case kCondGe: opc = kMipsBgez; break;
case kCondGt: opc = kMipsBgtz; break;
diff --git a/src/compiler/codegen/x86/ArchUtility.cc b/src/compiler/codegen/x86/ArchUtility.cc
index a5987f2..fa94db3 100644
--- a/src/compiler/codegen/x86/ArchUtility.cc
+++ b/src/compiler/codegen/x86/ArchUtility.cc
@@ -55,7 +55,7 @@
std::string buf;
size_t i = 0;
size_t fmt_len = strlen(fmt);
- while(i < fmt_len) {
+ while (i < fmt_len) {
if (fmt[i] != '!') {
buf += fmt[i];
i++;
@@ -71,7 +71,7 @@
DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands.
DCHECK_LT(i, fmt_len);
int operand = lir->operands[operand_number];
- switch(fmt[i]) {
+ switch (fmt[i]) {
case 'c':
DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName));
buf += x86CondName[operand];
diff --git a/src/compiler/codegen/x86/Assemble.cc b/src/compiler/codegen/x86/Assemble.cc
index b62b5b4..d1a8d64 100644
--- a/src/compiler/codegen/x86/Assemble.cc
+++ b/src/compiler/codegen/x86/Assemble.cc
@@ -433,7 +433,7 @@
return 5; // opcode + rel32
}
case kCall:
- switch(lir->opcode) {
+ switch (lir->opcode) {
case kX86CallR: return 2; // opcode modrm
case kX86CallM: // lir operands - 0: base, 1: disp
return computeSize(entry, lir->operands[1], false);
@@ -1030,7 +1030,7 @@
}
const X86EncodingMap *entry = &EncodingMap[lir->opcode];
size_t starting_cbuf_size = cUnit->codeBuffer.size();
- switch(entry->kind) {
+ switch (entry->kind) {
case kData: // 4 bytes of data
cUnit->codeBuffer.push_back(lir->operands[0]);
break;
@@ -1095,7 +1095,7 @@
emitJcc(cUnit, entry, lir->operands[0], lir->operands[1]);
break;
case kCall:
- switch(entry->opcode) {
+ switch (entry->opcode) {
case kX86CallM: // lir operands - 0: base, 1: disp
emitCallMem(cUnit, entry, lir->operands[0], lir->operands[1]);
break;
diff --git a/src/compiler/codegen/x86/X86/Gen.cc b/src/compiler/codegen/x86/X86/Gen.cc
index c6cd55c..f957cbc 100644
--- a/src/compiler/codegen/x86/X86/Gen.cc
+++ b/src/compiler/codegen/x86/X86/Gen.cc
@@ -387,7 +387,7 @@
}
X86ConditionCode oatX86ConditionEncoding(ConditionCode cond) {
- switch(cond) {
+ switch (cond) {
case kCondEq: return kX86CondEq;
case kCondNe: return kX86CondNe;
case kCondCs: return kX86CondC;