commit b3a84e2f308b3ed7d17b8e96fc7adfcac36ebe77
author Lupusoru, Razvan A <razvan.a.lupusoru@intel.com> Mon Jul 28 14:11:01 2014 -0700
committer Razvan A Lupusoru <razvan.a.lupusoru@intel.com> Wed Sep 03 10:05:40 2014 -0700
tree 381fb72a42defc934f01cddab40a63299c0ba592
parent 2a09504334a3a3b4c47100197df0827cc6740433

ART: Vectorization opcode implementation fixes

This patch fixes the implementation of the x86 vectorization opcodes.

Change-Id: I0028d54a9fa6edce791b7e3a053002d076798748
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
Signed-off-by: Philbert Lin <philbert.lin@intel.com>

compiler/dex/mir_graph.cc

diff --git a/compiler/dex/mir_graph.cc b/compiler/dex/mir_graph.cc
index e77be5d..62a8f26 100644
--- a/compiler/dex/mir_graph.cc
+++ b/compiler/dex/mir_graph.cc
@@ -68,6 +68,8 @@
   "ReserveVectorRegisters",
   "ReturnVectorRegisters",
   "MemBarrier",
+  "PackedArrayGet",
+  "PackedArrayPut",
 };
 
 MIRGraph::MIRGraph(CompilationUnit* cu, ArenaAllocator* arena)
@@ -1386,6 +1388,18 @@
       decoded_mir->append(ss.str());
       break;
     }
+    case kMirOpPackedArrayGet:
+    case kMirOpPackedArrayPut:
+      decoded_mir->append(StringPrintf(" vect%d", mir->dalvikInsn.vA));
+      if (ssa_rep != nullptr) {
+        decoded_mir->append(StringPrintf(", %s[%s]",
+                                        GetSSANameWithConst(ssa_rep->uses[0], false).c_str(),
+                                        GetSSANameWithConst(ssa_rep->uses[1], false).c_str()));
+      } else {
+        decoded_mir->append(StringPrintf(", v%d[v%d]", mir->dalvikInsn.vB, mir->dalvikInsn.vC));
+      }
+      FillTypeSizeString(mir->dalvikInsn.arg[0], decoded_mir);
+      break;
     default:
       break;
   }