commit b95a5345ae4217b70ca36f0cced92f68dda7caf5
author Stuart Monteith <stuart.monteith@arm.com> Wed Mar 12 13:32:32 2014 +0000
committer Andreas Gampe <agampe@google.com> Wed Mar 19 17:17:55 2014 -0700
tree d9c76db71eb8dd3a668643781eefe6152888fd1d
parent 66e4c3e96dccdec7423d673ad6bbf7821a776651

AArch64: Add arm64 runtime support.

Adds support for arm64 to ART. Assembler stubs are sufficient for
down calls into interpreter. JNI compiler and generics are not finished.

Basic Generic JNI functionality.

Change-Id: I4a07c79d1e037b9f5746673480e32cf456867b82

compiler/trampolines/trampoline_compiler.cc

diff --git a/compiler/trampolines/trampoline_compiler.cc b/compiler/trampolines/trampoline_compiler.cc
index 3e13e44..4dffef9 100644
--- a/compiler/trampolines/trampoline_compiler.cc
+++ b/compiler/trampolines/trampoline_compiler.cc
@@ -18,6 +18,7 @@
 
 #include "jni_internal.h"
 #include "utils/arm/assembler_arm.h"
+#include "utils/arm64/assembler_arm64.h"
 #include "utils/mips/assembler_mips.h"
 #include "utils/x86/assembler_x86.h"
 
@@ -53,6 +54,46 @@
 }
 }  // namespace arm
 
+namespace arm64 {
+static const std::vector<uint8_t>* CreateTrampoline(EntryPointCallingConvention abi,
+                                                    ThreadOffset offset) {
+  UniquePtr<Arm64Assembler> assembler(static_cast<Arm64Assembler*>(Assembler::Create(kArm64)));
+
+  switch (abi) {
+    case kInterpreterAbi:  // Thread* is first argument (X0) in interpreter ABI.
+      // FIXME IPx used by VIXL - this is unsafe.
+      __ Call(Arm64ManagedRegister::FromCoreRegister(X0), Offset(offset.Int32Value()),
+          Arm64ManagedRegister::FromCoreRegister(IP1));
+
+      break;
+    case kJniAbi:  // Load via Thread* held in JNIEnv* in first argument (X0).
+
+      __ LoadRawPtr(Arm64ManagedRegister::FromCoreRegister(IP1),
+                      Arm64ManagedRegister::FromCoreRegister(X0),
+                      Offset(JNIEnvExt::SelfOffset().Int32Value()));
+
+      // FIXME IPx used by VIXL - this is unsafe.
+      __ Call(Arm64ManagedRegister::FromCoreRegister(IP1), Offset(offset.Int32Value()),
+                Arm64ManagedRegister::FromCoreRegister(IP0));
+
+      break;
+    case kPortableAbi:  // X18 holds Thread*.
+    case kQuickAbi:  // Fall-through.
+      __ Call(Arm64ManagedRegister::FromCoreRegister(TR), Offset(offset.Int32Value()),
+                Arm64ManagedRegister::FromCoreRegister(IP0));
+
+      break;
+  }
+
+  size_t cs = assembler->CodeSize();
+  UniquePtr<std::vector<uint8_t> > entry_stub(new std::vector<uint8_t>(cs));
+  MemoryRegion code(&(*entry_stub)[0], entry_stub->size());
+  assembler->FinalizeInstructions(code);
+
+  return entry_stub.release();
+}
+}  // namespace arm64
+
 namespace mips {
 static const std::vector<uint8_t>* CreateTrampoline(EntryPointCallingConvention abi,
                                                     ThreadOffset offset) {
@@ -123,6 +164,8 @@
     case kArm:
     case kThumb2:
       return arm::CreateTrampoline(abi, offset);
+    case kArm64:
+      return arm64::CreateTrampoline(abi, offset);
     case kMips:
       return mips::CreateTrampoline(abi, offset);
     case kX86: