commit ba70200c03f0481543877b218a8626c107edfbf6
author David Srbecky <dsrbecky@google.com> Mon Feb 01 18:15:29 2016 +0000
committer David Srbecky <dsrbecky@google.com> Tue Feb 02 17:18:59 2016 +0000
tree e684332612c43e63b2af2799f2a28b0e9d2c95d5
parent 85fdcda926fbab0e5a7b3e8b3541f5d225b2bcdb

Add MIPS floating point register mapping to DWARF.

Change-Id: I88508461412bc166549843744a3c6a4ee925b2c7

compiler/elf_writer_debug.cc

diff --git a/compiler/elf_writer_debug.cc b/compiler/elf_writer_debug.cc
index 5dbbbc7..b43b86e 100644
--- a/compiler/elf_writer_debug.cc
+++ b/compiler/elf_writer_debug.cc
@@ -90,6 +90,10 @@
       return Reg::X86Fp(machine_reg);
     case kX86_64:
       return Reg::X86_64Fp(machine_reg);
+    case kMips:
+      return Reg::MipsFp(machine_reg);
+    case kMips64:
+      return Reg::Mips64Fp(machine_reg);
     default:
       LOG(FATAL) << "Unknown instruction set: " << isa;
       UNREACHABLE();
@@ -162,6 +166,14 @@
           opcodes.SameValue(Reg::MipsCore(reg));
         }
       }
+      // fp registers.
+      for (int reg = 0; reg < 32; reg++) {
+        if (reg < 24) {
+          opcodes.Undefined(Reg::Mips64Fp(reg));
+        } else {
+          opcodes.SameValue(Reg::Mips64Fp(reg));
+        }
+      }
       auto return_reg = Reg::MipsCore(31);  // R31(RA).
       WriteCIE(is64bit, return_reg, opcodes, format, buffer);
       return;
@@ -860,10 +872,6 @@
               expr.WriteOpReg(Reg::ArmDp(value / 2).num());
               break;
             }
-            if (isa == kMips || isa == kMips64) {
-              // TODO: Find what the DWARF floating point register numbers are on MIPS.
-              break;
-            }
             expr.WriteOpReg(GetDwarfFpReg(isa, value).num());
             if (piece == 0 && reg_hi.GetKind() == Kind::kInFpuRegisterHigh &&
                 reg_hi.GetValue() == reg_lo.GetValue()) {