commit ba70200c03f0481543877b218a8626c107edfbf6
author David Srbecky <dsrbecky@google.com> Mon Feb 01 18:15:29 2016 +0000
committer David Srbecky <dsrbecky@google.com> Tue Feb 02 17:18:59 2016 +0000
tree e684332612c43e63b2af2799f2a28b0e9d2c95d5
parent 85fdcda926fbab0e5a7b3e8b3541f5d225b2bcdb

Add MIPS floating point register mapping to DWARF.

Change-Id: I88508461412bc166549843744a3c6a4ee925b2c7

compiler/optimizing/code_generator_mips64.cc

diff --git a/compiler/optimizing/code_generator_mips64.cc b/compiler/optimizing/code_generator_mips64.cc
index cefcb95..3e1563c 100644
--- a/compiler/optimizing/code_generator_mips64.cc
+++ b/compiler/optimizing/code_generator_mips64.cc
@@ -523,7 +523,9 @@
   return dwarf::Reg::Mips64Core(static_cast<int>(reg));
 }
 
-// TODO: mapping of floating-point registers to DWARF
+static dwarf::Reg DWARFReg(FpuRegister reg) {
+  return dwarf::Reg::Mips64Fp(static_cast<int>(reg));
+}
 
 void CodeGeneratorMIPS64::GenerateFrameEntry() {
   __ Bind(&frame_entry_label_);
@@ -573,7 +575,7 @@
     if (allocated_registers_.ContainsFloatingPointRegister(reg)) {
       ofs -= kMips64DoublewordSize;
       __ Sdc1(reg, SP, ofs);
-      // TODO: __ cfi().RelOffset(DWARFReg(reg), ofs);
+      __ cfi().RelOffset(DWARFReg(reg), ofs);
     }
   }
 
@@ -610,7 +612,7 @@
       if (allocated_registers_.ContainsFloatingPointRegister(reg)) {
         __ Ldc1(reg, SP, ofs);
         ofs += kMips64DoublewordSize;
-        // TODO: __ cfi().Restore(DWARFReg(reg));
+        __ cfi().Restore(DWARFReg(reg));
       }
     }