AArch64: Rename A64_/A32_ register prefix to x/w.
A64/A32 look like architecture name, but they are all for arm64.
Use lower-case to name the registers defined in "ARM ARM" which can
also be directly used in assembly file.
Use upper-case to name the registers which are other aliases.
Change-Id: I0ac38ed75f977fdc362288b01179b84feaee5614
diff --git a/compiler/dex/quick/arm64/utility_arm64.cc b/compiler/dex/quick/arm64/utility_arm64.cc
index c8d45c6..e248410 100644
--- a/compiler/dex/quick/arm64/utility_arm64.cc
+++ b/compiler/dex/quick/arm64/utility_arm64.cc
@@ -554,7 +554,7 @@
/* RegReg operations with SP in first parameter need extended register instruction form.
* Only CMN and CMP instructions are implemented.
*/
- if (r_dest_src1 == rs_rA64_SP) {
+ if (r_dest_src1 == rs_sp) {
return OpRegRegExtend(op, r_dest_src1, r_src2, ENCODE_NO_EXTEND);
} else {
return OpRegRegShift(op, r_dest_src1, r_src2, ENCODE_NO_SHIFT);
@@ -1110,7 +1110,7 @@
// TODO: in future may need to differentiate Dalvik accesses w/ spills
if (mem_ref_type_ == ResourceMask::kDalvikReg) {
- DCHECK(r_base == rs_rA64_SP);
+ DCHECK(r_base == rs_sp);
AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, r_dest.Is64Bit());
}
return load;
@@ -1203,7 +1203,7 @@
// TODO: In future, may need to differentiate Dalvik & spill accesses.
if (mem_ref_type_ == ResourceMask::kDalvikReg) {
- DCHECK(r_base == rs_rA64_SP);
+ DCHECK(r_base == rs_sp);
AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, r_src.Is64Bit());
}
return store;