Trivial cleanup of typos and fixed-length buffers.
Change-Id: I4ea3bb51320160c5ebda8b2a8ba3ca81452915b5
diff --git a/src/compiler/codegen/CodegenUtil.cc b/src/compiler/codegen/CodegenUtil.cc
index c9c9c5e..2e2c254 100644
--- a/src/compiler/codegen/CodegenUtil.cc
+++ b/src/compiler/codegen/CodegenUtil.cc
@@ -326,33 +326,29 @@
}
}
-#define BSZ 100
void oatDumpPromotionMap(CompilationUnit *cUnit)
{
int numRegs = cUnit->numDalvikRegisters + cUnit->numCompilerTemps + 1;
for (int i = 0; i < numRegs; i++) {
PromotionMap vRegMap = cUnit->promotionMap[i];
- char buf[BSZ];
+ std::string buf;
if (vRegMap.fpLocation == kLocPhysReg) {
- snprintf(buf, 100, " : s%d", vRegMap.fpReg & FP_REG_MASK);
- } else {
- buf[0] = 0;
- }
- char buf2[BSZ];
- char buf3[BSZ];
- if (i < cUnit->numDalvikRegisters) {
- snprintf(buf3, BSZ, "%02d", i);
- } else if (i == cUnit->methodSReg) {
- strncpy(buf3, "Method*", BSZ);
- } else {
- snprintf(buf3, BSZ, "ct%d", i - cUnit->numDalvikRegisters);
+ StringAppendF(&buf, " : s%d", vRegMap.fpReg & FP_REG_MASK);
}
- snprintf(buf2, BSZ, "V[%s] -> %s%d%s", buf3,
+ std::string buf3;
+ if (i < cUnit->numDalvikRegisters) {
+ StringAppendF(&buf3, "%02d", i);
+ } else if (i == cUnit->methodSReg) {
+ buf3 = "Method*";
+ } else {
+ StringAppendF(&buf3, "ct%d", i - cUnit->numDalvikRegisters);
+ }
+
+ LOG(INFO) << StringPrintf("V[%s] -> %s%d%s", buf3.c_str(),
vRegMap.coreLocation == kLocPhysReg ?
"r" : "SP+", vRegMap.coreLocation == kLocPhysReg ?
- vRegMap.coreReg : oatSRegOffset(cUnit, i), buf);
- LOG(INFO) << buf2;
+ vRegMap.coreReg : oatSRegOffset(cUnit, i), buf.c_str());
}
}
diff --git a/src/compiler/codegen/GenInvoke.cc b/src/compiler/codegen/GenInvoke.cc
index 4847ef8..037a9bb 100644
--- a/src/compiler/codegen/GenInvoke.cc
+++ b/src/compiler/codegen/GenInvoke.cc
@@ -131,7 +131,7 @@
}
/*
- * Bit of a hack here - in leiu of a real scheduling pass,
+ * Bit of a hack here - in the absence of a real scheduling pass,
* emit the next instruction in static & direct invoke sequences.
*/
int nextSDCallInsn(CompilationUnit* cUnit, MIR* mir,
@@ -233,7 +233,7 @@
}
/*
- * Bit of a hack here - in leiu of a real scheduling pass,
+ * Bit of a hack here - in the absence of a real scheduling pass,
* emit the next instruction in a virtual invoke sequence.
* We can use rLR as a temp prior to target address loading
* Note also that we'll load the first argument ("this") into
diff --git a/src/compiler/codegen/RallocUtil.cc b/src/compiler/codegen/RallocUtil.cc
index b3fa739..5f1f62d 100644
--- a/src/compiler/codegen/RallocUtil.cc
+++ b/src/compiler/codegen/RallocUtil.cc
@@ -78,16 +78,13 @@
void dumpRegPool(RegisterInfo* p, int numRegs)
{
- int i;
LOG(INFO) << "================================================";
- for (i=0; i < numRegs; i++ ){
- char buf[100];
- snprintf(buf, 100,
+ for (int i = 0; i < numRegs; i++){
+ LOG(INFO) << StringPrintf(
"R[%d]: T:%d, U:%d, P:%d, p:%d, LV:%d, D:%d, SR:%d, ST:%x, EN:%x",
p[i].reg, p[i].isTemp, p[i].inUse, p[i].pair, p[i].partner,
p[i].live, p[i].dirty, p[i].sReg,(int)p[i].defStart,
(int)p[i].defEnd);
- LOG(INFO) << buf;
}
LOG(INFO) << "================================================";
}
@@ -158,7 +155,7 @@
* registers are the same as the Dalvik register number (and
* thus take the same position in the promotionMap. However,
* the special Method* and compiler temp resisters use negative
- * vReg numbers to distinquish them and can have an arbitrary
+ * vReg numbers to distinguish them and can have an arbitrary
* ssa name (above the last original Dalvik register). This function
* maps SSA names to positions in the promotionMap array.
*/