C++'ification of Quick compiler's casts
o Eliminate old useless LIR casts.
o Replace remaining C-style casts with new C++ versions.
o Unified instruction encoding enum
o Expand usage of the auto-generated ostream helpers for enum LOG messages.
o Replaced all usages of intptr_t with uintptr_t.
o Fixed bug in removeRedundantBranches, and moved to common code
Change-Id: I53211c0de1be913f958c8fde915296ac08345b7e
diff --git a/src/compiler/codegen/mips/target_mips.cc b/src/compiler/codegen/mips/target_mips.cc
index a5a8d7e..e157760 100644
--- a/src/compiler/codegen/mips/target_mips.cc
+++ b/src/compiler/codegen/mips/target_mips.cc
@@ -199,7 +199,7 @@
strcpy(tbuf, "!");
} else {
DCHECK_LT(fmt, fmtEnd);
- DCHECK_LT((unsigned)(nc-'0'), 4u);
+ DCHECK_LT(static_cast<unsigned>(nc-'0'), 4u);
operand = lir->operands[nc-'0'];
switch (*fmt++) {
case 'b':
@@ -233,19 +233,19 @@
sprintf(tbuf,"%d", operand*2);
break;
case 't':
- sprintf(tbuf,"0x%08x (L%p)", (int) baseAddr + lir->offset + 4 +
+ sprintf(tbuf,"0x%08x (L%p)", reinterpret_cast<uintptr_t>(baseAddr) + lir->offset + 4 +
(operand << 2), lir->target);
break;
case 'T':
- sprintf(tbuf,"0x%08x", (int) (operand << 2));
+ sprintf(tbuf,"0x%08x", operand << 2);
break;
case 'u': {
int offset_1 = lir->operands[0];
int offset_2 = NEXT_LIR(lir)->operands[0];
- intptr_t target =
- ((((intptr_t) baseAddr + lir->offset + 4) & ~3) +
+ uintptr_t target =
+ (((reinterpret_cast<uintptr_t>(baseAddr) + lir->offset + 4) & ~3) +
(offset_1 << 21 >> 9) + (offset_2 << 1)) & 0xfffffffc;
- sprintf(tbuf, "%p", (void *) target);
+ sprintf(tbuf, "%p", reinterpret_cast<void*>(target));
break;
}
@@ -275,11 +275,10 @@
}
// FIXME: need to redo resource maps for MIPS - fix this at that time
-void oatDumpResourceMask(LIR *lir, uint64_t mask, const char *prefix)
+void oatDumpResourceMask(LIR *mipsLIR, uint64_t mask, const char *prefix)
{
char buf[256];
buf[0] = 0;
- LIR *mipsLIR = (LIR *) lir;
if (mask == ENCODE_ALL) {
strcpy(buf, "all");
@@ -467,12 +466,6 @@
oatFreeTemp(cUnit, rMIPS_ARG3);
}
-/* Convert an instruction to a NOP */
-void oatNopLIR( LIR* lir)
-{
- ((LIR*)lir)->flags.isNop = true;
-}
-
/*
* Determine the initial instruction set to be used for this trace.
* Later components may decide to change this.
@@ -544,17 +537,15 @@
int numFPRegs = 0;
int numFPTemps = 0;
#endif
- RegisterPool *pool = (RegisterPool *)oatNew(cUnit, sizeof(*pool), true,
- kAllocRegAlloc);
+ RegisterPool *pool =
+ static_cast<RegisterPool*>(oatNew(cUnit, sizeof(*pool), true, kAllocRegAlloc));
cUnit->regPool = pool;
pool->numCoreRegs = numRegs;
- pool->coreRegs = (RegisterInfo *)
- oatNew(cUnit, numRegs * sizeof(*cUnit->regPool->coreRegs),
- true, kAllocRegAlloc);
+ pool->coreRegs = static_cast<RegisterInfo*>
+ (oatNew(cUnit, numRegs * sizeof(*cUnit->regPool->coreRegs), true, kAllocRegAlloc));
pool->numFPRegs = numFPRegs;
- pool->FPRegs = (RegisterInfo *)
- oatNew(cUnit, numFPRegs * sizeof(*cUnit->regPool->FPRegs), true,
- kAllocRegAlloc);
+ pool->FPRegs = static_cast<RegisterInfo*>
+ (oatNew(cUnit, numFPRegs * sizeof(*cUnit->regPool->FPRegs), true, kAllocRegAlloc));
oatInitPool(pool->coreRegs, coreRegs, pool->numCoreRegs);
oatInitPool(pool->FPRegs, fpRegs, pool->numFPRegs);
// Keep special registers from being allocated
@@ -573,9 +564,8 @@
oatMarkTemp(cUnit, fpTemps[i]);
}
// Construct the alias map.
- cUnit->phiAliasMap = (int*)oatNew(cUnit, cUnit->numSSARegs *
- sizeof(cUnit->phiAliasMap[0]), false,
- kAllocDFInfo);
+ cUnit->phiAliasMap = static_cast<int*>
+ (oatNew(cUnit, cUnit->numSSARegs * sizeof(cUnit->phiAliasMap[0]), false, kAllocDFInfo));
for (int i = 0; i < cUnit->numSSARegs; i++) {
cUnit->phiAliasMap[i] = i;
}
@@ -645,48 +635,11 @@
opRegImm(cUnit, kOpAdd, rMIPS_SP, cUnit->frameSize);
}
-/*
- * Nop any unconditional branches that go to the next instruction.
- * Note: new redundant branches may be inserted later, and we'll
- * use a check in final instruction assembly to nop those out.
- */
-void removeRedundantBranches(CompilationUnit* cUnit)
+bool branchUnconditional(LIR* lir)
{
- LIR* thisLIR;
-
- for (thisLIR = (LIR*) cUnit->firstLIRInsn;
- thisLIR != (LIR*) cUnit->lastLIRInsn;
- thisLIR = NEXT_LIR(thisLIR)) {
-
- /* Branch to the next instruction */
- if (thisLIR->opcode == kMipsB) {
- LIR* nextLIR = thisLIR;
-
- while (true) {
- nextLIR = NEXT_LIR(nextLIR);
-
- /*
- * Is the branch target the next instruction?
- */
- if (nextLIR == (LIR*) thisLIR->target) {
- thisLIR->flags.isNop = true;
- break;
- }
-
- /*
- * Found real useful stuff between the branch and the target.
- * Need to explicitly check the lastLIRInsn here because it
- * might be the last real instruction.
- */
- if (!isPseudoOpcode(nextLIR->opcode) ||
- (nextLIR = (LIR*) cUnit->lastLIRInsn))
- break;
- }
- }
- }
+ return (lir->opcode == kMipsB);
}
-
/* Common initialization routine for an architecture family */
bool oatArchInit()
{
@@ -695,8 +648,7 @@
for (i = 0; i < kMipsLast; i++) {
if (EncodingMap[i].opcode != i) {
LOG(FATAL) << "Encoding order for " << EncodingMap[i].name <<
- " is wrong: expecting " << i << ", seeing " <<
- (int)EncodingMap[i].opcode;
+ " is wrong: expecting " << i << ", seeing " << static_cast<int>(EncodingMap[i].opcode);
}
}