C++'ification of Quick compiler's casts
o Eliminate old useless LIR casts.
o Replace remaining C-style casts with new C++ versions.
o Unified instruction encoding enum
o Expand usage of the auto-generated ostream helpers for enum LOG messages.
o Replaced all usages of intptr_t with uintptr_t.
o Fixed bug in removeRedundantBranches, and moved to common code
Change-Id: I53211c0de1be913f958c8fde915296ac08345b7e
diff --git a/src/compiler/codegen/x86/assemble_x86.cc b/src/compiler/codegen/x86/assemble_x86.cc
index 63d2b83..0c2ff0d 100644
--- a/src/compiler/codegen/x86/assemble_x86.cc
+++ b/src/compiler/codegen/x86/assemble_x86.cc
@@ -557,7 +557,7 @@
reg = reg & X86_FP_REG_MASK;
}
if (reg >= 4) {
- DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg
+ DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)
<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);
}
DCHECK_LT(reg, 8);
@@ -614,7 +614,7 @@
reg = reg & X86_FP_REG_MASK;
}
if (reg >= 4) {
- DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg
+ DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)
<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);
}
DCHECK_LT(reg, 8);
@@ -705,7 +705,7 @@
reg = reg & X86_FP_REG_MASK;
}
if (reg >= 4) {
- DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg
+ DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)
<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);
}
DCHECK_LT(reg, 8);
@@ -958,7 +958,7 @@
DCHECK_EQ(0, entry->skeleton.extra_opcode2);
}
if (reg >= 4) {
- DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg
+ DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)
<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);
}
DCHECK_LT(reg, 8);
@@ -1118,11 +1118,11 @@
int base_or_table, uint8_t index, int scale, int table_or_disp) {
int disp;
if (entry->opcode == kX86PcRelLoadRA) {
- SwitchTable *tabRec = (SwitchTable*)table_or_disp;
+ SwitchTable *tabRec = reinterpret_cast<SwitchTable*>(table_or_disp);
disp = tabRec->offset;
} else {
DCHECK(entry->opcode == kX86PcRelAdr);
- FillArrayData *tabRec = (FillArrayData *)base_or_table;
+ FillArrayData *tabRec = reinterpret_cast<FillArrayData*>(base_or_table);
disp = tabRec->offset;
}
if (entry->skeleton.prefix1 != 0) {
@@ -1189,12 +1189,12 @@
* instruction. In those cases we will try to substitute a new code
* sequence or request that the trace be shortened and retried.
*/
-AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit, intptr_t startAddr) {
+AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit, uintptr_t startAddr) {
LIR *lir;
AssemblerStatus res = kSuccess; // Assume success
const bool kVerbosePcFixup = false;
- for (lir = (LIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {
+ for (lir = cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {
if (lir->opcode < 0) {
continue;
}
@@ -1209,13 +1209,13 @@
LIR *targetLIR = lir->target;
DCHECK(targetLIR != NULL);
int delta = 0;
- intptr_t pc;
+ uintptr_t pc;
if (IS_SIMM8(lir->operands[0])) {
pc = lir->offset + 2 /* opcode + rel8 */;
} else {
pc = lir->offset + 6 /* 2 byte opcode + rel32 */;
}
- intptr_t target = targetLIR->offset;
+ uintptr_t target = targetLIR->offset;
delta = target - pc;
if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {
if (kVerbosePcFixup) {
@@ -1239,8 +1239,8 @@
case kX86Jcc32: {
LIR *targetLIR = lir->target;
DCHECK(targetLIR != NULL);
- intptr_t pc = lir->offset + 6 /* 2 byte opcode + rel32 */;
- intptr_t target = targetLIR->offset;
+ uintptr_t pc = lir->offset + 6 /* 2 byte opcode + rel32 */;
+ uintptr_t target = targetLIR->offset;
int delta = target - pc;
if (kVerbosePcFixup) {
LOG(INFO) << "Source:";
@@ -1256,13 +1256,13 @@
LIR *targetLIR = lir->target;
DCHECK(targetLIR != NULL);
int delta = 0;
- intptr_t pc;
+ uintptr_t pc;
if (IS_SIMM8(lir->operands[0])) {
pc = lir->offset + 2 /* opcode + rel8 */;
} else {
pc = lir->offset + 5 /* opcode + rel32 */;
}
- intptr_t target = targetLIR->offset;
+ uintptr_t target = targetLIR->offset;
delta = target - pc;
if (!(cUnit->disableOpt & (1 << kSafeOptimizations)) && delta == 0) {
// Useless branch
@@ -1285,8 +1285,8 @@
case kX86Jmp32: {
LIR *targetLIR = lir->target;
DCHECK(targetLIR != NULL);
- intptr_t pc = lir->offset + 5 /* opcode + rel32 */;
- intptr_t target = targetLIR->offset;
+ uintptr_t pc = lir->offset + 5 /* opcode + rel32 */;
+ uintptr_t target = targetLIR->offset;
int delta = target - pc;
lir->operands[0] = delta;
break;
@@ -1423,9 +1423,7 @@
LIR* x86LIR;
int offset = 0;
- for (x86LIR = (LIR *) cUnit->firstLIRInsn;
- x86LIR;
- x86LIR = NEXT_LIR(x86LIR)) {
+ for (x86LIR = cUnit->firstLIRInsn; x86LIR; x86LIR = NEXT_LIR(x86LIR)) {
x86LIR->offset = offset;
if (x86LIR->opcode >= 0) {
if (!x86LIR->flags.isNop) {
diff --git a/src/compiler/codegen/x86/call_x86.cc b/src/compiler/codegen/x86/call_x86.cc
index 2b52270..c2b456f 100644
--- a/src/compiler/codegen/x86/call_x86.cc
+++ b/src/compiler/codegen/x86/call_x86.cc
@@ -38,8 +38,8 @@
dumpSparseSwitchTable(table);
}
int entries = table[1];
- int* keys = (int*)&table[2];
- int* targets = &keys[entries];
+ const int* keys = reinterpret_cast<const int*>(&table[2]);
+ const int* targets = &keys[entries];
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
for (int i = 0; i < entries; i++) {
int key = keys[i];
@@ -76,14 +76,13 @@
dumpPackedSwitchTable(table);
}
// Add the table to the list - we'll process it later
- SwitchTable *tabRec = (SwitchTable *)oatNew(cUnit, sizeof(SwitchTable),
- true, kAllocData);
+ SwitchTable *tabRec =
+ static_cast<SwitchTable *>(oatNew(cUnit, sizeof(SwitchTable), true, kAllocData));
tabRec->table = table;
tabRec->vaddr = cUnit->currentDalvikOffset;
int size = table[1];
- tabRec->targets = (LIR* *)oatNew(cUnit, size * sizeof(LIR*), true,
- kAllocLIR);
- oatInsertGrowableList(cUnit, &cUnit->switchTables, (intptr_t)tabRec);
+ tabRec->targets = static_cast<LIR**>(oatNew(cUnit, size * sizeof(LIR*), true, kAllocLIR));
+ oatInsertGrowableList(cUnit, &cUnit->switchTables, reinterpret_cast<uintptr_t>(tabRec));
// Get the switch value
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
@@ -107,7 +106,7 @@
// Load the displacement from the switch table
int dispReg = oatAllocTemp(cUnit);
newLIR5(cUnit, kX86PcRelLoadRA, dispReg, startOfMethodReg, keyReg, 2,
- (intptr_t)tabRec);
+ reinterpret_cast<uintptr_t>(tabRec));
// Add displacement to start of method
opRegReg(cUnit, kOpAdd, startOfMethodReg, dispReg);
// ..and go!
@@ -116,7 +115,7 @@
/* branchOver target here */
LIR* target = newLIR0(cUnit, kPseudoTargetLabel);
- branchOver->target = (LIR*)target;
+ branchOver->target = target;
}
void callRuntimeHelperRegReg(CompilationUnit* cUnit, int helperOffset,
@@ -136,25 +135,25 @@
{
const uint16_t* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
// Add the table to the list - we'll process it later
- FillArrayData *tabRec = (FillArrayData *)oatNew(cUnit, sizeof(FillArrayData),
- true, kAllocData);
+ FillArrayData *tabRec =
+ static_cast<FillArrayData*>(oatNew(cUnit, sizeof(FillArrayData), true, kAllocData));
tabRec->table = table;
tabRec->vaddr = cUnit->currentDalvikOffset;
uint16_t width = tabRec->table[1];
uint32_t size = tabRec->table[2] | ((static_cast<uint32_t>(tabRec->table[3])) << 16);
tabRec->size = (size * width) + 8;
- oatInsertGrowableList(cUnit, &cUnit->fillArrayData, (intptr_t)tabRec);
+ oatInsertGrowableList(cUnit, &cUnit->fillArrayData, reinterpret_cast<uintptr_t>(tabRec));
// Making a call - use explicit registers
oatFlushAllRegs(cUnit); /* Everything to home location */
loadValueDirectFixed(cUnit, rlSrc, rX86_ARG0);
// Materialize a pointer to the fill data image
newLIR1(cUnit, kX86StartOfMethod, rX86_ARG2);
- newLIR2(cUnit, kX86PcRelAdr, rX86_ARG1, (intptr_t)tabRec);
+ newLIR2(cUnit, kX86PcRelAdr, rX86_ARG1, reinterpret_cast<uintptr_t>(tabRec));
newLIR2(cUnit, kX86Add32RR, rX86_ARG1, rX86_ARG2);
- callRuntimeHelperRegReg(cUnit, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode), rX86_ARG0, rX86_ARG1,
- true);
+ callRuntimeHelperRegReg(cUnit, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode), rX86_ARG0,
+ rX86_ARG1, true);
}
void genMonitorEnter(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
@@ -209,7 +208,7 @@
storeBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
kUnsignedByte);
LIR* target = newLIR0(cUnit, kPseudoTargetLabel);
- branchOver->target = (LIR*)target;
+ branchOver->target = target;
oatFreeTemp(cUnit, regCardBase);
oatFreeTemp(cUnit, regCardNo);
}
@@ -235,7 +234,7 @@
* a leaf *and* our frame size < fudge factor.
*/
bool skipOverflowCheck = ((cUnit->attrs & METHOD_IS_LEAF) &&
- ((size_t)cUnit->frameSize <
+ (static_cast<size_t>(cUnit->frameSize) <
Thread::kStackOverflowReservedBytes));
newLIR0(cUnit, kPseudoMethodEntry);
/* Spill core callee saves */
@@ -248,7 +247,7 @@
opRegThreadMem(cUnit, kOpCmp, rX86_SP, Thread::StackEndOffset().Int32Value());
opCondBranch(cUnit, kCondUlt, tgt);
// Remember branch target - will process later
- oatInsertGrowableList(cUnit, &cUnit->throwLaunchpads, (intptr_t)tgt);
+ oatInsertGrowableList(cUnit, &cUnit->throwLaunchpads, reinterpret_cast<uintptr_t>(tgt));
}
flushIns(cUnit, argLocs, rlMethod);
diff --git a/src/compiler/codegen/x86/fp_x86.cc b/src/compiler/codegen/x86/fp_x86.cc
index 411bd1e..37e9168 100644
--- a/src/compiler/codegen/x86/fp_x86.cc
+++ b/src/compiler/codegen/x86/fp_x86.cc
@@ -324,7 +324,7 @@
ccode = kCondCc;
break;
default:
- LOG(FATAL) << "Unexpected ccode: " << (int)ccode;
+ LOG(FATAL) << "Unexpected ccode: " << ccode;
}
opCondBranch(cUnit, ccode, taken);
}
diff --git a/src/compiler/codegen/x86/int_x86.cc b/src/compiler/codegen/x86/int_x86.cc
index 1673b55..bcb51c4 100644
--- a/src/compiler/codegen/x86/int_x86.cc
+++ b/src/compiler/codegen/x86/int_x86.cc
@@ -29,7 +29,7 @@
opRegMem(cUnit, kOpCmp, reg1, base, offset);
LIR* branch = opCondBranch(cUnit, cCode, tgt);
// Remember branch target - will process later
- oatInsertGrowableList(cUnit, &cUnit->throwLaunchpads, (intptr_t)tgt);
+ oatInsertGrowableList(cUnit, &cUnit->throwLaunchpads, reinterpret_cast<uintptr_t>(tgt));
return branch;
}
@@ -208,7 +208,7 @@
case kCondGe:
break;
default:
- LOG(FATAL) << "Unexpected ccode: " << (int)ccode;
+ LOG(FATAL) << "Unexpected ccode: " << ccode;
}
opCondBranch(cUnit, ccode, taken);
}
diff --git a/src/compiler/codegen/x86/target_x86.cc b/src/compiler/codegen/x86/target_x86.cc
index a254876..b6440a7 100644
--- a/src/compiler/codegen/x86/target_x86.cc
+++ b/src/compiler/codegen/x86/target_x86.cc
@@ -281,11 +281,10 @@
return buf;
}
-void oatDumpResourceMask(LIR *lir, uint64_t mask, const char *prefix)
+void oatDumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix)
{
char buf[256];
buf[0] = 0;
- LIR *x86LIR = (LIR *) lir;
if (mask == ENCODE_ALL) {
strcpy(buf, "all");
@@ -437,12 +436,6 @@
oatFreeTemp(cUnit, rX86_ARG3);
}
-/* Convert an instruction to a NOP */
-void oatNopLIR( LIR* lir)
-{
- ((LIR*)lir)->flags.isNop = true;
-}
-
/*
* Determine the initial instruction set to be used for this trace.
* Later components may decide to change this.
@@ -502,17 +495,17 @@
int numTemps = sizeof(coreTemps)/sizeof(*coreTemps);
int numFPRegs = sizeof(fpRegs)/sizeof(*fpRegs);
int numFPTemps = sizeof(fpTemps)/sizeof(*fpTemps);
- RegisterPool *pool = (RegisterPool *)oatNew(cUnit, sizeof(*pool), true,
- kAllocRegAlloc);
+ RegisterPool *pool =
+ static_cast<RegisterPool*>(oatNew(cUnit, sizeof(*pool), true, kAllocRegAlloc));
cUnit->regPool = pool;
pool->numCoreRegs = numRegs;
- pool->coreRegs = (RegisterInfo *)
- oatNew(cUnit, numRegs * sizeof(*cUnit->regPool->coreRegs), true,
- kAllocRegAlloc);
+ pool->coreRegs =
+ static_cast<RegisterInfo*>(oatNew(cUnit, numRegs * sizeof(*cUnit->regPool->coreRegs),
+ true, kAllocRegAlloc));
pool->numFPRegs = numFPRegs;
- pool->FPRegs = (RegisterInfo *)
- oatNew(cUnit, numFPRegs * sizeof(*cUnit->regPool->FPRegs), true,
- kAllocRegAlloc);
+ pool->FPRegs =
+ static_cast<RegisterInfo *>(oatNew(cUnit, numFPRegs * sizeof(*cUnit->regPool->FPRegs),
+ true, kAllocRegAlloc));
oatInitPool(pool->coreRegs, coreRegs, pool->numCoreRegs);
oatInitPool(pool->FPRegs, fpRegs, pool->numFPRegs);
// Keep special registers from being allocated
@@ -527,9 +520,8 @@
oatMarkTemp(cUnit, fpTemps[i]);
}
// Construct the alias map.
- cUnit->phiAliasMap = (int*)oatNew(cUnit, cUnit->numSSARegs *
- sizeof(cUnit->phiAliasMap[0]), false,
- kAllocDFInfo);
+ cUnit->phiAliasMap = static_cast<int*>
+ (oatNew(cUnit, cUnit->numSSARegs * sizeof(cUnit->phiAliasMap[0]), false, kAllocDFInfo));
for (int i = 0; i < cUnit->numSSARegs; i++) {
cUnit->phiAliasMap[i] = i;
}
@@ -586,44 +578,9 @@
}
}
-/*
- * Nop any unconditional branches that go to the next instruction.
- * Note: new redundant branches may be inserted later, and we'll
- * use a check in final instruction assembly to nop those out.
- */
-void removeRedundantBranches(CompilationUnit* cUnit) {
- LIR* thisLIR;
-
- for (thisLIR = (LIR*) cUnit->firstLIRInsn;
- thisLIR != (LIR*) cUnit->lastLIRInsn;
- thisLIR = NEXT_LIR(thisLIR)) {
-
- /* Branch to the next instruction */
- if (thisLIR->opcode == kX86Jmp8 || thisLIR->opcode == kX86Jmp32) {
- LIR* nextLIR = thisLIR;
-
- while (true) {
- nextLIR = NEXT_LIR(nextLIR);
-
- /*
- * Is the branch target the next instruction?
- */
- if (nextLIR == (LIR*) thisLIR->target) {
- thisLIR->flags.isNop = true;
- break;
- }
-
- /*
- * Found real useful stuff between the branch and the target.
- * Need to explicitly check the lastLIRInsn here because it
- * might be the last real instruction.
- */
- if (!isPseudoOpcode(nextLIR->opcode) ||
- (nextLIR = (LIR*) cUnit->lastLIRInsn))
- break;
- }
- }
- }
+bool branchUnconditional(LIR* lir)
+{
+ return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32);
}
/* Common initialization routine for an architecture family */
@@ -634,7 +591,7 @@
if (EncodingMap[i].opcode != i) {
LOG(FATAL) << "Encoding order for " << EncodingMap[i].name
<< " is wrong: expecting " << i << ", seeing "
- << (int)EncodingMap[i].opcode;
+ << static_cast<int>(EncodingMap[i].opcode);
}
}
diff --git a/src/compiler/codegen/x86/x86_lir.h b/src/compiler/codegen/x86/x86_lir.h
index 3008bc2..9f29d08 100644
--- a/src/compiler/codegen/x86/x86_lir.h
+++ b/src/compiler/codegen/x86/x86_lir.h
@@ -220,7 +220,7 @@
#define rX86_COUNT rCX
#define rX86_PC INVALID_REG
-#define isPseudoOpcode(opCode) ((int)(opCode) < 0)
+#define isPseudoOpcode(opCode) (static_cast<int>(opCode) < 0)
/*
* The following enum defines the list of supported X86 instructions by the