commit df62950e7a32031b82360c407d46a37b94188fbb
author Brian Carlstrom <bdc@google.com> Wed Jul 17 22:39:56 2013 -0700
committer Brian Carlstrom <bdc@google.com> Thu Jul 18 00:13:18 2013 -0700
tree 038bf95a2ce296ae3e0c30a131ac22c0986f0f52
parent 0cd7ec2dcd8d7ba30bf3ca420b40dac52849876c

Fix cpplint whitespace/parens issues

Change-Id: Ifc678d59a8bed24ffddde5a0e543620b17b0aba9

compiler/dex/quick/arm/int_arm.cc

diff --git a/compiler/dex/quick/arm/int_arm.cc b/compiler/dex/quick/arm/int_arm.cc
index e12df6c..3a367c9 100644
--- a/compiler/dex/quick/arm/int_arm.cc
+++ b/compiler/dex/quick/arm/int_arm.cc
@@ -129,7 +129,7 @@
   int32_t low_reg = rl_src1.low_reg;
   int32_t high_reg = rl_src1.high_reg;
 
-  switch(ccode) {
+  switch (ccode) {
     case kCondEq:
     case kCondNe:
       LIR* target;
@@ -270,7 +270,7 @@
   rl_src1 = LoadValueWide(rl_src1, kCoreReg);
   rl_src2 = LoadValueWide(rl_src2, kCoreReg);
   OpRegReg(kOpCmp, rl_src1.high_reg, rl_src2.high_reg);
-  switch(ccode) {
+  switch (ccode) {
     case kCondEq:
       OpCondBranch(kCondNe, not_taken);
       break;
@@ -436,7 +436,7 @@
   int r_hi = AllocTemp();
   int r_lo = AllocTemp();
   NewLIR4(kThumb2Smull, r_lo, r_hi, r_magic, rl_src.low_reg);
-  switch(pattern) {
+  switch (pattern) {
     case Divide3:
       OpRegRegRegShift(kOpSub, rl_result.low_reg, r_hi,
                rl_src.low_reg, EncodeShift(kArmAsr, 31));
@@ -1002,7 +1002,7 @@
     return;
   }
   RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
-  switch(opcode) {
+  switch (opcode) {
     case Instruction::SHL_LONG:
     case Instruction::SHL_LONG_2ADDR:
       if (shift_amount == 1) {
@@ -1090,7 +1090,7 @@
   int32_t mod_imm_hi = ModifiedImmediate(val_hi);
 
   // Only a subset of add/sub immediate instructions set carry - so bail if we don't fit
-  switch(opcode) {
+  switch (opcode) {
     case Instruction::ADD_LONG:
     case Instruction::ADD_LONG_2ADDR:
     case Instruction::SUB_LONG: