Mark top of managed stack on helper transitions

To assist with unwind from a helper function, store current SP prior
to helper call in Thread.  NOTE: we may wish to push this into a
trampoline to reduce code expansion.  NOTE #2:  Because any helper
function which can throw will be non-leaf, it will spill lr at the saved
address - 4 (the word immediately below caller's Method*).  To identify
the callsite, load the spilled lr, clear the low bit, subtract 2, and use
that address in the native <-> dalvik mapping to identify the callsite.

Also in this CL are a ralloc fix and some extra SSA logging.

Change-Id: Idd442f0c55413a5146c24709b1db1150604f4554
diff --git a/src/compiler/codegen/arm/ArchFactory.cc b/src/compiler/codegen/arm/ArchFactory.cc
index 66eaf54..34a333d 100644
--- a/src/compiler/codegen/arm/ArchFactory.cc
+++ b/src/compiler/codegen/arm/ArchFactory.cc
@@ -62,7 +62,7 @@
     if (cCode == kArmCondAl) {
         branch = genUnconditionalBranch(cUnit, tgt);
     } else {
-        branch = genCmpImmBranch(cUnit, kArmCondEq, reg, 0);
+        branch = genCmpImmBranch(cUnit, cCode, reg, immVal);
         branch->generic.target = (LIR*)tgt;
     }
     // Remember branch target - will process later
@@ -86,18 +86,18 @@
     return genImmedCheck(cUnit, kArmCondEq, mReg, 0, mir, kArmThrowNullPointer);
 }
 
-/* Perform bound check on two registers */
-static TGT_LIR* genBoundsCheck(CompilationUnit* cUnit, int rIndex,
-                               int rBound, MIR* mir, ArmThrowKind kind)
+/* Perform check on two registers */
+static TGT_LIR* genRegRegCheck(CompilationUnit* cUnit, ArmConditionCode cCode,
+                               int reg1, int reg2, MIR* mir, ArmThrowKind kind)
 {
     ArmLIR* tgt = (ArmLIR*)oatNew(sizeof(ArmLIR), true);
     tgt->opcode = kArmPseudoThrowTarget;
     tgt->operands[0] = kind;
-    tgt->operands[1] = mir->offset;
-    tgt->operands[2] = rIndex;
-    tgt->operands[3] = rBound;
-    opRegReg(cUnit, kOpCmp, rIndex, rBound);
-    ArmLIR* branch = genConditionalBranch(cUnit, kArmCondCs, tgt);
+    tgt->operands[1] = mir ? mir->offset : 0;
+    tgt->operands[2] = reg1;
+    tgt->operands[3] = reg2;
+    opRegReg(cUnit, kOpCmp, reg1, reg2);
+    ArmLIR* branch = genConditionalBranch(cUnit, cCode, tgt);
     // Remember branch target - will process later
     oatInsertGrowableList(&cUnit->throwLaunchpads, (intptr_t)tgt);
     return branch;