Quick backend: rename target-specific #defines
Another step towards a single compiler. The #include build mechanism
relies on macros with the same name to take on different values for
our various targets. This CL prepends a target-specific string
(and exposes some needed by common code as functions rather than #defines).
Macros and #defines still available for use from target-dependent code,
but functions added for target independent use. For example,
rRET0 for Arm becomes rARM_RET0 in target-dependent code, and
targetRegister(kRet0) in target-independent code.
No logic changes, other than adding functions to return previously #defined
values. As of this CL, the primary target includes, xxxLIR.h, have no
macro collisions.
Change-Id: I5e11df844815b7d129b525a209dd7c46bd9a4a09
diff --git a/src/compiler/codegen/arm/Thumb2/Factory.cc b/src/compiler/codegen/arm/Thumb2/Factory.cc
index c373e35..fc3aaa0 100644
--- a/src/compiler/codegen/arm/Thumb2/Factory.cc
+++ b/src/compiler/codegen/arm/Thumb2/Factory.cc
@@ -18,9 +18,9 @@
/* This file contains codegen for the Thumb ISA. */
-static int coreRegs[] = {r0, r1, r2, r3, rSUSPEND, r5, r6, r7, r8, rSELF, r10,
- r11, r12, rSP, rLR, rPC};
-static int reservedRegs[] = {rSUSPEND, rSELF, rSP, rLR, rPC};
+static int coreRegs[] = {r0, r1, r2, r3, rARM_SUSPEND, r5, r6, r7, r8, rARM_SELF, r10,
+ r11, r12, rARM_SP, rARM_LR, rARM_PC};
+static int reservedRegs[] = {rARM_SUSPEND, rARM_SELF, rARM_SP, rARM_LR, rARM_PC};
static int fpRegs[] = {fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
@@ -54,7 +54,7 @@
LIR* loadFPConstantValue(CompilationUnit* cUnit, int rDest, int value)
{
int encodedImm = encodeImmSingle(value);
- DCHECK(SINGLEREG(rDest));
+ DCHECK(ARM_SINGLEREG(rDest));
if (encodedImm >= 0) {
return newLIR2(cUnit, kThumb2Vmovs_IMM8, rDest, encodedImm);
}
@@ -136,12 +136,12 @@
LIR* res;
int modImm;
- if (FPREG(rDest)) {
+ if (ARM_FPREG(rDest)) {
return loadFPConstantValue(cUnit, rDest, value);
}
/* See if the value can be constructed cheaply */
- if (LOWREG(rDest) && (value >= 0) && (value <= 255)) {
+ if (ARM_LOWREG(rDest) && (value >= 0) && (value <= 255)) {
return newLIR2(cUnit, kThumbMovImm, rDest, value);
}
/* Check Modified immediate special cases */
@@ -212,7 +212,7 @@
LIR* opRegRegShift(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
int rSrc2, int shift)
{
- bool thumbForm = ((shift == 0) && LOWREG(rDestSrc1) && LOWREG(rSrc2));
+ bool thumbForm = ((shift == 0) && ARM_LOWREG(rDestSrc1) && ARM_LOWREG(rSrc2));
ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpAdc:
@@ -231,9 +231,9 @@
case kOpCmp:
if (thumbForm)
opcode = kThumbCmpRR;
- else if ((shift == 0) && !LOWREG(rDestSrc1) && !LOWREG(rSrc2))
+ else if ((shift == 0) && !ARM_LOWREG(rDestSrc1) && !ARM_LOWREG(rSrc2))
opcode = kThumbCmpHH;
- else if ((shift == 0) && LOWREG(rDestSrc1))
+ else if ((shift == 0) && ARM_LOWREG(rDestSrc1))
opcode = kThumbCmpLH;
else if (shift == 0)
opcode = kThumbCmpHL;
@@ -245,11 +245,11 @@
break;
case kOpMov:
DCHECK_EQ(shift, 0);
- if (LOWREG(rDestSrc1) && LOWREG(rSrc2))
+ if (ARM_LOWREG(rDestSrc1) && ARM_LOWREG(rSrc2))
opcode = kThumbMovRR;
- else if (!LOWREG(rDestSrc1) && !LOWREG(rSrc2))
+ else if (!ARM_LOWREG(rDestSrc1) && !ARM_LOWREG(rSrc2))
opcode = kThumbMovRR_H2H;
- else if (LOWREG(rDestSrc1))
+ else if (ARM_LOWREG(rDestSrc1))
opcode = kThumbMovRR_H2L;
else
opcode = kThumbMovRR_L2H;
@@ -334,8 +334,8 @@
int rSrc2, int shift)
{
ArmOpcode opcode = kThumbBkpt;
- bool thumbForm = (shift == 0) && LOWREG(rDest) && LOWREG(rSrc1) &&
- LOWREG(rSrc2);
+ bool thumbForm = (shift == 0) && ARM_LOWREG(rDest) && ARM_LOWREG(rSrc1) &&
+ ARM_LOWREG(rSrc2);
switch (op) {
case kOpAdd:
opcode = (thumbForm) ? kThumbAddRRR : kThumb2AddRRR;
@@ -411,7 +411,7 @@
int absValue = (neg) ? -value : value;
ArmOpcode opcode = kThumbBkpt;
ArmOpcode altOpcode = kThumbBkpt;
- bool allLowRegs = (LOWREG(rDest) && LOWREG(rSrc1));
+ bool allLowRegs = (ARM_LOWREG(rDest) && ARM_LOWREG(rSrc1));
int modImm = modifiedImmediate(value);
int modImmNeg = modifiedImmediate(-value);
@@ -434,10 +434,10 @@
case kOpRor:
return newLIR3(cUnit, kThumb2RorRRI5, rDest, rSrc1, value);
case kOpAdd:
- if (LOWREG(rDest) && (rSrc1 == r13sp) &&
+ if (ARM_LOWREG(rDest) && (rSrc1 == r13sp) &&
(value <= 1020) && ((value & 0x3)==0)) {
return newLIR3(cUnit, kThumbAddSpRel, rDest, rSrc1, value >> 2);
- } else if (LOWREG(rDest) && (rSrc1 == r15pc) &&
+ } else if (ARM_LOWREG(rDest) && (rSrc1 == r15pc) &&
(value <= 1020) && ((value & 0x3)==0)) {
return newLIR3(cUnit, kThumbAddPcRel, rDest, rSrc1, value >> 2);
}
@@ -529,7 +529,7 @@
{
bool neg = (value < 0);
int absValue = (neg) ? -value : value;
- bool shortForm = (((absValue & 0xff) == absValue) && LOWREG(rDestSrc1));
+ bool shortForm = (((absValue & 0xff) == absValue) && ARM_LOWREG(rDestSrc1));
ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpAdd:
@@ -549,9 +549,9 @@
}
break;
case kOpCmp:
- if (LOWREG(rDestSrc1) && shortForm)
+ if (ARM_LOWREG(rDestSrc1) && shortForm)
opcode = (shortForm) ? kThumbCmpRI8 : kThumbCmpRR;
- else if (LOWREG(rDestSrc1))
+ else if (ARM_LOWREG(rDestSrc1))
opcode = kThumbCmpRR;
else {
shortForm = false;
@@ -609,9 +609,9 @@
{
int encodedImm = encodeImmDouble(valLo, valHi);
LIR* res;
- if (FPREG(rDestLo)) {
+ if (ARM_FPREG(rDestLo)) {
if (encodedImm >= 0) {
- res = newLIR2(cUnit, kThumb2Vmovd_IMM8, S2D(rDestLo, rDestHi),
+ res = newLIR2(cUnit, kThumb2Vmovd_IMM8, s2d(rDestLo, rDestHi),
encodedImm);
} else {
LIR* dataTarget = scanLiteralPoolWide(cUnit->literalList, valLo, valHi);
@@ -620,7 +620,7 @@
}
LIR* loadPcRel =
rawLIR(cUnit, cUnit->currentDalvikOffset, kThumb2Vldrd,
- S2D(rDestLo, rDestHi), r15pc, 0, 0, 0, dataTarget);
+ s2d(rDestLo, rDestHi), r15pc, 0, 0, 0, dataTarget);
setMemRefType(loadPcRel, true, kLiteral);
loadPcRel->aliasInfo = (intptr_t)dataTarget;
oatAppendLIR(cUnit, (LIR* ) loadPcRel);
@@ -640,19 +640,19 @@
LIR* loadBaseIndexed(CompilationUnit* cUnit, int rBase, int rIndex, int rDest,
int scale, OpSize size)
{
- bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rDest);
+ bool allLowRegs = ARM_LOWREG(rBase) && ARM_LOWREG(rIndex) && ARM_LOWREG(rDest);
LIR* load;
ArmOpcode opcode = kThumbBkpt;
bool thumbForm = (allLowRegs && (scale == 0));
int regPtr;
- if (FPREG(rDest)) {
- if (SINGLEREG(rDest)) {
+ if (ARM_FPREG(rDest)) {
+ if (ARM_SINGLEREG(rDest)) {
DCHECK((size == kWord) || (size == kSingle));
opcode = kThumb2Vldrs;
size = kSingle;
} else {
- DCHECK(DOUBLEREG(rDest));
+ DCHECK(ARM_DOUBLEREG(rDest));
DCHECK((size == kLong) || (size == kDouble));
DCHECK_EQ((rDest & 0x1), 0);
opcode = kThumb2Vldrd;
@@ -705,19 +705,19 @@
LIR* storeBaseIndexed(CompilationUnit* cUnit, int rBase, int rIndex, int rSrc,
int scale, OpSize size)
{
- bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rSrc);
+ bool allLowRegs = ARM_LOWREG(rBase) && ARM_LOWREG(rIndex) && ARM_LOWREG(rSrc);
LIR* store;
ArmOpcode opcode = kThumbBkpt;
bool thumbForm = (allLowRegs && (scale == 0));
int regPtr;
- if (FPREG(rSrc)) {
- if (SINGLEREG(rSrc)) {
+ if (ARM_FPREG(rSrc)) {
+ if (ARM_SINGLEREG(rSrc)) {
DCHECK((size == kWord) || (size == kSingle));
opcode = kThumb2Vstrs;
size = kSingle;
} else {
- DCHECK(DOUBLEREG(rSrc));
+ DCHECK(ARM_DOUBLEREG(rSrc));
DCHECK((size == kLong) || (size == kDouble));
DCHECK_EQ((rSrc & 0x1), 0);
opcode = kThumb2Vstrd;
@@ -777,17 +777,17 @@
ArmOpcode opcode = kThumbBkpt;
bool shortForm = false;
bool thumb2Form = (displacement < 4092 && displacement >= 0);
- bool allLowRegs = (LOWREG(rBase) && LOWREG(rDest));
+ bool allLowRegs = (ARM_LOWREG(rBase) && ARM_LOWREG(rDest));
int encodedDisp = displacement;
bool is64bit = false;
switch (size) {
case kDouble:
case kLong:
is64bit = true;
- if (FPREG(rDest)) {
- if (SINGLEREG(rDest)) {
- DCHECK(FPREG(rDestHi));
- rDest = S2D(rDest, rDestHi);
+ if (ARM_FPREG(rDest)) {
+ if (ARM_SINGLEREG(rDest)) {
+ DCHECK(ARM_FPREG(rDestHi));
+ rDest = s2d(rDest, rDestHi);
}
opcode = kThumb2Vldrd;
if (displacement <= 1020) {
@@ -804,7 +804,7 @@
}
case kSingle:
case kWord:
- if (FPREG(rDest)) {
+ if (ARM_FPREG(rDest)) {
opcode = kThumb2Vldrs;
if (displacement <= 1020) {
shortForm = true;
@@ -812,12 +812,12 @@
}
break;
}
- if (LOWREG(rDest) && (rBase == r15pc) &&
+ if (ARM_LOWREG(rDest) && (rBase == r15pc) &&
(displacement <= 1020) && (displacement >= 0)) {
shortForm = true;
encodedDisp >>= 2;
opcode = kThumbLdrPcRel;
- } else if (LOWREG(rDest) && (rBase == r13sp) &&
+ } else if (ARM_LOWREG(rDest) && (rBase == r13sp) &&
(displacement <= 1020) && (displacement >= 0)) {
shortForm = true;
encodedDisp >>= 2;
@@ -878,7 +878,7 @@
}
// TODO: in future may need to differentiate Dalvik accesses w/ spills
- if (rBase == rSP) {
+ if (rBase == rARM_SP) {
annotateDalvikRegAccess(load, displacement >> 2, true /* isLoad */, is64bit);
}
return load;
@@ -906,21 +906,21 @@
ArmOpcode opcode = kThumbBkpt;
bool shortForm = false;
bool thumb2Form = (displacement < 4092 && displacement >= 0);
- bool allLowRegs = (LOWREG(rBase) && LOWREG(rSrc));
+ bool allLowRegs = (ARM_LOWREG(rBase) && ARM_LOWREG(rSrc));
int encodedDisp = displacement;
bool is64bit = false;
switch (size) {
case kLong:
case kDouble:
is64bit = true;
- if (!FPREG(rSrc)) {
+ if (!ARM_FPREG(rSrc)) {
res = storeBaseDispBody(cUnit, rBase, displacement, rSrc, -1, kWord);
storeBaseDispBody(cUnit, rBase, displacement + 4, rSrcHi, -1, kWord);
return res;
}
- if (SINGLEREG(rSrc)) {
- DCHECK(FPREG(rSrcHi));
- rSrc = S2D(rSrc, rSrcHi);
+ if (ARM_SINGLEREG(rSrc)) {
+ DCHECK(ARM_FPREG(rSrcHi));
+ rSrc = s2d(rSrc, rSrcHi);
}
opcode = kThumb2Vstrd;
if (displacement <= 1020) {
@@ -930,8 +930,8 @@
break;
case kSingle:
case kWord:
- if (FPREG(rSrc)) {
- DCHECK(SINGLEREG(rSrc));
+ if (ARM_FPREG(rSrc)) {
+ DCHECK(ARM_SINGLEREG(rSrc));
opcode = kThumb2Vstrs;
if (displacement <= 1020) {
shortForm = true;
@@ -984,7 +984,7 @@
}
// TODO: In future, may need to differentiate Dalvik & spill accesses
- if (rBase == rSP) {
+ if (rBase == rARM_SP) {
annotateDalvikRegAccess(store, displacement >> 2, false /* isLoad */,
is64bit);
}
@@ -1011,14 +1011,14 @@
LIR* fpRegCopy(CompilationUnit* cUnit, int rDest, int rSrc)
{
int opcode;
- DCHECK_EQ(DOUBLEREG(rDest), DOUBLEREG(rSrc));
- if (DOUBLEREG(rDest)) {
+ DCHECK_EQ(ARM_DOUBLEREG(rDest), ARM_DOUBLEREG(rSrc));
+ if (ARM_DOUBLEREG(rDest)) {
opcode = kThumb2Vmovd;
} else {
- if (SINGLEREG(rDest)) {
- opcode = SINGLEREG(rSrc) ? kThumb2Vmovs : kThumb2Fmsr;
+ if (ARM_SINGLEREG(rDest)) {
+ opcode = ARM_SINGLEREG(rSrc) ? kThumb2Vmovs : kThumb2Fmsr;
} else {
- DCHECK(SINGLEREG(rSrc));
+ DCHECK(ARM_SINGLEREG(rSrc));
opcode = kThumb2Fmrs;
}
}
diff --git a/src/compiler/codegen/arm/Thumb2/Gen.cc b/src/compiler/codegen/arm/Thumb2/Gen.cc
index cbe6b14..0a8e579 100644
--- a/src/compiler/codegen/arm/Thumb2/Gen.cc
+++ b/src/compiler/codegen/arm/Thumb2/Gen.cc
@@ -42,7 +42,7 @@
// Bad case - half in register, half in frame. Just punt
loc.location = kLocInvalid;
} else if (argNum < 2) {
- loc.lowReg = rARG1 + argNum;
+ loc.lowReg = rARM_ARG1 + argNum;
loc.highReg = loc.lowReg + 1;
loc.location = kLocPhysReg;
} else {
@@ -50,7 +50,7 @@
}
} else {
if (argNum < 3) {
- loc.lowReg = rARG1 + argNum;
+ loc.lowReg = rARM_ARG1 + argNum;
loc.location = kLocPhysReg;
} else {
loc.location = kLocDalvikFrame;
@@ -69,10 +69,10 @@
if (loc.location == kLocDalvikFrame) {
int start = (inPosition(cUnit, loc.sRegLow) + 1) * sizeof(uint32_t);
loc.lowReg = oatAllocTemp(cUnit);
- loadWordDisp(cUnit, rSP, start, loc.lowReg);
+ loadWordDisp(cUnit, rARM_SP, start, loc.lowReg);
if (loc.wide) {
loc.highReg = oatAllocTemp(cUnit);
- loadWordDisp(cUnit, rSP, start + sizeof(uint32_t), loc.highReg);
+ loadWordDisp(cUnit, rARM_SP, start + sizeof(uint32_t), loc.highReg);
}
loc.location = kLocPhysReg;
}
@@ -88,7 +88,7 @@
int vReg = SRegToVReg(cUnit, mir->ssaRep->uses[i]);
int inPosition = vReg - firstIn;
if (inPosition < numArgRegs) {
- oatLockTemp(cUnit, rARG1 + inPosition);
+ oatLockTemp(cUnit, rARM_ARG1 + inPosition);
}
}
}
@@ -239,7 +239,7 @@
break;
case kConstFunction:
genPrintLabel(cUnit, mir);
- loadConstant(cUnit, rRET0, mir->dalvikInsn.vB);
+ loadConstant(cUnit, rARM_RET0, mir->dalvikInsn.vB);
nextMir = getNextMir(cUnit, &bb, mir);
break;
case kIGet:
@@ -291,7 +291,7 @@
if (specialCase != kIdentity) {
genPrintLabel(cUnit, nextMir);
}
- newLIR1(cUnit, kThumbBx, rLR);
+ newLIR1(cUnit, kThumbBx, rARM_LR);
cUnit->coreSpillMask = 0;
cUnit->numCoreSpills = 0;
cUnit->fpSpillMask = 0;
@@ -356,14 +356,14 @@
* The test loop will look something like:
*
* adr rBase, <table>
- * ldr rVal, [rSP, vRegOff]
+ * ldr rVal, [rARM_SP, vRegOff]
* mov rIdx, #tableSize
* lp:
* ldmia rBase!, {rKey, rDisp}
* sub rIdx, #1
* cmp rVal, rKey
* ifeq
- * add rPC, rDisp ; This is the branch from which we compute displacement
+ * add rARM_PC, rDisp ; This is the branch from which we compute displacement
* cbnz rIdx, lp
*/
void genSparseSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
@@ -488,12 +488,12 @@
// Making a call - use explicit registers
oatFlushAllRegs(cUnit); /* Everything to home location */
loadValueDirectFixed(cUnit, rlSrc, r0);
- loadWordDisp(cUnit, rSELF, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode),
- rLR);
+ loadWordDisp(cUnit, rARM_SELF, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode),
+ rARM_LR);
// Materialize a pointer to the fill data image
newLIR3(cUnit, kThumb2Adr, r1, 0, (intptr_t)tabRec);
oatClobberCalleeSave(cUnit);
- LIR* callInst = opReg(cUnit, kOpBlx, rLR);
+ LIR* callInst = opReg(cUnit, kOpBlx, rARM_LR);
markSafepointPC(cUnit, callInst);
}
@@ -511,8 +511,8 @@
RegLocation rlResult;
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR2(cUnit, kThumb2Vnegd, S2D(rlResult.lowReg, rlResult.highReg),
- S2D(rlSrc.lowReg, rlSrc.highReg));
+ newLIR2(cUnit, kThumb2Vnegd, s2d(rlResult.lowReg, rlResult.highReg),
+ s2d(rlSrc.lowReg, rlSrc.highReg));
storeValueWide(cUnit, rlDest, rlResult);
}
@@ -549,7 +549,7 @@
loadValueDirectFixed(cUnit, rlSrc, r0); // Get obj
oatLockCallTemps(cUnit); // Prepare for explicit register usage
genNullCheck(cUnit, rlSrc.sRegLow, r0, optFlags);
- loadWordDisp(cUnit, rSELF, Thread::ThinLockIdOffset().Int32Value(), r2);
+ loadWordDisp(cUnit, rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), r2);
newLIR3(cUnit, kThumb2Ldrex, r1, r0,
Object::MonitorOffset().Int32Value() >> 2); // Get object->lock
// Align owner
@@ -564,9 +564,9 @@
opRegImm(cUnit, kOpCmp, r1, 0);
opIT(cUnit, kArmCondNe, "T");
// Go expensive route - artLockObjectFromCode(self, obj);
- loadWordDisp(cUnit, rSELF, ENTRYPOINT_OFFSET(pLockObjectFromCode), rLR);
+ loadWordDisp(cUnit, rARM_SELF, ENTRYPOINT_OFFSET(pLockObjectFromCode), rARM_LR);
oatClobberCalleeSave(cUnit);
- LIR* callInst = opReg(cUnit, kOpBlx, rLR);
+ LIR* callInst = opReg(cUnit, kOpBlx, rARM_LR);
markSafepointPC(cUnit, callInst);
oatGenMemBarrier(cUnit, kSY);
}
@@ -585,7 +585,7 @@
oatLockCallTemps(cUnit); // Prepare for explicit register usage
genNullCheck(cUnit, rlSrc.sRegLow, r0, optFlags);
loadWordDisp(cUnit, r0, Object::MonitorOffset().Int32Value(), r1); // Get lock
- loadWordDisp(cUnit, rSELF, Thread::ThinLockIdOffset().Int32Value(), r2);
+ loadWordDisp(cUnit, rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), r2);
// Is lock unheld on lock or held by us (==threadId) on unlock?
opRegRegImm(cUnit, kOpAnd, r3, r1,
(LW_HASH_STATE_MASK << LW_HASH_STATE_SHIFT));
@@ -596,9 +596,9 @@
opIT(cUnit, kArmCondEq, "EE");
storeWordDisp(cUnit, r0, Object::MonitorOffset().Int32Value(), r3);
// Go expensive route - UnlockObjectFromCode(obj);
- loadWordDisp(cUnit, rSELF, ENTRYPOINT_OFFSET(pUnlockObjectFromCode), rLR);
+ loadWordDisp(cUnit, rARM_SELF, ENTRYPOINT_OFFSET(pUnlockObjectFromCode), rARM_LR);
oatClobberCalleeSave(cUnit);
- LIR* callInst = opReg(cUnit, kOpBlx, rLR);
+ LIR* callInst = opReg(cUnit, kOpBlx, rARM_LR);
markSafepointPC(cUnit, callInst);
oatGenMemBarrier(cUnit, kSY);
}
@@ -643,7 +643,7 @@
target1 = newLIR0(cUnit, kPseudoTargetLabel);
- RegLocation rlTemp = LOC_C_RETURN; // Just using as template, will change
+ RegLocation rlTemp = locCReturn(); // Just using as template, will change
rlTemp.lowReg = tReg;
storeValue(cUnit, rlDest, rlTemp);
oatFreeTemp(cUnit, tReg);
@@ -708,13 +708,13 @@
LIR* branch;
int modImm;
ArmConditionCode armCond = oatArmConditionEncoding(cond);
- if ((LOWREG(reg)) && (checkValue == 0) &&
+ if ((ARM_LOWREG(reg)) && (checkValue == 0) &&
((armCond == kArmCondEq) || (armCond == kArmCondNe))) {
branch = newLIR2(cUnit, (armCond == kArmCondEq) ? kThumb2Cbz : kThumb2Cbnz,
reg, 0);
} else {
modImm = modifiedImmediate(checkValue);
- if (LOWREG(reg) && ((checkValue & 0xff) == checkValue)) {
+ if (ARM_LOWREG(reg) && ((checkValue & 0xff) == checkValue)) {
newLIR2(cUnit, kThumbCmpRI8, reg, checkValue);
} else if (modImm >= 0) {
newLIR2(cUnit, kThumb2CmpRI8, reg, modImm);
@@ -732,13 +732,13 @@
{
LIR* res;
int opcode;
- if (FPREG(rDest) || FPREG(rSrc))
+ if (ARM_FPREG(rDest) || ARM_FPREG(rSrc))
return fpRegCopy(cUnit, rDest, rSrc);
- if (LOWREG(rDest) && LOWREG(rSrc))
+ if (ARM_LOWREG(rDest) && ARM_LOWREG(rSrc))
opcode = kThumbMovRR;
- else if (!LOWREG(rDest) && !LOWREG(rSrc))
+ else if (!ARM_LOWREG(rDest) && !ARM_LOWREG(rSrc))
opcode = kThumbMovRR_H2H;
- else if (LOWREG(rDest))
+ else if (ARM_LOWREG(rDest))
opcode = kThumbMovRR_H2L;
else
opcode = kThumbMovRR_L2H;
@@ -759,19 +759,19 @@
void opRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
int srcLo, int srcHi)
{
- bool destFP = FPREG(destLo) && FPREG(destHi);
- bool srcFP = FPREG(srcLo) && FPREG(srcHi);
- DCHECK_EQ(FPREG(srcLo), FPREG(srcHi));
- DCHECK_EQ(FPREG(destLo), FPREG(destHi));
+ bool destFP = ARM_FPREG(destLo) && ARM_FPREG(destHi);
+ bool srcFP = ARM_FPREG(srcLo) && ARM_FPREG(srcHi);
+ DCHECK_EQ(ARM_FPREG(srcLo), ARM_FPREG(srcHi));
+ DCHECK_EQ(ARM_FPREG(destLo), ARM_FPREG(destHi));
if (destFP) {
if (srcFP) {
- opRegCopy(cUnit, S2D(destLo, destHi), S2D(srcLo, srcHi));
+ opRegCopy(cUnit, s2d(destLo, destHi), s2d(srcLo, srcHi));
} else {
- newLIR3(cUnit, kThumb2Fmdrr, S2D(destLo, destHi), srcLo, srcHi);
+ newLIR3(cUnit, kThumb2Fmdrr, s2d(destLo, destHi), srcLo, srcHi);
}
} else {
if (srcFP) {
- newLIR3(cUnit, kThumb2Fmrrd, destLo, destHi, S2D(srcLo, srcHi));
+ newLIR3(cUnit, kThumb2Fmrrd, destLo, destHi, s2d(srcLo, srcHi));
} else {
// Handle overlap
if (srcHi == destLo) {
@@ -872,7 +872,7 @@
int regCardBase = oatAllocTemp(cUnit);
int regCardNo = oatAllocTemp(cUnit);
LIR* branchOver = opCmpImmBranch(cUnit, kCondEq, valReg, 0, NULL);
- loadWordDisp(cUnit, rSELF, Thread::CardTableOffset().Int32Value(), regCardBase);
+ loadWordDisp(cUnit, rARM_SELF, Thread::CardTableOffset().Int32Value(), regCardBase);
opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, CardTable::kCardShift);
storeBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
kUnsignedByte);
@@ -994,18 +994,18 @@
RegLocation rlDest = inlineTargetWide(cUnit, info); // double place for result
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR2(cUnit, kThumb2Vsqrtd, S2D(rlResult.lowReg, rlResult.highReg),
- S2D(rlSrc.lowReg, rlSrc.highReg));
- newLIR2(cUnit, kThumb2Vcmpd, S2D(rlResult.lowReg, rlResult.highReg),
- S2D(rlResult.lowReg, rlResult.highReg));
+ newLIR2(cUnit, kThumb2Vsqrtd, s2d(rlResult.lowReg, rlResult.highReg),
+ s2d(rlSrc.lowReg, rlSrc.highReg));
+ newLIR2(cUnit, kThumb2Vcmpd, s2d(rlResult.lowReg, rlResult.highReg),
+ s2d(rlResult.lowReg, rlResult.highReg));
newLIR0(cUnit, kThumb2Fmstat);
branch = newLIR2(cUnit, kThumbBCond, 0, kArmCondEq);
oatClobberCalleeSave(cUnit);
oatLockCallTemps(cUnit); // Using fixed registers
int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pSqrt));
- newLIR3(cUnit, kThumb2Fmrrd, r0, r1, S2D(rlSrc.lowReg, rlSrc.highReg));
+ newLIR3(cUnit, kThumb2Fmrrd, r0, r1, s2d(rlSrc.lowReg, rlSrc.highReg));
newLIR1(cUnit, kThumbBlxR, rTgt);
- newLIR3(cUnit, kThumb2Fmdrr, S2D(rlResult.lowReg, rlResult.highReg), r0, r1);
+ newLIR3(cUnit, kThumb2Fmdrr, s2d(rlResult.lowReg, rlResult.highReg), r0, r1);
branch->target = newLIR0(cUnit, kPseudoTargetLabel);
storeValueWide(cUnit, rlDest, rlResult);
return true;
@@ -1048,7 +1048,7 @@
// Test suspend flag, return target of taken suspend branch
LIR* opTestSuspend(CompilationUnit* cUnit, LIR* target)
{
- newLIR2(cUnit, kThumbSubRI8, rSUSPEND, 1);
+ newLIR2(cUnit, kThumbSubRI8, rARM_SUSPEND, 1);
return opCondBranch(cUnit, (target == NULL) ? kCondEq : kCondNe, target);
}
diff --git a/src/compiler/codegen/arm/Thumb2/Ralloc.cc b/src/compiler/codegen/arm/Thumb2/Ralloc.cc
index 894488a..ab5cf33 100644
--- a/src/compiler/codegen/arm/Thumb2/Ralloc.cc
+++ b/src/compiler/codegen/arm/Thumb2/Ralloc.cc
@@ -68,7 +68,7 @@
oatInitPool(pool->FPRegs, fpRegs, pool->numFPRegs);
// Keep special registers from being allocated
for (int i = 0; i < numReserved; i++) {
- if (NO_SUSPEND && (reservedRegs[i] == rSUSPEND)) {
+ if (NO_SUSPEND && (reservedRegs[i] == rARM_SUSPEND)) {
//To measure cost of suspend check
continue;
}