diff --git a/src/compiler/CompilerIR.h b/src/compiler/CompilerIR.h
index 3f855bb..5de9c4e 100644
--- a/src/compiler/CompilerIR.h
+++ b/src/compiler/CompilerIR.h
@@ -44,6 +44,26 @@
   kAnyReg,
 };
 
+enum SpecialTargetRegister {
+  kSelf,            // Thread
+  kSuspend,         // Used to reduce suspend checks
+  kLr,
+  kPc,
+  kSp,
+  kArg0,
+  kArg1,
+  kArg2,
+  kArg3,
+  kFArg0,
+  kFArg1,
+  kFArg2,
+  kFArg3,
+  kRet0,
+  kRet1,
+  kInvokeTgt,
+  kCount
+};
+
 enum RegLocationType {
   kLocDalvikFrame = 0, // Normal Dalvik register
   kLocPhysReg,
diff --git a/src/compiler/codegen/CodegenFactory.cc b/src/compiler/codegen/CodegenFactory.cc
index b0dc30c..600b324 100644
--- a/src/compiler/codegen/CodegenFactory.cc
+++ b/src/compiler/codegen/CodegenFactory.cc
@@ -58,7 +58,7 @@
   } else {
     DCHECK((rlSrc.location == kLocDalvikFrame) ||
            (rlSrc.location == kLocCompilerTemp));
-    loadWordDisp(cUnit, rSP, oatSRegOffset(cUnit, rlSrc.sRegLow), rDest);
+    loadWordDisp(cUnit, targetReg(kSp), oatSRegOffset(cUnit, rlSrc.sRegLow), rDest);
   }
 }
 
@@ -88,7 +88,7 @@
   } else {
     DCHECK((rlSrc.location == kLocDalvikFrame) ||
            (rlSrc.location == kLocCompilerTemp));
-    loadBaseDispWide(cUnit, rSP, oatSRegOffset(cUnit, rlSrc.sRegLow),
+    loadBaseDispWide(cUnit, targetReg(kSp), oatSRegOffset(cUnit, rlSrc.sRegLow),
                      regLo, regHi, INVALID_SREG);
   }
 }
@@ -167,7 +167,7 @@
   if (oatIsDirty(cUnit, rlDest.lowReg) &&
       oatLiveOut(cUnit, rlDest.sRegLow)) {
     defStart = (LIR* )cUnit->lastLIRInsn;
-    storeBaseDisp(cUnit, rSP, oatSRegOffset(cUnit, rlDest.sRegLow),
+    storeBaseDisp(cUnit, targetReg(kSp), oatSRegOffset(cUnit, rlDest.sRegLow),
                   rlDest.lowReg, kWord);
     oatMarkClean(cUnit, rlDest);
     defEnd = (LIR* )cUnit->lastLIRInsn;
@@ -207,7 +207,7 @@
 #endif
   LIR* defStart;
   LIR* defEnd;
-  DCHECK_EQ(FPREG(rlSrc.lowReg), FPREG(rlSrc.highReg));
+  DCHECK_EQ(fpReg(rlSrc.lowReg), fpReg(rlSrc.highReg));
   DCHECK(rlDest.wide);
   DCHECK(rlSrc.wide);
   if (rlSrc.location == kLocPhysReg) {
@@ -248,7 +248,7 @@
     defStart = (LIR*)cUnit->lastLIRInsn;
     DCHECK_EQ((SRegToVReg(cUnit, rlDest.sRegLow)+1),
               SRegToVReg(cUnit, oatSRegHi(rlDest.sRegLow)));
-    storeBaseDispWide(cUnit, rSP, oatSRegOffset(cUnit, rlDest.sRegLow),
+    storeBaseDispWide(cUnit, targetReg(kSp), oatSRegOffset(cUnit, rlDest.sRegLow),
                       rlDest.lowReg, rlDest.highReg);
     oatMarkClean(cUnit, rlDest);
     defEnd = (LIR*)cUnit->lastLIRInsn;
diff --git a/src/compiler/codegen/CodegenUtil.cc b/src/compiler/codegen/CodegenUtil.cc
index 2450058..b0a1e44 100644
--- a/src/compiler/codegen/CodegenUtil.cc
+++ b/src/compiler/codegen/CodegenUtil.cc
@@ -258,7 +258,7 @@
     PromotionMap vRegMap = cUnit->promotionMap[i];
     std::string buf;
     if (vRegMap.fpLocation == kLocPhysReg) {
-      StringAppendF(&buf, " : s%d", vRegMap.fpReg & FP_REG_MASK);
+      StringAppendF(&buf, " : s%d", vRegMap.fpReg & fpRegMask());
     }
 
     std::string buf3;
diff --git a/src/compiler/codegen/CompilerCodegen.h b/src/compiler/codegen/CompilerCodegen.h
index 7584d2b..868e666 100644
--- a/src/compiler/codegen/CompilerCodegen.h
+++ b/src/compiler/codegen/CompilerCodegen.h
@@ -222,6 +222,17 @@
 LIR* opIT(CompilationUnit* cUnit, ArmConditionCode cond, const char* guide);
 uint64_t getPCUseDefEncoding();
 uint64_t getRegMaskCommon(CompilationUnit* cUnit, int reg);
+int s2d(int lowReg, int highReg);
+bool fpReg(int reg);
+bool singleReg(int reg);
+bool doubleReg(int reg);
+uint32_t fpRegMask();
+bool sameRegType(int reg1, int reg2);
+int targetReg(SpecialTargetRegister reg);
+RegLocation locCReturn();
+RegLocation locCReturnWide();
+RegLocation locCReturnFloat();
+RegLocation locCReturnDouble();
 
 }  // namespace art
 
diff --git a/src/compiler/codegen/GenCommon.cc b/src/compiler/codegen/GenCommon.cc
index 591e12c..bc61c54 100644
--- a/src/compiler/codegen/GenCommon.cc
+++ b/src/compiler/codegen/GenCommon.cc
@@ -63,14 +63,14 @@
 
 void callRuntimeHelperImm(CompilationUnit* cUnit, int helperOffset, int arg0, bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
-  loadConstant(cUnit, rARG0, arg0);
+  loadConstant(cUnit, targetReg(kArg0), arg0);
   oatClobberCalleeSave(cUnit);
   callHelper(cUnit, rTgt, helperOffset, safepointPC);
 }
 
 void callRuntimeHelperReg(CompilationUnit* cUnit, int helperOffset, int arg0, bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
-  opRegCopy(cUnit, rARG0, arg0);
+  opRegCopy(cUnit, targetReg(kArg0), arg0);
   oatClobberCalleeSave(cUnit);
   callHelper(cUnit, rTgt, helperOffset, safepointPC);
 }
@@ -79,9 +79,9 @@
                                   bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
   if (arg0.wide == 0) {
-    loadValueDirectFixed(cUnit, arg0, rARG0);
+    loadValueDirectFixed(cUnit, arg0, targetReg(kArg0));
   } else {
-    loadValueDirectWideFixed(cUnit, arg0, rARG0, rARG1);
+    loadValueDirectWideFixed(cUnit, arg0, targetReg(kArg0), targetReg(kArg1));
   }
   oatClobberCalleeSave(cUnit);
   callHelper(cUnit, rTgt, helperOffset, safepointPC);
@@ -90,8 +90,8 @@
 void callRuntimeHelperImmImm(CompilationUnit* cUnit, int helperOffset, int arg0, int arg1,
                              bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
-  loadConstant(cUnit, rARG0, arg0);
-  loadConstant(cUnit, rARG1, arg1);
+  loadConstant(cUnit, targetReg(kArg0), arg0);
+  loadConstant(cUnit, targetReg(kArg1), arg1);
   oatClobberCalleeSave(cUnit);
   callHelper(cUnit, rTgt, helperOffset, safepointPC);
 }
@@ -100,11 +100,11 @@
                                      RegLocation arg1, bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
   if (arg1.wide == 0) {
-    loadValueDirectFixed(cUnit, arg1, rARG1);
+    loadValueDirectFixed(cUnit, arg1, targetReg(kArg1));
   } else {
-    loadValueDirectWideFixed(cUnit, arg1, rARG1, rARG2);
+    loadValueDirectWideFixed(cUnit, arg1, targetReg(kArg1), targetReg(kArg2));
   }
-  loadConstant(cUnit, rARG0, arg0);
+  loadConstant(cUnit, targetReg(kArg0), arg0);
   oatClobberCalleeSave(cUnit);
   callHelper(cUnit, rTgt, helperOffset, safepointPC);
 }
@@ -112,8 +112,8 @@
 void callRuntimeHelperRegLocationImm(CompilationUnit* cUnit, int helperOffset, RegLocation arg0,
                                      int arg1, bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
-  loadValueDirectFixed(cUnit, arg0, rARG0);
-  loadConstant(cUnit, rARG1, arg1);
+  loadValueDirectFixed(cUnit, arg0, targetReg(kArg0));
+  loadConstant(cUnit, targetReg(kArg1), arg1);
   oatClobberCalleeSave(cUnit);
   callHelper(cUnit, rTgt, helperOffset, safepointPC);
 }
@@ -121,8 +121,8 @@
 void callRuntimeHelperImmReg(CompilationUnit* cUnit, int helperOffset, int arg0, int arg1,
                              bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
-  opRegCopy(cUnit, rARG1, arg1);
-  loadConstant(cUnit, rARG0, arg0);
+  opRegCopy(cUnit, targetReg(kArg1), arg1);
+  loadConstant(cUnit, targetReg(kArg0), arg0);
   oatClobberCalleeSave(cUnit);
   callHelper(cUnit, rTgt, helperOffset, safepointPC);
 }
@@ -130,16 +130,16 @@
 void callRuntimeHelperRegImm(CompilationUnit* cUnit, int helperOffset, int arg0, int arg1,
                              bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
-  opRegCopy(cUnit, rARG0, arg0);
-  loadConstant(cUnit, rARG1, arg1);
+  opRegCopy(cUnit, targetReg(kArg0), arg0);
+  loadConstant(cUnit, targetReg(kArg1), arg1);
   oatClobberCalleeSave(cUnit);
   callHelper(cUnit, rTgt, helperOffset, safepointPC);
 }
 
 void callRuntimeHelperImmMethod(CompilationUnit* cUnit, int helperOffset, int arg0, bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
-  loadCurrMethodDirect(cUnit, rARG1);
-  loadConstant(cUnit, rARG0, arg0);
+  loadCurrMethodDirect(cUnit, targetReg(kArg1));
+  loadConstant(cUnit, targetReg(kArg0), arg0);
   oatClobberCalleeSave(cUnit);
   callHelper(cUnit, rTgt, helperOffset, safepointPC);
 }
@@ -148,26 +148,26 @@
                                              RegLocation arg0, RegLocation arg1, bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
   if (arg0.wide == 0) {
-    loadValueDirectFixed(cUnit, arg0, arg0.fp ? rFARG0 : rARG0);
+    loadValueDirectFixed(cUnit, arg0, arg0.fp ? targetReg(kFArg0) : targetReg(kArg0));
     if (arg1.wide == 0) {
       if (cUnit->instructionSet == kMips) {
-        loadValueDirectFixed(cUnit, arg1, arg1.fp ? rFARG2 : rARG1);
+        loadValueDirectFixed(cUnit, arg1, arg1.fp ? targetReg(kFArg2) : targetReg(kArg1));
       } else {
-        loadValueDirectFixed(cUnit, arg1, rARG1);
+        loadValueDirectFixed(cUnit, arg1, targetReg(kArg1));
       }
     } else {
       if (cUnit->instructionSet == kMips) {
-        loadValueDirectWideFixed(cUnit, arg1, arg1.fp ? rFARG2 : rARG1, arg1.fp ? rFARG3 : rARG2);
+        loadValueDirectWideFixed(cUnit, arg1, arg1.fp ? targetReg(kFArg2) : targetReg(kArg1), arg1.fp ? targetReg(kFArg3) : targetReg(kArg2));
       } else {
-        loadValueDirectWideFixed(cUnit, arg1, rARG1, rARG2);
+        loadValueDirectWideFixed(cUnit, arg1, targetReg(kArg1), targetReg(kArg2));
       }
     }
   } else {
-    loadValueDirectWideFixed(cUnit, arg0, arg0.fp ? rFARG0 : rARG0, arg0.fp ? rFARG1 : rARG1);
+    loadValueDirectWideFixed(cUnit, arg0, arg0.fp ? targetReg(kFArg0) : targetReg(kArg0), arg0.fp ? targetReg(kFArg1) : targetReg(kArg1));
     if (arg1.wide == 0) {
-      loadValueDirectFixed(cUnit, arg1, arg1.fp ? rFARG2 : rARG2);
+      loadValueDirectFixed(cUnit, arg1, arg1.fp ? targetReg(kFArg2) : targetReg(kArg2));
     } else {
-      loadValueDirectWideFixed(cUnit, arg1, arg1.fp ? rFARG2 : rARG2, arg1.fp ? rFARG3 : rARG3);
+      loadValueDirectWideFixed(cUnit, arg1, arg1.fp ? targetReg(kFArg2) : targetReg(kArg2), arg1.fp ? targetReg(kFArg3) : targetReg(kArg3));
     }
   }
   oatClobberCalleeSave(cUnit);
@@ -177,9 +177,9 @@
 void callRuntimeHelperRegReg(CompilationUnit* cUnit, int helperOffset, int arg0, int arg1,
                              bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
-  DCHECK_NE((int)rARG0, arg1);  // check copy into arg0 won't clobber arg1
-  opRegCopy(cUnit, rARG0, arg0);
-  opRegCopy(cUnit, rARG1, arg1);
+  DCHECK_NE((int)targetReg(kArg0), arg1);  // check copy into arg0 won't clobber arg1
+  opRegCopy(cUnit, targetReg(kArg0), arg0);
+  opRegCopy(cUnit, targetReg(kArg1), arg1);
   oatClobberCalleeSave(cUnit);
   callHelper(cUnit, rTgt, helperOffset, safepointPC);
 }
@@ -187,10 +187,10 @@
 void callRuntimeHelperRegRegImm(CompilationUnit* cUnit, int helperOffset, int arg0, int arg1,
                                 int arg2, bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
-  DCHECK_NE((int)rARG0, arg1);  // check copy into arg0 won't clobber arg1
-  opRegCopy(cUnit, rARG0, arg0);
-  opRegCopy(cUnit, rARG1, arg1);
-  loadConstant(cUnit, rARG2, arg2);
+  DCHECK_NE((int)targetReg(kArg0), arg1);  // check copy into arg0 won't clobber arg1
+  opRegCopy(cUnit, targetReg(kArg0), arg0);
+  opRegCopy(cUnit, targetReg(kArg1), arg1);
+  loadConstant(cUnit, targetReg(kArg2), arg2);
   oatClobberCalleeSave(cUnit);
   callHelper(cUnit, rTgt, helperOffset, safepointPC);
 }
@@ -198,9 +198,9 @@
 void callRuntimeHelperImmMethodRegLocation(CompilationUnit* cUnit, int helperOffset, int arg0,
                                            RegLocation arg2, bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
-  loadValueDirectFixed(cUnit, arg2, rARG2);
-  loadCurrMethodDirect(cUnit, rARG1);
-  loadConstant(cUnit, rARG0, arg0);
+  loadValueDirectFixed(cUnit, arg2, targetReg(kArg2));
+  loadCurrMethodDirect(cUnit, targetReg(kArg1));
+  loadConstant(cUnit, targetReg(kArg0), arg0);
   oatClobberCalleeSave(cUnit);
   callHelper(cUnit, rTgt, helperOffset, safepointPC);
 }
@@ -208,9 +208,9 @@
 void callRuntimeHelperImmMethodImm(CompilationUnit* cUnit, int helperOffset, int arg0, int arg2,
                                    bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
-  loadCurrMethodDirect(cUnit, rARG1);
-  loadConstant(cUnit, rARG2, arg2);
-  loadConstant(cUnit, rARG0, arg0);
+  loadCurrMethodDirect(cUnit, targetReg(kArg1));
+  loadConstant(cUnit, targetReg(kArg2), arg2);
+  loadConstant(cUnit, targetReg(kArg0), arg0);
   oatClobberCalleeSave(cUnit);
   callHelper(cUnit, rTgt, helperOffset, safepointPC);
 }
@@ -219,13 +219,13 @@
                                                 int arg0, RegLocation arg1, RegLocation arg2,
                                                 bool safepointPC) {
   int rTgt = callHelperSetup(cUnit, helperOffset);
-  loadValueDirectFixed(cUnit, arg1, rARG1);
+  loadValueDirectFixed(cUnit, arg1, targetReg(kArg1));
   if (arg2.wide == 0) {
-    loadValueDirectFixed(cUnit, arg2, rARG2);
+    loadValueDirectFixed(cUnit, arg2, targetReg(kArg2));
   } else {
-    loadValueDirectWideFixed(cUnit, arg2, rARG2, rARG3);
+    loadValueDirectWideFixed(cUnit, arg2, targetReg(kArg2), targetReg(kArg3));
   }
-  loadConstant(cUnit, rARG0, arg0);
+  loadConstant(cUnit, targetReg(kArg0), arg0);
   oatClobberCalleeSave(cUnit);
   callHelper(cUnit, rTgt, helperOffset, safepointPC);
 }
@@ -451,16 +451,16 @@
     funcOffset = ENTRYPOINT_OFFSET(pCheckAndAllocArrayFromCodeWithAccessCheck);
   }
   callRuntimeHelperImmMethodImm(cUnit, funcOffset, typeIdx, elems, true);
-  oatFreeTemp(cUnit, rARG2);
-  oatFreeTemp(cUnit, rARG1);
+  oatFreeTemp(cUnit, targetReg(kArg2));
+  oatFreeTemp(cUnit, targetReg(kArg1));
   /*
    * NOTE: the implicit target for Instruction::FILLED_NEW_ARRAY is the
    * return region.  Because AllocFromCode placed the new array
-   * in rRET0, we'll just lock it into place.  When debugger support is
+   * in kRet0, we'll just lock it into place.  When debugger support is
    * added, it may be necessary to additionally copy all return
    * values to a home location in thread-local storage
    */
-  oatLockTemp(cUnit, rRET0);
+  oatLockTemp(cUnit, targetReg(kRet0));
 
   // TODO: use the correct component size, currently all supported types
   // share array alignment with ints (see comment at head of function)
@@ -479,7 +479,7 @@
     for (int i = 0; i < elems; i++) {
       RegLocation loc = oatUpdateLoc(cUnit, info->args[i]);
       if (loc.location == kLocPhysReg) {
-        storeBaseDisp(cUnit, rSP, oatSRegOffset(cUnit, loc.sRegLow),
+        storeBaseDisp(cUnit, targetReg(kSp), oatSRegOffset(cUnit, loc.sRegLow),
                       loc.lowReg, kWord);
       }
     }
@@ -494,10 +494,10 @@
     int rVal = INVALID_REG;
     switch(cUnit->instructionSet) {
       case kThumb2:
-        rVal = rLR;
+        rVal = targetReg(kLr);
         break;
       case kX86:
-        oatFreeTemp(cUnit, rRET0);
+        oatFreeTemp(cUnit, targetReg(kRet0));
         rVal = oatAllocTemp(cUnit);
         break;
       case kMips:
@@ -507,10 +507,10 @@
     }
     // Set up source pointer
     RegLocation rlFirst = info->args[0];
-    opRegRegImm(cUnit, kOpAdd, rSrc, rSP,
+    opRegRegImm(cUnit, kOpAdd, rSrc, targetReg(kSp),
                 oatSRegOffset(cUnit, rlFirst.sRegLow));
     // Set up the target pointer
-    opRegRegImm(cUnit, kOpAdd, rDst, rRET0,
+    opRegRegImm(cUnit, kOpAdd, rDst, targetReg(kRet0),
                 Array::DataOffset(component_size).Int32Value());
     // Set up the loop counter (known to be > 0)
     loadConstant(cUnit, rIdx, elems - 1);
@@ -523,13 +523,13 @@
     opDecAndBranch(cUnit, kCondGe, rIdx, target);
     if (cUnit->instructionSet == kX86) {
       // Restore the target pointer
-      opRegRegImm(cUnit, kOpAdd, rRET0, rDst, -Array::DataOffset(component_size).Int32Value());
+      opRegRegImm(cUnit, kOpAdd, targetReg(kRet0), rDst, -Array::DataOffset(component_size).Int32Value());
     }
   } else if (!info->isRange) {
     // TUNING: interleave
     for (int i = 0; i < elems; i++) {
       RegLocation rlArg = loadValue(cUnit, info->args[i], kCoreReg);
-      storeBaseDisp(cUnit, rRET0,
+      storeBaseDisp(cUnit, targetReg(kRet0),
                     Array::DataOffset(component_size).Int32Value() +
                     i * 4, rlArg.lowReg, kWord);
       // If the loadValue caused a temp to be allocated, free it
@@ -579,10 +579,10 @@
       oatFlushAllRegs(cUnit);
       // Using fixed register to sync with possible call to runtime
       // support.
-      int rMethod = rARG1;
+      int rMethod = targetReg(kArg1);
       oatLockTemp(cUnit, rMethod);
       loadCurrMethodDirect(cUnit, rMethod);
-      rBase = rARG0;
+      rBase = targetReg(kArg0);
       oatLockTemp(cUnit, rBase);
       loadWordDisp(cUnit, rMethod,
                    AbstractMethod::DexCacheInitializedStaticStorageOffset().Int32Value(),
@@ -594,11 +594,11 @@
       // or NULL if not initialized. Check for NULL and call helper if NULL.
       // TUNING: fast path should fall through
       LIR* branchOver = opCmpImmBranch(cUnit, kCondNe, rBase, 0, NULL);
-      loadConstant(cUnit, rARG0, ssbIndex);
+      loadConstant(cUnit, targetReg(kArg0), ssbIndex);
       callRuntimeHelperImm(cUnit, ENTRYPOINT_OFFSET(pInitializeStaticStorage), ssbIndex, true);
       if (cUnit->instructionSet == kMips) {
-        // For Arm, rRET0 = rARG0 = rBASE, for Mips, we need to copy
-        opRegCopy(cUnit, rBase, rRET0);
+        // For Arm, kRet0 = kArg0 = rBase, for Mips, we need to copy
+        opRegCopy(cUnit, rBase, targetReg(kRet0));
       }
       LIR* skipTarget = newLIR0(cUnit, kPseudoTargetLabel);
       branchOver->target = (LIR*)skipTarget;
@@ -671,10 +671,10 @@
       oatFlushAllRegs(cUnit);
       // Using fixed register to sync with possible call to runtime
       // support
-      int rMethod = rARG1;
+      int rMethod = targetReg(kArg1);
       oatLockTemp(cUnit, rMethod);
       loadCurrMethodDirect(cUnit, rMethod);
-      rBase = rARG0;
+      rBase = targetReg(kArg0);
       oatLockTemp(cUnit, rBase);
       loadWordDisp(cUnit, rMethod,
                    AbstractMethod::DexCacheInitializedStaticStorageOffset().Int32Value(),
@@ -688,8 +688,8 @@
       LIR* branchOver = opCmpImmBranch(cUnit, kCondNe, rBase, 0, NULL);
       callRuntimeHelperImm(cUnit, ENTRYPOINT_OFFSET(pInitializeStaticStorage), ssbIndex, true);
       if (cUnit->instructionSet == kMips) {
-        // For Arm, rRET0 = rARG0 = rBASE, for Mips, we need to copy
-        opRegCopy(cUnit, rBase, rRET0);
+        // For Arm, kRet0 = kArg0 = rBase, for Mips, we need to copy
+        opRegCopy(cUnit, rBase, targetReg(kRet0));
       }
       LIR* skipTarget = newLIR0(cUnit, kPseudoTargetLabel);
       branchOver->target = (LIR*)skipTarget;
@@ -733,8 +733,8 @@
 void genShowTarget(CompilationUnit* cUnit)
 {
   DCHECK_NE(cUnit->instructionSet, kX86) << "unimplemented genShowTarget";
-  LIR* branchOver = opCmpImmBranch(cUnit, kCondNe, rINVOKE_TGT, 0, NULL);
-  loadWordDisp(cUnit, rSELF, ENTRYPOINT_OFFSET(pDebugMe), rINVOKE_TGT);
+  LIR* branchOver = opCmpImmBranch(cUnit, kCondNe, targetReg(kInvokeTgt), 0, NULL);
+  loadWordDisp(cUnit, targetReg(kSelf), ENTRYPOINT_OFFSET(pDebugMe), targetReg(kInvokeTgt));
   LIR* target = newLIR0(cUnit, kPseudoTargetLabel);
   branchOver->target = (LIR*)target;
 }
@@ -796,34 +796,34 @@
         funcOffset = ENTRYPOINT_OFFSET(pThrowNullPointerFromCode);
         break;
       case kThrowArrayBounds:
-        // Move v1 (array index) to rARG0 and v2 (array length) to rARG1
-        if (v2 != rARG0) {
-          opRegCopy(cUnit, rARG0, v1);
+        // Move v1 (array index) to kArg0 and v2 (array length) to kArg1
+        if (v2 != targetReg(kArg0)) {
+          opRegCopy(cUnit, targetReg(kArg0), v1);
           if (targetX86) {
             // x86 leaves the array pointer in v2, so load the array length that the handler expects
-            opRegMem(cUnit, kOpMov, rARG1, v2, Array::LengthOffset().Int32Value());
+            opRegMem(cUnit, kOpMov, targetReg(kArg1), v2, Array::LengthOffset().Int32Value());
           } else {
-            opRegCopy(cUnit, rARG1, v2);
+            opRegCopy(cUnit, targetReg(kArg1), v2);
           }
         } else {
-          if (v1 == rARG1) {
-            // Swap v1 and v2, using rARG2 as a temp
-            opRegCopy(cUnit, rARG2, v1);
+          if (v1 == targetReg(kArg1)) {
+            // Swap v1 and v2, using kArg2 as a temp
+            opRegCopy(cUnit, targetReg(kArg2), v1);
             if (targetX86) {
               // x86 leaves the array pointer in v2; load the array length that the handler expects
-              opRegMem(cUnit, kOpMov, rARG1, v2, Array::LengthOffset().Int32Value());
+              opRegMem(cUnit, kOpMov, targetReg(kArg1), v2, Array::LengthOffset().Int32Value());
             } else {
-              opRegCopy(cUnit, rARG1, v2);
+              opRegCopy(cUnit, targetReg(kArg1), v2);
             }
-            opRegCopy(cUnit, rARG0, rARG2);
+            opRegCopy(cUnit, targetReg(kArg0), targetReg(kArg2));
           } else {
             if (targetX86) {
               // x86 leaves the array pointer in v2; load the array length that the handler expects
-              opRegMem(cUnit, kOpMov, rARG1, v2, Array::LengthOffset().Int32Value());
+              opRegMem(cUnit, kOpMov, targetReg(kArg1), v2, Array::LengthOffset().Int32Value());
             } else {
-              opRegCopy(cUnit, rARG1, v2);
+              opRegCopy(cUnit, targetReg(kArg1), v2);
             }
-            opRegCopy(cUnit, rARG0, v1);
+            opRegCopy(cUnit, targetReg(kArg0), v1);
           }
         }
         funcOffset = ENTRYPOINT_OFFSET(pThrowArrayBoundsFromCode);
@@ -832,7 +832,7 @@
         funcOffset = ENTRYPOINT_OFFSET(pThrowDivZeroFromCode);
         break;
       case kThrowNoSuchMethod:
-        opRegCopy(cUnit, rARG0, v1);
+        opRegCopy(cUnit, targetReg(kArg0), v1);
         funcOffset =
           ENTRYPOINT_OFFSET(pThrowNoSuchMethodFromCode);
         break;
@@ -840,9 +840,9 @@
         funcOffset = ENTRYPOINT_OFFSET(pThrowStackOverflowFromCode);
         // Restore stack alignment
         if (targetX86) {
-          opRegImm(cUnit, kOpAdd, rSP, cUnit->frameSize);
+          opRegImm(cUnit, kOpAdd, targetReg(kSp), cUnit->frameSize);
         } else {
-          opRegImm(cUnit, kOpAdd, rSP, (cUnit->numCoreSpills + cUnit->numFPSpills) * 4);
+          opRegImm(cUnit, kOpAdd, targetReg(kSp), (cUnit->numCoreSpills + cUnit->numFPSpills) * 4);
         }
         break;
       default:
@@ -990,7 +990,7 @@
                                                    *cUnit->dex_file,
                                                    type_idx)) {
     // Call out to helper which resolves type and verifies access.
-    // Resolved type returned in rRET0.
+    // Resolved type returned in kRet0.
     callRuntimeHelperImmReg(cUnit, ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccessFromCode),
                             type_idx, rlMethod.lowReg, true);
     RegLocation rlResult = oatGetReturn(cUnit, false);
@@ -1019,7 +1019,7 @@
       LIR* branch2 = opUnconditionalBranch(cUnit,0);
       // TUNING: move slow path to end & remove unconditional branch
       LIR* target1 = newLIR0(cUnit, kPseudoTargetLabel);
-      // Call out to helper, which will return resolved type in rARG0
+      // Call out to helper, which will return resolved type in kArg0
       callRuntimeHelperImmReg(cUnit, ENTRYPOINT_OFFSET(pInitializeTypeFromCode), type_idx,
                               rlMethod.lowReg, true);
       RegLocation rlResult = oatGetReturn(cUnit, false);
@@ -1051,27 +1051,27 @@
     // slow path, resolve string if not in dex cache
     oatFlushAllRegs(cUnit);
     oatLockCallTemps(cUnit); // Using explicit registers
-    loadCurrMethodDirect(cUnit, rARG2);
-    loadWordDisp(cUnit, rARG2,
-                 AbstractMethod::DexCacheStringsOffset().Int32Value(), rARG0);
-    // Might call out to helper, which will return resolved string in rRET0
+    loadCurrMethodDirect(cUnit, targetReg(kArg2));
+    loadWordDisp(cUnit, targetReg(kArg2),
+                 AbstractMethod::DexCacheStringsOffset().Int32Value(), targetReg(kArg0));
+    // Might call out to helper, which will return resolved string in kRet0
     int rTgt = callHelperSetup(cUnit, ENTRYPOINT_OFFSET(pResolveStringFromCode));
-    loadWordDisp(cUnit, rARG0, offset_of_string, rRET0);
-    loadConstant(cUnit, rARG1, string_idx);
+    loadWordDisp(cUnit, targetReg(kArg0), offset_of_string, targetReg(kRet0));
+    loadConstant(cUnit, targetReg(kArg1), string_idx);
     if (cUnit->instructionSet == kThumb2) {
-      opRegImm(cUnit, kOpCmp, rRET0, 0);  // Is resolved?
+      opRegImm(cUnit, kOpCmp, targetReg(kRet0), 0);  // Is resolved?
       genBarrier(cUnit);
       // For testing, always force through helper
       if (!EXERCISE_SLOWEST_STRING_PATH) {
         opIT(cUnit, kArmCondEq, "T");
       }
-      opRegCopy(cUnit, rARG0, rARG2);   // .eq
+      opRegCopy(cUnit, targetReg(kArg0), targetReg(kArg2));   // .eq
       LIR* callInst = opReg(cUnit, kOpBlx, rTgt);    // .eq, helper(Method*, string_idx)
       markSafepointPC(cUnit, callInst);
       oatFreeTemp(cUnit, rTgt);
     } else if (cUnit->instructionSet == kMips) {
-      LIR* branch = opCmpImmBranch(cUnit, kCondNe, rRET0, 0, NULL);
-      opRegCopy(cUnit, rARG0, rARG2);   // .eq
+      LIR* branch = opCmpImmBranch(cUnit, kCondNe, targetReg(kRet0), 0, NULL);
+      opRegCopy(cUnit, targetReg(kArg0), targetReg(kArg2));   // .eq
       LIR* callInst = opReg(cUnit, kOpBlx, rTgt);
       markSafepointPC(cUnit, callInst);
       oatFreeTemp(cUnit, rTgt);
@@ -1079,7 +1079,7 @@
       branch->target = target;
     } else {
       DCHECK_EQ(cUnit->instructionSet, kX86);
-      callRuntimeHelperRegReg(cUnit, ENTRYPOINT_OFFSET(pResolveStringFromCode), rARG2, rARG1, true);
+      callRuntimeHelperRegReg(cUnit, ENTRYPOINT_OFFSET(pResolveStringFromCode), targetReg(kArg2), targetReg(kArg1), true);
     }
     genBarrier(cUnit);
     storeValue(cUnit, rlDest, oatGetReturn(cUnit, false));
@@ -1121,9 +1121,9 @@
   int funcOffset = ENTRYPOINT_OFFSET(pGetAndClearException);
   if (cUnit->instructionSet == kX86) {
     // Runtime helper will load argument for x86.
-    callRuntimeHelperReg(cUnit, funcOffset, rARG0, false);
+    callRuntimeHelperReg(cUnit, funcOffset, targetReg(kArg0), false);
   } else {
-    callRuntimeHelperReg(cUnit, funcOffset, rSELF, false);
+    callRuntimeHelperReg(cUnit, funcOffset, targetReg(kSelf), false);
   }
   RegLocation rlResult = oatGetReturn(cUnit, false);
   storeValue(cUnit, rlDest, rlResult);
@@ -1141,21 +1141,21 @@
   oatFlushAllRegs(cUnit);
   // May generate a call - use explicit registers
   oatLockCallTemps(cUnit);
-  loadCurrMethodDirect(cUnit, rARG1);  // rARG1 <= current Method*
-  int classReg = rARG2;  // rARG2 will hold the Class*
+  loadCurrMethodDirect(cUnit, targetReg(kArg1));  // kArg1 <= current Method*
+  int classReg = targetReg(kArg2);  // kArg2 will hold the Class*
   if (!cUnit->compiler->CanAccessTypeWithoutChecks(cUnit->method_idx,
                                                    *cUnit->dex_file,
                                                    type_idx)) {
     // Check we have access to type_idx and if not throw IllegalAccessError,
-    // returns Class* in rARG0
+    // returns Class* in kArg0
     callRuntimeHelperImm(cUnit, ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccessFromCode),
                          type_idx, true);
-    opRegCopy(cUnit, classReg, rRET0);  // Align usage with fast path
-    loadValueDirectFixed(cUnit, rlSrc, rARG0);  // rARG0 <= ref
+    opRegCopy(cUnit, classReg, targetReg(kRet0));  // Align usage with fast path
+    loadValueDirectFixed(cUnit, rlSrc, targetReg(kArg0));  // kArg0 <= ref
   } else {
-    // Load dex cache entry into classReg (rARG2)
-    loadValueDirectFixed(cUnit, rlSrc, rARG0);  // rARG0 <= ref
-    loadWordDisp(cUnit, rARG1,
+    // Load dex cache entry into classReg (kArg2)
+    loadValueDirectFixed(cUnit, rlSrc, targetReg(kArg0));  // kArg0 <= ref
+    loadWordDisp(cUnit, targetReg(kArg1),
                  AbstractMethod::DexCacheResolvedTypesOffset().Int32Value(), classReg);
     int32_t offset_of_type =
         Array::DataOffset(sizeof(Class*)).Int32Value() + (sizeof(Class*)
@@ -1166,47 +1166,47 @@
       // Need to test presence of type in dex cache at runtime
       LIR* hopBranch = opCmpImmBranch(cUnit, kCondNe, classReg, 0, NULL);
       // Not resolved
-      // Call out to helper, which will return resolved type in rRET0
+      // Call out to helper, which will return resolved type in kRet0
       callRuntimeHelperImm(cUnit, ENTRYPOINT_OFFSET(pInitializeTypeFromCode), type_idx, true);
-      opRegCopy(cUnit, rARG2, rRET0); // Align usage with fast path
-      loadValueDirectFixed(cUnit, rlSrc, rARG0);  /* reload Ref */
+      opRegCopy(cUnit, targetReg(kArg2), targetReg(kRet0)); // Align usage with fast path
+      loadValueDirectFixed(cUnit, rlSrc, targetReg(kArg0));  /* reload Ref */
       // Rejoin code paths
       LIR* hopTarget = newLIR0(cUnit, kPseudoTargetLabel);
       hopBranch->target = (LIR*)hopTarget;
     }
   }
-  /* rARG0 is ref, rARG2 is class. If ref==null, use directly as bool result */
+  /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result */
   RegLocation rlResult = oatGetReturn(cUnit, false);
   if (cUnit->instructionSet == kMips) {
     loadConstant(cUnit, rlResult.lowReg, 0);  // store false result for if branch is taken
   }
-  LIR* branch1 = opCmpImmBranch(cUnit, kCondEq, rARG0, 0, NULL);
+  LIR* branch1 = opCmpImmBranch(cUnit, kCondEq, targetReg(kArg0), 0, NULL);
   /* load object->klass_ */
   DCHECK_EQ(Object::ClassOffset().Int32Value(), 0);
-  loadWordDisp(cUnit, rARG0,  Object::ClassOffset().Int32Value(), rARG1);
-  /* rARG0 is ref, rARG1 is ref->klass_, rARG2 is class */
+  loadWordDisp(cUnit, targetReg(kArg0),  Object::ClassOffset().Int32Value(), targetReg(kArg1));
+  /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class */
   LIR* callInst;
   LIR* branchover = NULL;
   if (cUnit->instructionSet == kThumb2) {
     /* Uses conditional nullification */
     int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pInstanceofNonTrivialFromCode));
-    opRegReg(cUnit, kOpCmp, rARG1, rARG2);  // Same?
+    opRegReg(cUnit, kOpCmp, targetReg(kArg1), targetReg(kArg2));  // Same?
     opIT(cUnit, kArmCondEq, "EE");   // if-convert the test
-    loadConstant(cUnit, rARG0, 1);     // .eq case - load true
-    opRegCopy(cUnit, rARG0, rARG2);    // .ne case - arg0 <= class
+    loadConstant(cUnit, targetReg(kArg0), 1);     // .eq case - load true
+    opRegCopy(cUnit, targetReg(kArg0), targetReg(kArg2));    // .ne case - arg0 <= class
     callInst = opReg(cUnit, kOpBlx, rTgt);    // .ne case: helper(class, ref->class)
     oatFreeTemp(cUnit, rTgt);
   } else {
     /* Uses branchovers */
     loadConstant(cUnit, rlResult.lowReg, 1);     // assume true
-    branchover = opCmpBranch(cUnit, kCondEq, rARG1, rARG2, NULL);
+    branchover = opCmpBranch(cUnit, kCondEq, targetReg(kArg1), targetReg(kArg2), NULL);
     if (cUnit->instructionSet != kX86) {
       int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pInstanceofNonTrivialFromCode));
-      opRegCopy(cUnit, rARG0, rARG2);    // .ne case - arg0 <= class
+      opRegCopy(cUnit, targetReg(kArg0), targetReg(kArg2));    // .ne case - arg0 <= class
       callInst = opReg(cUnit, kOpBlx, rTgt);    // .ne case: helper(class, ref->class)
       oatFreeTemp(cUnit, rTgt);
     } else {
-      opRegCopy(cUnit, rARG0, rARG2);
+      opRegCopy(cUnit, targetReg(kArg0), targetReg(kArg2));
       callInst = opThreadMem(cUnit, kOpBlx, ENTRYPOINT_OFFSET(pInstanceofNonTrivialFromCode));
     }
   }
@@ -1226,20 +1226,20 @@
   oatFlushAllRegs(cUnit);
   // May generate a call - use explicit registers
   oatLockCallTemps(cUnit);
-  loadCurrMethodDirect(cUnit, rARG1);  // rARG1 <= current Method*
-  int classReg = rARG2;  // rARG2 will hold the Class*
+  loadCurrMethodDirect(cUnit, targetReg(kArg1));  // kArg1 <= current Method*
+  int classReg = targetReg(kArg2);  // kArg2 will hold the Class*
   if (!cUnit->compiler->CanAccessTypeWithoutChecks(cUnit->method_idx,
                                                    *cUnit->dex_file,
                                                    type_idx)) {
     // Check we have access to type_idx and if not throw IllegalAccessError,
-    // returns Class* in rRET0
+    // returns Class* in kRet0
     // InitializeTypeAndVerifyAccess(idx, method)
     callRuntimeHelperImmReg(cUnit, ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccessFromCode),
-                            type_idx, rARG1, true);
-    opRegCopy(cUnit, classReg, rRET0);  // Align usage with fast path
+                            type_idx, targetReg(kArg1), true);
+    opRegCopy(cUnit, classReg, targetReg(kRet0));  // Align usage with fast path
   } else {
-    // Load dex cache entry into classReg (rARG2)
-    loadWordDisp(cUnit, rARG1,
+    // Load dex cache entry into classReg (kArg2)
+    loadWordDisp(cUnit, targetReg(kArg1),
                  AbstractMethod::DexCacheResolvedTypesOffset().Int32Value(), classReg);
     int32_t offset_of_type =
         Array::DataOffset(sizeof(Class*)).Int32Value() +
@@ -1250,38 +1250,38 @@
       // Need to test presence of type in dex cache at runtime
       LIR* hopBranch = opCmpImmBranch(cUnit, kCondNe, classReg, 0, NULL);
       // Not resolved
-      // Call out to helper, which will return resolved type in rARG0
+      // Call out to helper, which will return resolved type in kArg0
       // InitializeTypeFromCode(idx, method)
-      callRuntimeHelperImmReg(cUnit, ENTRYPOINT_OFFSET(pInitializeTypeFromCode), type_idx, rARG1,
+      callRuntimeHelperImmReg(cUnit, ENTRYPOINT_OFFSET(pInitializeTypeFromCode), type_idx, targetReg(kArg1),
                               true);
-      opRegCopy(cUnit, classReg, rRET0); // Align usage with fast path
+      opRegCopy(cUnit, classReg, targetReg(kRet0)); // Align usage with fast path
       // Rejoin code paths
       LIR* hopTarget = newLIR0(cUnit, kPseudoTargetLabel);
       hopBranch->target = (LIR*)hopTarget;
     }
   }
-  // At this point, classReg (rARG2) has class
-  loadValueDirectFixed(cUnit, rlSrc, rARG0);  // rARG0 <= ref
+  // At this point, classReg (kArg2) has class
+  loadValueDirectFixed(cUnit, rlSrc, targetReg(kArg0));  // kArg0 <= ref
   /* Null is OK - continue */
-  LIR* branch1 = opCmpImmBranch(cUnit, kCondEq, rARG0, 0, NULL);
+  LIR* branch1 = opCmpImmBranch(cUnit, kCondEq, targetReg(kArg0), 0, NULL);
   /* load object->klass_ */
   DCHECK_EQ(Object::ClassOffset().Int32Value(), 0);
-  loadWordDisp(cUnit, rARG0,  Object::ClassOffset().Int32Value(), rARG1);
-  /* rARG1 now contains object->klass_ */
+  loadWordDisp(cUnit, targetReg(kArg0),  Object::ClassOffset().Int32Value(), targetReg(kArg1));
+  /* kArg1 now contains object->klass_ */
   LIR* branch2;
   if (cUnit->instructionSet == kThumb2) {
     int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pCheckCastFromCode));
-    opRegReg(cUnit, kOpCmp, rARG1, classReg);
+    opRegReg(cUnit, kOpCmp, targetReg(kArg1), classReg);
     branch2 = opCondBranch(cUnit, kCondEq, NULL); /* If eq, trivial yes */
-    opRegCopy(cUnit, rARG0, rARG1);
-    opRegCopy(cUnit, rARG1, rARG2);
+    opRegCopy(cUnit, targetReg(kArg0), targetReg(kArg1));
+    opRegCopy(cUnit, targetReg(kArg1), targetReg(kArg2));
     oatClobberCalleeSave(cUnit);
     LIR* callInst = opReg(cUnit, kOpBlx, rTgt);
     markSafepointPC(cUnit, callInst);
     oatFreeTemp(cUnit, rTgt);
   } else {
-    branch2 = opCmpBranch(cUnit, kCondEq, rARG1, classReg, NULL);
-    callRuntimeHelperRegReg(cUnit, ENTRYPOINT_OFFSET(pCheckCastFromCode), rARG1, rARG2, true);
+    branch2 = opCmpBranch(cUnit, kCondEq, targetReg(kArg1), classReg, NULL);
+    callRuntimeHelperRegReg(cUnit, ENTRYPOINT_OFFSET(pCheckCastFromCode), targetReg(kArg1), targetReg(kArg2), true);
   }
   /* branch target here */
   LIR* target = newLIR0(cUnit, kPseudoTargetLabel);
@@ -1302,10 +1302,10 @@
   oatFlushAllRegs(cUnit);  // Use explicit registers
   oatLockCallTemps(cUnit);
 
-  int rValue = rARG0;  // Register holding value
-  int rArrayClass = rARG1;  // Register holding array's Class
-  int rArray = rARG2;  // Register holding array
-  int rIndex = rARG3;  // Register holding index into array
+  int rValue = targetReg(kArg0);  // Register holding value
+  int rArrayClass = targetReg(kArg1);  // Register holding array's Class
+  int rArray = targetReg(kArg2);  // Register holding array
+  int rIndex = targetReg(kArg3);  // Register holding index into array
 
   loadValueDirectFixed(cUnit, rlArray, rArray);  // Grab array
   loadValueDirectFixed(cUnit, rlSrc, rValue);  // Grab value
@@ -1332,7 +1332,7 @@
 
   if (cUnit->instructionSet == kX86) {
     // make an extra temp available for card mark below
-    oatFreeTemp(cUnit, rARG1);
+    oatFreeTemp(cUnit, targetReg(kArg1));
     if (!(optFlags & MIR_IGNORE_RANGE_CHECK)) {
       /* if (rlIndex >= [rlArray + lenOffset]) goto kThrowArrayBounds */
       genRegMemCheck(cUnit, kCondUge, rIndex, rArray, lenOffset, kThrowArrayBounds);
@@ -1343,7 +1343,7 @@
     bool needsRangeCheck = (!(optFlags & MIR_IGNORE_RANGE_CHECK));
     int regLen = INVALID_REG;
     if (needsRangeCheck) {
-      regLen = rARG1;
+      regLen = targetReg(kArg1);
       loadWordDisp(cUnit, rArray, lenOffset, regLen);  // Get len
     }
     /* rPtr -> array data */
@@ -1569,8 +1569,8 @@
      * lr is used explicitly elsewhere in the code generator and cannot
      * normally be used as a general temp register.
      */
-    oatMarkTemp(cUnit, rLR);   // Add lr to the temp pool
-    oatFreeTemp(cUnit, rLR);   // and make it available
+    oatMarkTemp(cUnit, targetReg(kLr));   // Add lr to the temp pool
+    oatFreeTemp(cUnit, targetReg(kLr));   // and make it available
   }
   rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
   rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
@@ -1598,8 +1598,8 @@
   freeRegLocTemps(cUnit, rlResult, rlSrc2);
   storeValueWide(cUnit, rlDest, rlResult);
   if (cUnit->instructionSet == kThumb2) {
-    oatClobber(cUnit, rLR);
-    oatUnmarkTemp(cUnit, rLR);  // Remove lr from the temp pool
+    oatClobber(cUnit, targetReg(kLr));
+    oatUnmarkTemp(cUnit, targetReg(kLr));  // Remove lr from the temp pool
   }
 }
 
@@ -1670,7 +1670,7 @@
       op = kOpDiv;
       isDivRem = true;
       break;
-    /* NOTE: returns in rARG1 */
+    /* NOTE: returns in kArg1 */
     case Instruction::REM_INT:
     case Instruction::REM_INT_2ADDR:
       checkZero = true;
@@ -1718,7 +1718,7 @@
         int tReg = INVALID_REG;
         if (cUnit->instructionSet == kX86) {
           // X86 doesn't require masking and must use ECX
-          tReg = rCOUNT;  // rCX
+          tReg = targetReg(kCount);  // rCX
           loadValueDirectFixed(cUnit, rlSrc2, tReg);
         } else {
           rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
@@ -1748,11 +1748,11 @@
     } else {
       int funcOffset = ENTRYPOINT_OFFSET(pIdivmod);
       oatFlushAllRegs(cUnit);   /* Send everything to home location */
-      loadValueDirectFixed(cUnit, rlSrc2, rARG1);
+      loadValueDirectFixed(cUnit, rlSrc2, targetReg(kArg1));
       int rTgt = callHelperSetup(cUnit, funcOffset);
-      loadValueDirectFixed(cUnit, rlSrc1, rARG0);
+      loadValueDirectFixed(cUnit, rlSrc1, targetReg(kArg0));
       if (checkZero) {
-        genImmedCheck(cUnit, kCondEq, rARG1, 0, kThrowDivZero);
+        genImmedCheck(cUnit, kCondEq, targetReg(kArg1), 0, kThrowDivZero);
       }
       // NOTE: callout here is not a safepoint
       callHelper(cUnit, rTgt, funcOffset, false /* not a safepoint */ );
@@ -1985,10 +1985,10 @@
         rlResult = genDivRemLit(cUnit, rlDest, rlSrc.lowReg, lit, isDiv);
       } else {
         oatFlushAllRegs(cUnit);   /* Everything to home location */
-        loadValueDirectFixed(cUnit, rlSrc, rARG0);
-        oatClobber(cUnit, rARG0);
+        loadValueDirectFixed(cUnit, rlSrc, targetReg(kArg0));
+        oatClobber(cUnit, targetReg(kArg0));
         int funcOffset = ENTRYPOINT_OFFSET(pIdivmod);
-        callRuntimeHelperRegImm(cUnit, funcOffset, rARG0, lit, false);
+        callRuntimeHelperRegImm(cUnit, funcOffset, targetReg(kArg0), lit, false);
         if (isDiv)
           rlResult = oatGetReturn(cUnit, false);
         else
@@ -2022,7 +2022,7 @@
   bool callOut = false;
   bool checkZero = false;
   int funcOffset;
-  int retReg = rRET0;
+  int retReg = targetReg(kRet0);
 
   switch (opcode) {
     case Instruction::NOT_LONG:
@@ -2061,14 +2061,14 @@
     case Instruction::MUL_LONG:
     case Instruction::MUL_LONG_2ADDR:
       callOut = true;
-      retReg = rRET0;
+      retReg = targetReg(kRet0);
       funcOffset = ENTRYPOINT_OFFSET(pLmul);
       break;
     case Instruction::DIV_LONG:
     case Instruction::DIV_LONG_2ADDR:
       callOut = true;
       checkZero = true;
-      retReg = rRET0;
+      retReg = targetReg(kRet0);
       funcOffset = ENTRYPOINT_OFFSET(pLdiv);
       break;
     case Instruction::REM_LONG:
@@ -2076,8 +2076,8 @@
       callOut = true;
       checkZero = true;
       funcOffset = ENTRYPOINT_OFFSET(pLdivmod);
-      /* NOTE - for Arm, result is in rARG2/rARG3 instead of rRET0/rRET1 */
-      retReg = (cUnit->instructionSet == kThumb2) ? rARG2 : rRET0;
+      /* NOTE - for Arm, result is in kArg2/kArg3 instead of kRet0/kRet1 */
+      retReg = (cUnit->instructionSet == kThumb2) ? targetReg(kArg2) : targetReg(kRet0);
       break;
     case Instruction::AND_LONG_2ADDR:
     case Instruction::AND_LONG:
@@ -2114,18 +2114,18 @@
   } else {
     oatFlushAllRegs(cUnit);   /* Send everything to home location */
     if (checkZero) {
-      loadValueDirectWideFixed(cUnit, rlSrc2, rARG2, rARG3);
+      loadValueDirectWideFixed(cUnit, rlSrc2, targetReg(kArg2), targetReg(kArg3));
       int rTgt = callHelperSetup(cUnit, funcOffset);
-      genDivZeroCheck(cUnit, rARG2, rARG3);
-      loadValueDirectWideFixed(cUnit, rlSrc1, rARG0, rARG1);
+      genDivZeroCheck(cUnit, targetReg(kArg2), targetReg(kArg3));
+      loadValueDirectWideFixed(cUnit, rlSrc1, targetReg(kArg0), targetReg(kArg1));
       // NOTE: callout here is not a safepoint
       callHelper(cUnit, rTgt, funcOffset, false /* not safepoint */);
     } else {
       callRuntimeHelperRegLocationRegLocation(cUnit, funcOffset,
                           rlSrc1, rlSrc2, false);
     }
-    // Adjust return regs in to handle case of rem returning rARG2/rARG3
-    if (retReg == rRET0)
+    // Adjust return regs in to handle case of rem returning kArg2/kArg3
+    if (retReg == targetReg(kRet0))
       rlResult = oatGetReturnWide(cUnit, false);
     else
       rlResult = oatGetReturnWideAlt(cUnit);
@@ -2143,9 +2143,10 @@
    */
   oatFlushAllRegs(cUnit);   /* Send everything to home location */
   if (rlSrc.wide) {
-    loadValueDirectWideFixed(cUnit, rlSrc, rlSrc.fp ? rFARG0 : rARG0, rlSrc.fp ? rFARG1 : rARG1);
+    loadValueDirectWideFixed(cUnit, rlSrc, rlSrc.fp ? targetReg(kFArg0) : targetReg(kArg0),
+                             rlSrc.fp ? targetReg(kFArg1) : targetReg(kArg1));
   } else {
-    loadValueDirectFixed(cUnit, rlSrc, rlSrc.fp ? rFARG0 : rARG0);
+    loadValueDirectFixed(cUnit, rlSrc, rlSrc.fp ? targetReg(kFArg0) : targetReg(kArg0));
   }
   callRuntimeHelperRegLocation(cUnit, funcOffset, rlSrc, false);
   if (rlDest.wide) {
diff --git a/src/compiler/codegen/GenInvoke.cc b/src/compiler/codegen/GenInvoke.cc
index 2da6242..efd4f5a 100644
--- a/src/compiler/codegen/GenInvoke.cc
+++ b/src/compiler/codegen/GenInvoke.cc
@@ -41,24 +41,24 @@
 {
   /*
    * Dummy up a RegLocation for the incoming Method*
-   * It will attempt to keep rARG0 live (or copy it to home location
+   * It will attempt to keep kArg0 live (or copy it to home location
    * if promoted).
    */
   RegLocation rlSrc = rlMethod;
   rlSrc.location = kLocPhysReg;
-  rlSrc.lowReg = rARG0;
+  rlSrc.lowReg = targetReg(kArg0);
   rlSrc.home = false;
   oatMarkLive(cUnit, rlSrc.lowReg, rlSrc.sRegLow);
   storeValue(cUnit, rlMethod, rlSrc);
   // If Method* has been promoted, explicitly flush
   if (rlMethod.location == kLocPhysReg) {
-    storeWordDisp(cUnit, rSP, 0, rARG0);
+    storeWordDisp(cUnit, targetReg(kSp), 0, targetReg(kArg0));
   }
 
   if (cUnit->numIns == 0)
     return;
   const int numArgRegs = 3;
-  static int argRegs[] = {rARG1, rARG2, rARG3};
+  static SpecialTargetRegister argRegs[] = {kArg1, kArg2, kArg3};
   int startVReg = cUnit->numDalvikRegisters - cUnit->numIns;
   /*
    * Copy incoming arguments to their proper home locations.
@@ -79,10 +79,10 @@
       bool needFlush = true;
       RegLocation* tLoc = &argLocs[i];
       if ((vMap->coreLocation == kLocPhysReg) && !tLoc->fp) {
-        opRegCopy(cUnit, vMap->coreReg, argRegs[i]);
+        opRegCopy(cUnit, vMap->coreReg, targetReg(argRegs[i]));
         needFlush = false;
       } else if ((vMap->fpLocation == kLocPhysReg) && tLoc->fp) {
-        opRegCopy(cUnit, vMap->fpReg, argRegs[i]);
+        opRegCopy(cUnit, vMap->fpReg, targetReg(argRegs[i]));
         needFlush = false;
       } else {
         needFlush = true;
@@ -95,17 +95,17 @@
             (pMap->fpLocation != vMap->fpLocation);
       }
       if (needFlush) {
-        storeBaseDisp(cUnit, rSP, oatSRegOffset(cUnit, startVReg + i),
-                      argRegs[i], kWord);
+        storeBaseDisp(cUnit, targetReg(kSp), oatSRegOffset(cUnit, startVReg + i),
+                      targetReg(argRegs[i]), kWord);
       }
     } else {
       // If arriving in frame & promoted
       if (vMap->coreLocation == kLocPhysReg) {
-        loadWordDisp(cUnit, rSP, oatSRegOffset(cUnit, startVReg + i),
+        loadWordDisp(cUnit, targetReg(kSp), oatSRegOffset(cUnit, startVReg + i),
                      vMap->coreReg);
       }
       if (vMap->fpLocation == kLocPhysReg) {
-        loadWordDisp(cUnit, rSP, oatSRegOffset(cUnit, startVReg + i),
+        loadWordDisp(cUnit, targetReg(kSp), oatSRegOffset(cUnit, startVReg + i),
                      vMap->fpReg);
       }
     }
@@ -147,28 +147,28 @@
   }
   if (directCode != 0 && directMethod != 0) {
     switch (state) {
-    case 0:  // Get the current Method* [sets rARG0]
+    case 0:  // Get the current Method* [sets kArg0]
       if (directCode != (uintptr_t)-1) {
-        loadConstant(cUnit, rINVOKE_TGT, directCode);
+        loadConstant(cUnit, targetReg(kInvokeTgt), directCode);
       } else {
         LIR* dataTarget = scanLiteralPool(cUnit->codeLiteralList, dexIdx, 0);
         if (dataTarget == NULL) {
           dataTarget = addWordData(cUnit, &cUnit->codeLiteralList, dexIdx);
           dataTarget->operands[1] = type;
         }
-        LIR* loadPcRel = opPcRelLoad(cUnit, rINVOKE_TGT, dataTarget);
+        LIR* loadPcRel = opPcRelLoad(cUnit, targetReg(kInvokeTgt), dataTarget);
         oatAppendLIR(cUnit, loadPcRel);
         DCHECK_EQ(cUnit->instructionSet, kThumb2) << (void*)dataTarget;
       }
       if (directMethod != (uintptr_t)-1) {
-        loadConstant(cUnit, rARG0, directMethod);
+        loadConstant(cUnit, targetReg(kArg0), directMethod);
       } else {
         LIR* dataTarget = scanLiteralPool(cUnit->methodLiteralList, dexIdx, 0);
         if (dataTarget == NULL) {
           dataTarget = addWordData(cUnit, &cUnit->methodLiteralList, dexIdx);
           dataTarget->operands[1] = type;
         }
-        LIR* loadPcRel = opPcRelLoad(cUnit, rARG0, dataTarget);
+        LIR* loadPcRel = opPcRelLoad(cUnit, targetReg(kArg0), dataTarget);
         oatAppendLIR(cUnit, loadPcRel);
         DCHECK_EQ(cUnit->instructionSet, kThumb2) << (void*)dataTarget;
       }
@@ -178,40 +178,38 @@
     }
   } else {
     switch (state) {
-    case 0:  // Get the current Method* [sets rARG0]
+    case 0:  // Get the current Method* [sets kArg0]
       // TUNING: we can save a reg copy if Method* has been promoted.
-      loadCurrMethodDirect(cUnit, rARG0);
+      loadCurrMethodDirect(cUnit, targetReg(kArg0));
       break;
     case 1:  // Get method->dex_cache_resolved_methods_
-      loadWordDisp(cUnit, rARG0,
-        AbstractMethod::DexCacheResolvedMethodsOffset().Int32Value(),
-        rARG0);
+      loadWordDisp(cUnit, targetReg(kArg0),
+        AbstractMethod::DexCacheResolvedMethodsOffset().Int32Value(), targetReg(kArg0));
       // Set up direct code if known.
       if (directCode != 0) {
         if (directCode != (uintptr_t)-1) {
-          loadConstant(cUnit, rINVOKE_TGT, directCode);
+          loadConstant(cUnit, targetReg(kInvokeTgt), directCode);
         } else {
           LIR* dataTarget = scanLiteralPool(cUnit->codeLiteralList, dexIdx, 0);
           if (dataTarget == NULL) {
             dataTarget = addWordData(cUnit, &cUnit->codeLiteralList, dexIdx);
             dataTarget->operands[1] = type;
           }
-          LIR* loadPcRel = opPcRelLoad(cUnit, rINVOKE_TGT, dataTarget);
+          LIR* loadPcRel = opPcRelLoad(cUnit, targetReg(kInvokeTgt), dataTarget);
           oatAppendLIR(cUnit, loadPcRel);
           DCHECK_EQ(cUnit->instructionSet, kThumb2) << (void*)dataTarget;
         }
       }
       break;
     case 2:  // Grab target method*
-      loadWordDisp(cUnit, rARG0,
-                   Array::DataOffset(sizeof(Object*)).Int32Value() + dexIdx * 4,
-                   rARG0);
+      loadWordDisp(cUnit, targetReg(kArg0),
+                   Array::DataOffset(sizeof(Object*)).Int32Value() + dexIdx * 4, targetReg(kArg0));
       break;
     case 3:  // Grab the code from the method*
       if (cUnit->instructionSet != kX86) {
         if (directCode == 0) {
-          loadWordDisp(cUnit, rARG0, AbstractMethod::GetCodeOffset().Int32Value(),
-                       rINVOKE_TGT);
+          loadWordDisp(cUnit, targetReg(kArg0), AbstractMethod::GetCodeOffset().Int32Value(),
+                       targetReg(kInvokeTgt));
         }
         break;
       }
@@ -226,9 +224,9 @@
 /*
  * Bit of a hack here - in the absence of a real scheduling pass,
  * emit the next instruction in a virtual invoke sequence.
- * We can use rLR as a temp prior to target address loading
+ * We can use kLr as a temp prior to target address loading
  * Note also that we'll load the first argument ("this") into
- * rARG1 here rather than the standard loadArgRegs.
+ * kArg1 here rather than the standard loadArgRegs.
  */
 int nextVCallInsn(CompilationUnit* cUnit, CallInfo* info,
                   int state, uint32_t dexIdx, uint32_t methodIdx,
@@ -239,28 +237,29 @@
    * fully resolved at compile time.
    */
   switch (state) {
-    case 0: {  // Get "this" [set rARG1]
+    case 0: {  // Get "this" [set kArg1]
       RegLocation  rlArg = info->args[0];
-      loadValueDirectFixed(cUnit, rlArg, rARG1);
+      loadValueDirectFixed(cUnit, rlArg, targetReg(kArg1));
       break;
     }
-    case 1: // Is "this" null? [use rARG1]
-      genNullCheck(cUnit, info->args[0].sRegLow, rARG1, info->optFlags);
-      // get this->klass_ [use rARG1, set rINVOKE_TGT]
-      loadWordDisp(cUnit, rARG1, Object::ClassOffset().Int32Value(),
-                   rINVOKE_TGT);
+    case 1: // Is "this" null? [use kArg1]
+      genNullCheck(cUnit, info->args[0].sRegLow, targetReg(kArg1), info->optFlags);
+      // get this->klass_ [use kArg1, set kInvokeTgt]
+      loadWordDisp(cUnit, targetReg(kArg1), Object::ClassOffset().Int32Value(),
+                   targetReg(kInvokeTgt));
       break;
-    case 2: // Get this->klass_->vtable [usr rINVOKE_TGT, set rINVOKE_TGT]
-      loadWordDisp(cUnit, rINVOKE_TGT, Class::VTableOffset().Int32Value(),
-                   rINVOKE_TGT);
+    case 2: // Get this->klass_->vtable [usr kInvokeTgt, set kInvokeTgt]
+      loadWordDisp(cUnit, targetReg(kInvokeTgt), Class::VTableOffset().Int32Value(),
+                   targetReg(kInvokeTgt));
       break;
-    case 3: // Get target method [use rINVOKE_TGT, set rARG0]
-      loadWordDisp(cUnit, rINVOKE_TGT, (methodIdx * 4) +
-                   Array::DataOffset(sizeof(Object*)).Int32Value(), rARG0);
+    case 3: // Get target method [use kInvokeTgt, set kArg0]
+      loadWordDisp(cUnit, targetReg(kInvokeTgt), (methodIdx * 4) +
+                   Array::DataOffset(sizeof(Object*)).Int32Value(), targetReg(kArg0));
       break;
-    case 4: // Get the compiled code address [uses rARG0, sets rINVOKE_TGT]
+    case 4: // Get the compiled code address [uses kArg0, sets kInvokeTgt]
       if (cUnit->instructionSet != kX86) {
-        loadWordDisp(cUnit, rARG0, AbstractMethod::GetCodeOffset().Int32Value(), rINVOKE_TGT);
+        loadWordDisp(cUnit, targetReg(kArg0), AbstractMethod::GetCodeOffset().Int32Value(),
+                     targetReg(kInvokeTgt));
         break;
       }
       // Intentional fallthrough for X86
@@ -287,20 +286,20 @@
 
   if (directMethod != 0) {
     switch (state) {
-      case 0:  // Load the trampoline target [sets rINVOKE_TGT].
+      case 0:  // Load the trampoline target [sets kInvokeTgt].
         if (cUnit->instructionSet != kX86) {
-          loadWordDisp(cUnit, rSELF, trampoline, rINVOKE_TGT);
+          loadWordDisp(cUnit, targetReg(kSelf), trampoline, targetReg(kInvokeTgt));
         }
-        // Get the interface Method* [sets rARG0]
+        // Get the interface Method* [sets kArg0]
         if (directMethod != (uintptr_t)-1) {
-          loadConstant(cUnit, rARG0, directMethod);
+          loadConstant(cUnit, targetReg(kArg0), directMethod);
         } else {
           LIR* dataTarget = scanLiteralPool(cUnit->methodLiteralList, dexIdx, 0);
           if (dataTarget == NULL) {
             dataTarget = addWordData(cUnit, &cUnit->methodLiteralList, dexIdx);
             dataTarget->operands[1] = kInterface;
           }
-          LIR* loadPcRel = opPcRelLoad(cUnit, rARG0, dataTarget);
+          LIR* loadPcRel = opPcRelLoad(cUnit, targetReg(kArg0), dataTarget);
           oatAppendLIR(cUnit, loadPcRel);
           DCHECK_EQ(cUnit->instructionSet, kThumb2) << (void*)dataTarget;
         }
@@ -311,22 +310,22 @@
   } else {
     switch (state) {
       case 0:
-        // Get the current Method* [sets rARG0] - TUNING: remove copy of method if it is promoted.
-        loadCurrMethodDirect(cUnit, rARG0);
-        // Load the trampoline target [sets rINVOKE_TGT].
+        // Get the current Method* [sets kArg0] - TUNING: remove copy of method if it is promoted.
+        loadCurrMethodDirect(cUnit, targetReg(kArg0));
+        // Load the trampoline target [sets kInvokeTgt].
         if (cUnit->instructionSet != kX86) {
-          loadWordDisp(cUnit, rSELF, trampoline, rINVOKE_TGT);
+          loadWordDisp(cUnit, targetReg(kSelf), trampoline, targetReg(kInvokeTgt));
         }
         break;
-    case 1:  // Get method->dex_cache_resolved_methods_ [set/use rARG0]
-      loadWordDisp(cUnit, rARG0,
+    case 1:  // Get method->dex_cache_resolved_methods_ [set/use kArg0]
+      loadWordDisp(cUnit, targetReg(kArg0),
                    AbstractMethod::DexCacheResolvedMethodsOffset().Int32Value(),
-                   rARG0);
+                   targetReg(kArg0));
       break;
-    case 2:  // Grab target method* [set/use rARG0]
-      loadWordDisp(cUnit, rARG0,
+    case 2:  // Grab target method* [set/use kArg0]
+      loadWordDisp(cUnit, targetReg(kArg0),
                    Array::DataOffset(sizeof(Object*)).Int32Value() + dexIdx * 4,
-                   rARG0);
+                   targetReg(kArg0));
       break;
     default:
       return -1;
@@ -345,10 +344,10 @@
   if (state == 0) {
     if (cUnit->instructionSet != kX86) {
       // Load trampoline target
-      loadWordDisp(cUnit, rSELF, trampoline, rINVOKE_TGT);
+      loadWordDisp(cUnit, targetReg(kSelf), trampoline, targetReg(kInvokeTgt));
     }
-    // Load rARG0 with method index
-    loadConstant(cUnit, rARG0, dexIdx);
+    // Load kArg0 with method index
+    loadConstant(cUnit, targetReg(kArg0), dexIdx);
     return 1;
   }
   return -1;
@@ -402,8 +401,8 @@
                 uint32_t methodIdx, uintptr_t directCode,
                 uintptr_t directMethod, InvokeType type, bool skipThis)
 {
-  int lastArgReg = rARG3;
-  int nextReg = rARG1;
+  int lastArgReg = targetReg(kArg3);
+  int nextReg = targetReg(kArg1);
   int nextArg = 0;
   if (skipThis) {
     nextReg++;
@@ -412,7 +411,7 @@
   for (; (nextReg <= lastArgReg) && (nextArg < info->numArgWords); nextReg++) {
     RegLocation rlArg = info->args[nextArg++];
     rlArg = oatUpdateRawLoc(cUnit, rlArg);
-    if (rlArg.wide && (nextReg <= rARG2)) {
+    if (rlArg.wide && (nextReg <= targetReg(kArg2))) {
       loadValueDirectWideFixed(cUnit, rlArg, nextReg, nextReg + 1);
       nextReg++;
       nextArg++;
@@ -428,7 +427,7 @@
 
 /*
  * Load up to 5 arguments, the first three of which will be in
- * rARG1 .. rARG3.  On entry rARG0 contains the current method pointer,
+ * kArg1 .. kArg3.  On entry kArg0 contains the current method pointer,
  * and as part of the load sequence, it must be replaced with
  * the target method pointer.  Note, this may also be called
  * for "range" variants if the number of arguments is 5 or fewer.
@@ -464,14 +463,14 @@
       if (rlArg.location == kLocPhysReg) {
         reg = rlArg.highReg;
       } else {
-        // rARG2 & rARG3 can safely be used here
-        reg = rARG3;
-        loadWordDisp(cUnit, rSP, oatSRegOffset(cUnit, rlArg.sRegLow) + 4, reg);
+        // kArg2 & rArg3 can safely be used here
+        reg = targetReg(kArg3);
+        loadWordDisp(cUnit, targetReg(kSp), oatSRegOffset(cUnit, rlArg.sRegLow) + 4, reg);
         callState = nextCallInsn(cUnit, info, callState, dexIdx,
                                  methodIdx, directCode, directMethod, type);
       }
-      storeBaseDisp(cUnit, rSP, (nextUse + 1) * 4, reg, kWord);
-      storeBaseDisp(cUnit, rSP, 16 /* (3+1)*4 */, reg, kWord);
+      storeBaseDisp(cUnit, targetReg(kSp), (nextUse + 1) * 4, reg, kWord);
+      storeBaseDisp(cUnit, targetReg(kSp), 16 /* (3+1)*4 */, reg, kWord);
       callState = nextCallInsn(cUnit, info, callState, dexIdx, methodIdx,
                                directCode, directMethod, type);
       nextUse++;
@@ -486,9 +485,9 @@
         lowReg = rlArg.lowReg;
         highReg = rlArg.highReg;
       } else {
-        lowReg = rARG2;
+        lowReg = targetReg(kArg2);
         if (rlArg.wide) {
-          highReg = rARG3;
+          highReg = targetReg(kArg3);
           loadValueDirectWideFixed(cUnit, rlArg, lowReg, highReg);
         } else {
           loadValueDirectFixed(cUnit, rlArg, lowReg);
@@ -498,10 +497,10 @@
       }
       int outsOffset = (nextUse + 1) * 4;
       if (rlArg.wide) {
-        storeBaseDispWide(cUnit, rSP, outsOffset, lowReg, highReg);
+        storeBaseDispWide(cUnit, targetReg(kSp), outsOffset, lowReg, highReg);
         nextUse += 2;
       } else {
-        storeWordDisp(cUnit, rSP, outsOffset, lowReg);
+        storeWordDisp(cUnit, targetReg(kSp), outsOffset, lowReg);
         nextUse++;
       }
       callState = nextCallInsn(cUnit, info, callState, dexIdx, methodIdx,
@@ -514,7 +513,7 @@
                           type, skipThis);
 
   if (pcrLabel) {
-    *pcrLabel = genNullCheck(cUnit, info->args[0].sRegLow, rARG1,
+    *pcrLabel = genNullCheck(cUnit, info->args[0].sRegLow, targetReg(kArg1),
                              info->optFlags);
   }
   return callState;
@@ -529,10 +528,10 @@
  * Two general strategies:
  *    If < 20 arguments
  *       Pass args 3-18 using vldm/vstm block copy
- *       Pass arg0, arg1 & arg2 in rARG1-rARG3
+ *       Pass arg0, arg1 & arg2 in kArg1-kArg3
  *    If 20+ arguments
  *       Pass args arg19+ using memcpy block copy
- *       Pass arg0, arg1 & arg2 in rARG1-rARG3
+ *       Pass arg0, arg1 & arg2 in kArg1-kArg3
  *
  */
 int genDalvikArgsRange(CompilationUnit* cUnit, CallInfo* info, int callState,
@@ -559,14 +558,14 @@
     if (loc.wide) {
       loc = oatUpdateLocWide(cUnit, loc);
       if ((nextArg >= 2) && (loc.location == kLocPhysReg)) {
-        storeBaseDispWide(cUnit, rSP, oatSRegOffset(cUnit, loc.sRegLow),
+        storeBaseDispWide(cUnit, targetReg(kSp), oatSRegOffset(cUnit, loc.sRegLow),
                           loc.lowReg, loc.highReg);
       }
       nextArg += 2;
     } else {
       loc = oatUpdateLoc(cUnit, loc);
       if ((nextArg >= 3) && (loc.location == kLocPhysReg)) {
-        storeBaseDisp(cUnit, rSP, oatSRegOffset(cUnit, loc.sRegLow),
+        storeBaseDisp(cUnit, targetReg(kSp), oatSRegOffset(cUnit, loc.sRegLow),
                       loc.lowReg, kWord);
       }
       nextArg++;
@@ -577,33 +576,33 @@
   int outsOffset = 4 /* Method* */ + (3 * 4);
   if (cUnit->instructionSet != kThumb2) {
     // Generate memcpy
-    opRegRegImm(cUnit, kOpAdd, rARG0, rSP, outsOffset);
-    opRegRegImm(cUnit, kOpAdd, rARG1, rSP, startOffset);
-    callRuntimeHelperRegRegImm(cUnit, ENTRYPOINT_OFFSET(pMemcpy),
-                               rARG0, rARG1, (info->numArgWords - 3) * 4, false);
+    opRegRegImm(cUnit, kOpAdd, targetReg(kArg0), targetReg(kSp), outsOffset);
+    opRegRegImm(cUnit, kOpAdd, targetReg(kArg1), targetReg(kSp), startOffset);
+    callRuntimeHelperRegRegImm(cUnit, ENTRYPOINT_OFFSET(pMemcpy), targetReg(kArg0),
+                               targetReg(kArg1), (info->numArgWords - 3) * 4, false);
   } else {
     if (info->numArgWords >= 20) {
       // Generate memcpy
-      opRegRegImm(cUnit, kOpAdd, rARG0, rSP, outsOffset);
-      opRegRegImm(cUnit, kOpAdd, rARG1, rSP, startOffset);
-      callRuntimeHelperRegRegImm(cUnit, ENTRYPOINT_OFFSET(pMemcpy),
-                                 rARG0, rARG1, (info->numArgWords - 3) * 4, false);
+      opRegRegImm(cUnit, kOpAdd, targetReg(kArg0), targetReg(kSp), outsOffset);
+      opRegRegImm(cUnit, kOpAdd, targetReg(kArg1), targetReg(kSp), startOffset);
+      callRuntimeHelperRegRegImm(cUnit, ENTRYPOINT_OFFSET(pMemcpy), targetReg(kArg0),
+                                 targetReg(kArg1), (info->numArgWords - 3) * 4, false);
     } else {
-      // Use vldm/vstm pair using rARG3 as a temp
+      // Use vldm/vstm pair using kArg3 as a temp
       int regsLeft = std::min(info->numArgWords - 3, 16);
       callState = nextCallInsn(cUnit, info, callState, dexIdx, methodIdx,
                                directCode, directMethod, type);
-      opRegRegImm(cUnit, kOpAdd, rARG3, rSP, startOffset);
-      LIR* ld = opVldm(cUnit, rARG3, regsLeft);
+      opRegRegImm(cUnit, kOpAdd, targetReg(kArg3), targetReg(kSp), startOffset);
+      LIR* ld = opVldm(cUnit, targetReg(kArg3), regsLeft);
       //TUNING: loosen barrier
       ld->defMask = ENCODE_ALL;
       setMemRefType(ld, true /* isLoad */, kDalvikReg);
       callState = nextCallInsn(cUnit, info, callState, dexIdx, methodIdx,
                                directCode, directMethod, type);
-      opRegRegImm(cUnit, kOpAdd, rARG3, rSP, 4 /* Method* */ + (3 * 4));
+      opRegRegImm(cUnit, kOpAdd, targetReg(kArg3), targetReg(kSp), 4 /* Method* */ + (3 * 4));
       callState = nextCallInsn(cUnit, info, callState, dexIdx, methodIdx,
                                directCode, directMethod, type);
-      LIR* st = opVstm(cUnit, rARG3, regsLeft);
+      LIR* st = opVstm(cUnit, targetReg(kArg3), regsLeft);
       setMemRefType(st, false /* isLoad */, kDalvikReg);
       st->defMask = ENCODE_ALL;
       callState = nextCallInsn(cUnit, info, callState, dexIdx, methodIdx,
@@ -618,7 +617,7 @@
   callState = nextCallInsn(cUnit, info, callState, dexIdx, methodIdx,
                            directCode, directMethod, type);
   if (pcrLabel) {
-    *pcrLabel = genNullCheck(cUnit, info->args[0].sRegLow, rARG1,
+    *pcrLabel = genNullCheck(cUnit, info->args[0].sRegLow, targetReg(kArg1),
                              info->optFlags);
   }
   return callState;
@@ -854,9 +853,9 @@
   }
   oatClobberCalleeSave(cUnit);
   oatLockCallTemps(cUnit);  // Using fixed registers
-  int regPtr = rARG0;
-  int regChar = rARG1;
-  int regStart = rARG2;
+  int regPtr = targetReg(kArg0);
+  int regChar = targetReg(kArg1);
+  int regStart = targetReg(kArg2);
 
   RegLocation rlObj = info->args[0];
   RegLocation rlChar = info->args[1];
@@ -899,8 +898,8 @@
   }
   oatClobberCalleeSave(cUnit);
   oatLockCallTemps(cUnit);  // Using fixed registers
-  int regThis = rARG0;
-  int regCmp = rARG1;
+  int regThis = targetReg(kArg0);
+  int regCmp = targetReg(kArg1);
 
   RegLocation rlThis = info->args[0];
   RegLocation rlCmp = info->args[1];
diff --git a/src/compiler/codegen/LocalOptimizations.cc b/src/compiler/codegen/LocalOptimizations.cc
index d2275aa..2688d65 100644
--- a/src/compiler/codegen/LocalOptimizations.cc
+++ b/src/compiler/codegen/LocalOptimizations.cc
@@ -151,7 +151,7 @@
           DCHECK(!(EncodingMap[checkLIR->opcode].flags & IS_STORE));
           /* Same value && same register type */
           if (checkLIR->aliasInfo == thisLIR->aliasInfo &&
-            REGTYPE(checkLIR->operands[0]) == REGTYPE(nativeRegId)) {
+              sameRegType(checkLIR->operands[0], nativeRegId)) {
             /*
              * Different destination register - insert
              * a move
@@ -166,8 +166,7 @@
           /* Must alias */
           if (checkLIR->aliasInfo == thisLIR->aliasInfo) {
             /* Only optimize compatible registers */
-            bool regCompatible =
-                REGTYPE(checkLIR->operands[0]) == REGTYPE(nativeRegId);
+            bool regCompatible = sameRegType(checkLIR->operands[0], nativeRegId);
             if ((isThisLIRLoad && isCheckLIRLoad) ||
                 (!isThisLIRLoad && isCheckLIRLoad)) {
               /* RAR or RAW */
diff --git a/src/compiler/codegen/MethodCodegenDriver.cc b/src/compiler/codegen/MethodCodegenDriver.cc
index 8fd6045..3170abc 100644
--- a/src/compiler/codegen/MethodCodegenDriver.cc
+++ b/src/compiler/codegen/MethodCodegenDriver.cc
@@ -25,8 +25,8 @@
 /* Mark register usage state and return long retloc */
 RegLocation oatGetReturnWide(CompilationUnit* cUnit, bool isDouble)
 {
-  RegLocation gpr_res = LOC_C_RETURN_WIDE;
-  RegLocation fpr_res = LOC_C_RETURN_WIDE_DOUBLE;
+  RegLocation gpr_res = locCReturnWide();
+  RegLocation fpr_res = locCReturnDouble();
   RegLocation res = isDouble ? fpr_res : gpr_res;
   oatClobber(cUnit, res.lowReg);
   oatClobber(cUnit, res.highReg);
@@ -38,8 +38,8 @@
 
 RegLocation oatGetReturn(CompilationUnit* cUnit, bool isFloat)
 {
-  RegLocation gpr_res = LOC_C_RETURN;
-  RegLocation fpr_res = LOC_C_RETURN_FLOAT;
+  RegLocation gpr_res = locCReturn();
+  RegLocation fpr_res = locCReturnFloat();
   RegLocation res = isFloat ? fpr_res : gpr_res;
   oatClobber(cUnit, res.lowReg);
   if (cUnit->instructionSet == kMips) {
@@ -126,10 +126,11 @@
   }
   LIR* callInst;
   if (cUnit->instructionSet != kX86) {
-    callInst = opReg(cUnit, kOpBlx, rINVOKE_TGT);
+    callInst = opReg(cUnit, kOpBlx, targetReg(kInvokeTgt));
   } else {
     if (fastPath && info->type != kInterface) {
-      callInst = opMem(cUnit, kOpBlx, rARG0, AbstractMethod::GetCodeOffset().Int32Value());
+      callInst = opMem(cUnit, kOpBlx, targetReg(kArg0),
+                       AbstractMethod::GetCodeOffset().Int32Value());
     } else {
       int trampoline = 0;
       switch (info->type) {
diff --git a/src/compiler/codegen/arm/ArchFactory.cc b/src/compiler/codegen/arm/ArchFactory.cc
index f85bd2f..f75d8e3 100644
--- a/src/compiler/codegen/arm/ArchFactory.cc
+++ b/src/compiler/codegen/arm/ArchFactory.cc
@@ -44,8 +44,8 @@
 
 int loadHelper(CompilationUnit* cUnit, int offset)
 {
-  loadWordDisp(cUnit, rSELF, offset, rLR);
-  return rLR;
+  loadWordDisp(cUnit, rARM_SELF, offset, rARM_LR);
+  return rARM_LR;
 }
 
 void genEntrySequence(CompilationUnit* cUnit, RegLocation* argLocs,
@@ -73,7 +73,7 @@
   newLIR0(cUnit, kPseudoMethodEntry);
   if (!skipOverflowCheck) {
     /* Load stack limit */
-    loadWordDisp(cUnit, rSELF, Thread::StackEndOffset().Int32Value(), r12);
+    loadWordDisp(cUnit, rARM_SELF, Thread::StackEndOffset().Int32Value(), r12);
   }
   /* Spill core callee saves */
   newLIR1(cUnit, kThumb2Push, cUnit->coreSpillMask);
@@ -87,11 +87,11 @@
     newLIR1(cUnit, kThumb2VPushCS, cUnit->numFPSpills);
   }
   if (!skipOverflowCheck) {
-    opRegRegImm(cUnit, kOpSub, rLR, rSP, cUnit->frameSize - (spillCount * 4));
-    genRegRegCheck(cUnit, kCondCc, rLR, r12, kThrowStackOverflow);
-    opRegCopy(cUnit, rSP, rLR);     // Establish stack
+    opRegRegImm(cUnit, kOpSub, rARM_LR, rARM_SP, cUnit->frameSize - (spillCount * 4));
+    genRegRegCheck(cUnit, kCondCc, rARM_LR, r12, kThrowStackOverflow);
+    opRegCopy(cUnit, rARM_SP, rARM_LR);     // Establish stack
   } else {
-    opRegImm(cUnit, kOpSub, rSP, cUnit->frameSize - (spillCount * 4));
+    opRegImm(cUnit, kOpSub, rARM_SP, cUnit->frameSize - (spillCount * 4));
   }
 
   flushIns(cUnit, argLocs, rlMethod);
@@ -113,20 +113,20 @@
   oatLockTemp(cUnit, r1);
 
   newLIR0(cUnit, kPseudoMethodExit);
-  opRegImm(cUnit, kOpAdd, rSP, cUnit->frameSize - (spillCount * 4));
+  opRegImm(cUnit, kOpAdd, rARM_SP, cUnit->frameSize - (spillCount * 4));
   /* Need to restore any FP callee saves? */
   if (cUnit->numFPSpills) {
     newLIR1(cUnit, kThumb2VPopCS, cUnit->numFPSpills);
   }
-  if (cUnit->coreSpillMask & (1 << rLR)) {
-    /* Unspill rLR to rPC */
-    cUnit->coreSpillMask &= ~(1 << rLR);
-    cUnit->coreSpillMask |= (1 << rPC);
+  if (cUnit->coreSpillMask & (1 << rARM_LR)) {
+    /* Unspill rARM_LR to rARM_PC */
+    cUnit->coreSpillMask &= ~(1 << rARM_LR);
+    cUnit->coreSpillMask |= (1 << rARM_PC);
   }
   newLIR1(cUnit, kThumb2Pop, cUnit->coreSpillMask);
-  if (!(cUnit->coreSpillMask & (1 << rPC))) {
-    /* We didn't pop to rPC, so must do a bv rLR */
-    newLIR1(cUnit, kThumbBx, rLR);
+  if (!(cUnit->coreSpillMask & (1 << rARM_PC))) {
+    /* We didn't pop to rARM_PC, so must do a bv rARM_LR */
+    newLIR1(cUnit, kThumbBx, rARM_LR);
   }
 }
 
diff --git a/src/compiler/codegen/arm/ArchUtility.cc b/src/compiler/codegen/arm/ArchUtility.cc
index 8746b68..2d4b314 100644
--- a/src/compiler/codegen/arm/ArchUtility.cc
+++ b/src/compiler/codegen/arm/ArchUtility.cc
@@ -22,6 +22,92 @@
 
 namespace art {
 
+RegLocation locCReturn()
+{
+  RegLocation res = ARM_LOC_C_RETURN;
+  return res;
+}
+
+RegLocation locCReturnWide()
+{
+  RegLocation res = ARM_LOC_C_RETURN_WIDE;
+  return res;
+}
+
+RegLocation locCReturnFloat()
+{
+  RegLocation res = ARM_LOC_C_RETURN_FLOAT;
+  return res;
+}
+
+RegLocation locCReturnDouble()
+{
+  RegLocation res = ARM_LOC_C_RETURN_DOUBLE;
+  return res;
+}
+
+// Return a target-dependent special register.
+int targetReg(SpecialTargetRegister reg) {
+  int res = INVALID_REG;
+  switch (reg) {
+    case kSelf: res = rARM_SELF; break;
+    case kSuspend: res =  rARM_SUSPEND; break;
+    case kLr: res =  rARM_LR; break;
+    case kPc: res =  rARM_PC; break;
+    case kSp: res =  rARM_SP; break;
+    case kArg0: res = rARM_ARG0; break;
+    case kArg1: res = rARM_ARG1; break;
+    case kArg2: res = rARM_ARG2; break;
+    case kArg3: res = rARM_ARG3; break;
+    case kFArg0: res = rARM_FARG0; break;
+    case kFArg1: res = rARM_FARG1; break;
+    case kFArg2: res = rARM_FARG2; break;
+    case kFArg3: res = rARM_FARG3; break;
+    case kRet0: res = rARM_RET0; break;
+    case kRet1: res = rARM_RET1; break;
+    case kInvokeTgt: res = rARM_INVOKE_TGT; break;
+    case kCount: res = rARM_COUNT; break;
+  }
+  return res;
+}
+
+
+// Create a double from a pair of singles.
+int s2d(int lowReg, int highReg)
+{
+  return ARM_S2D(lowReg, highReg);
+}
+
+// Is reg a single or double?
+bool fpReg(int reg)
+{
+  return ARM_FPREG(reg);
+}
+
+// Is reg a single?
+bool singleReg(int reg)
+{
+  return ARM_SINGLEREG(reg);
+}
+
+// Is reg a double?
+bool doubleReg(int reg)
+{
+  return ARM_DOUBLEREG(reg);
+}
+
+// Return mask to strip off fp reg flags and bias.
+uint32_t fpRegMask()
+{
+  return ARM_FP_REG_MASK;
+}
+
+// True if both regs single, both core or both double.
+bool sameRegType(int reg1, int reg2)
+{
+  return (ARM_REGTYPE(reg1) == ARM_REGTYPE(reg2));
+}
+
 /*
  * Decode the register id.
  */
@@ -34,9 +120,9 @@
 
   regId = reg & 0x1f;
   /* Each double register is equal to a pair of single-precision FP registers */
-  seed = DOUBLEREG(reg) ? 3 : 1;
+  seed = ARM_DOUBLEREG(reg) ? 3 : 1;
   /* FP register starts at bit position 16 */
-  shift = FPREG(reg) ? kArmFPReg0 : 0;
+  shift = ARM_FPREG(reg) ? kArmFPReg0 : 0;
   /* Expand the double register id into single offset */
   shift += regId;
   return (seed << shift);
@@ -306,10 +392,10 @@
              sprintf(tbuf,"%d [%#x]", operand, operand);
              break;
            case 's':
-             sprintf(tbuf,"s%d",operand & FP_REG_MASK);
+             sprintf(tbuf,"s%d",operand & ARM_FP_REG_MASK);
              break;
            case 'S':
-             sprintf(tbuf,"d%d",(operand & FP_REG_MASK) >> 1);
+             sprintf(tbuf,"d%d",(operand & ARM_FP_REG_MASK) >> 1);
              break;
            case 'h':
              sprintf(tbuf,"%04x", operand);
diff --git a/src/compiler/codegen/arm/ArmLIR.h b/src/compiler/codegen/arm/ArmLIR.h
index 05082ed..7eebc83 100644
--- a/src/compiler/codegen/arm/ArmLIR.h
+++ b/src/compiler/codegen/arm/ArmLIR.h
@@ -30,12 +30,12 @@
  *        pointer in r0 as a hidden arg0. Otherwise used as codegen scratch
  *        registers.
  * r0-r1: As in C/C++ r0 is 32-bit return register and r0/r1 is 64-bit
- * r4   : (rSUSPEND) is reserved (suspend check/debugger assist)
+ * r4   : (rARM_SUSPEND) is reserved (suspend check/debugger assist)
  * r5   : Callee save (promotion target)
  * r6   : Callee save (promotion target)
  * r7   : Callee save (promotion target)
  * r8   : Callee save (promotion target)
- * r9   : (rSELF) is reserved (pointer to thread-local storage)
+ * r9   : (rARM_SELF) is reserved (pointer to thread-local storage)
  * r10  : Callee save (promotion target)
  * r11  : Callee save (promotion target)
  * r12  : Scratch, may be trashed by linkage stubs
@@ -95,17 +95,17 @@
  */
 
 /* Offset to distingish FP regs */
-#define FP_REG_OFFSET 32
+#define ARM_FP_REG_OFFSET 32
 /* Offset to distinguish DP FP regs */
-#define FP_DOUBLE 64
+#define ARM_FP_DOUBLE 64
 /* First FP callee save */
-#define FP_CALLEE_SAVE_BASE 16
+#define ARM_FP_CALLEE_SAVE_BASE 16
 /* Reg types */
-#define REGTYPE(x) (x & (FP_REG_OFFSET | FP_DOUBLE))
-#define FPREG(x) ((x & FP_REG_OFFSET) == FP_REG_OFFSET)
-#define LOWREG(x) ((x & 0x7) == x)
-#define DOUBLEREG(x) ((x & FP_DOUBLE) == FP_DOUBLE)
-#define SINGLEREG(x) (FPREG(x) && !DOUBLEREG(x))
+#define ARM_REGTYPE(x) (x & (ARM_FP_REG_OFFSET | ARM_FP_DOUBLE))
+#define ARM_FPREG(x) ((x & ARM_FP_REG_OFFSET) == ARM_FP_REG_OFFSET)
+#define ARM_LOWREG(x) ((x & 0x7) == x)
+#define ARM_DOUBLEREG(x) ((x & ARM_FP_DOUBLE) == ARM_FP_DOUBLE)
+#define ARM_SINGLEREG(x) (ARM_FPREG(x) && !ARM_DOUBLEREG(x))
 /*
  * Note: the low register of a floating point pair is sufficient to
  * create the name of a double, but require both names to be passed to
@@ -113,21 +113,17 @@
  * rework is done in this area.  Also, it is a good reminder in the calling
  * code that reg locations always describe doubles as a pair of singles.
  */
-#define S2D(x,y) ((x) | FP_DOUBLE)
+#define ARM_S2D(x,y) ((x) | ARM_FP_DOUBLE)
 /* Mask to strip off fp flags */
-#define FP_REG_MASK (FP_REG_OFFSET-1)
-/* non-existent Dalvik register */
-#define vNone   (-1)
-/* non-existant physical register */
-#define rNone   (-1)
+#define ARM_FP_REG_MASK (ARM_FP_REG_OFFSET-1)
 
 /* RegisterLocation templates return values (r0, or r0/r1) */
-#define LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r0, INVALID_REG,\
-                      INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1, \
-                      INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_FLOAT  LOC_C_RETURN
-#define LOC_C_RETURN_WIDE_DOUBLE  LOC_C_RETURN_WIDE
+#define ARM_LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r0, INVALID_REG,\
+                          INVALID_SREG, INVALID_SREG}
+#define ARM_LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1, \
+                               INVALID_SREG, INVALID_SREG}
+#define ARM_LOC_C_RETURN_FLOAT  ARM_LOC_C_RETURN
+#define ARM_LOC_C_RETURN_DOUBLE  ARM_LOC_C_RETURN_WIDE
 
 enum ArmResourceEncodingPos {
   kArmGPReg0   = 0,
@@ -145,95 +141,89 @@
 #define ENCODE_ARM_REG_PC           (1ULL << kArmRegPC)
 #define ENCODE_ARM_REG_FPCS_LIST(N) ((u8)N << kArmFPReg16)
 
-/*
- * Annotate special-purpose core registers:
- *   - ARM architecture: r13sp, r14lr, and r15pc
- *
- * rPC, rFP, and rSELF are for architecture-independent code to use.
- */
-enum NativeRegisterPool {
+enum ArmNativeRegisterPool {
   r0   = 0,
   r1   = 1,
   r2   = 2,
   r3   = 3,
-  rSUSPEND = 4,
+  rARM_SUSPEND = 4,
   r5   = 5,
   r6   = 6,
   r7   = 7,
   r8   = 8,
-  rSELF  = 9,
+  rARM_SELF  = 9,
   r10  = 10,
   r11  = 11,
   r12  = 12,
   r13sp  = 13,
-  rSP  = 13,
+  rARM_SP  = 13,
   r14lr  = 14,
-  rLR  = 14,
+  rARM_LR  = 14,
   r15pc  = 15,
-  rPC  = 15,
-  fr0  =  0 + FP_REG_OFFSET,
-  fr1  =  1 + FP_REG_OFFSET,
-  fr2  =  2 + FP_REG_OFFSET,
-  fr3  =  3 + FP_REG_OFFSET,
-  fr4  =  4 + FP_REG_OFFSET,
-  fr5  =  5 + FP_REG_OFFSET,
-  fr6  =  6 + FP_REG_OFFSET,
-  fr7  =  7 + FP_REG_OFFSET,
-  fr8  =  8 + FP_REG_OFFSET,
-  fr9  =  9 + FP_REG_OFFSET,
-  fr10 = 10 + FP_REG_OFFSET,
-  fr11 = 11 + FP_REG_OFFSET,
-  fr12 = 12 + FP_REG_OFFSET,
-  fr13 = 13 + FP_REG_OFFSET,
-  fr14 = 14 + FP_REG_OFFSET,
-  fr15 = 15 + FP_REG_OFFSET,
-  fr16 = 16 + FP_REG_OFFSET,
-  fr17 = 17 + FP_REG_OFFSET,
-  fr18 = 18 + FP_REG_OFFSET,
-  fr19 = 19 + FP_REG_OFFSET,
-  fr20 = 20 + FP_REG_OFFSET,
-  fr21 = 21 + FP_REG_OFFSET,
-  fr22 = 22 + FP_REG_OFFSET,
-  fr23 = 23 + FP_REG_OFFSET,
-  fr24 = 24 + FP_REG_OFFSET,
-  fr25 = 25 + FP_REG_OFFSET,
-  fr26 = 26 + FP_REG_OFFSET,
-  fr27 = 27 + FP_REG_OFFSET,
-  fr28 = 28 + FP_REG_OFFSET,
-  fr29 = 29 + FP_REG_OFFSET,
-  fr30 = 30 + FP_REG_OFFSET,
-  fr31 = 31 + FP_REG_OFFSET,
-  dr0 = fr0 + FP_DOUBLE,
-  dr1 = fr2 + FP_DOUBLE,
-  dr2 = fr4 + FP_DOUBLE,
-  dr3 = fr6 + FP_DOUBLE,
-  dr4 = fr8 + FP_DOUBLE,
-  dr5 = fr10 + FP_DOUBLE,
-  dr6 = fr12 + FP_DOUBLE,
-  dr7 = fr14 + FP_DOUBLE,
-  dr8 = fr16 + FP_DOUBLE,
-  dr9 = fr18 + FP_DOUBLE,
-  dr10 = fr20 + FP_DOUBLE,
-  dr11 = fr22 + FP_DOUBLE,
-  dr12 = fr24 + FP_DOUBLE,
-  dr13 = fr26 + FP_DOUBLE,
-  dr14 = fr28 + FP_DOUBLE,
-  dr15 = fr30 + FP_DOUBLE,
+  rARM_PC  = 15,
+  fr0  =  0 + ARM_FP_REG_OFFSET,
+  fr1  =  1 + ARM_FP_REG_OFFSET,
+  fr2  =  2 + ARM_FP_REG_OFFSET,
+  fr3  =  3 + ARM_FP_REG_OFFSET,
+  fr4  =  4 + ARM_FP_REG_OFFSET,
+  fr5  =  5 + ARM_FP_REG_OFFSET,
+  fr6  =  6 + ARM_FP_REG_OFFSET,
+  fr7  =  7 + ARM_FP_REG_OFFSET,
+  fr8  =  8 + ARM_FP_REG_OFFSET,
+  fr9  =  9 + ARM_FP_REG_OFFSET,
+  fr10 = 10 + ARM_FP_REG_OFFSET,
+  fr11 = 11 + ARM_FP_REG_OFFSET,
+  fr12 = 12 + ARM_FP_REG_OFFSET,
+  fr13 = 13 + ARM_FP_REG_OFFSET,
+  fr14 = 14 + ARM_FP_REG_OFFSET,
+  fr15 = 15 + ARM_FP_REG_OFFSET,
+  fr16 = 16 + ARM_FP_REG_OFFSET,
+  fr17 = 17 + ARM_FP_REG_OFFSET,
+  fr18 = 18 + ARM_FP_REG_OFFSET,
+  fr19 = 19 + ARM_FP_REG_OFFSET,
+  fr20 = 20 + ARM_FP_REG_OFFSET,
+  fr21 = 21 + ARM_FP_REG_OFFSET,
+  fr22 = 22 + ARM_FP_REG_OFFSET,
+  fr23 = 23 + ARM_FP_REG_OFFSET,
+  fr24 = 24 + ARM_FP_REG_OFFSET,
+  fr25 = 25 + ARM_FP_REG_OFFSET,
+  fr26 = 26 + ARM_FP_REG_OFFSET,
+  fr27 = 27 + ARM_FP_REG_OFFSET,
+  fr28 = 28 + ARM_FP_REG_OFFSET,
+  fr29 = 29 + ARM_FP_REG_OFFSET,
+  fr30 = 30 + ARM_FP_REG_OFFSET,
+  fr31 = 31 + ARM_FP_REG_OFFSET,
+  dr0 = fr0 + ARM_FP_DOUBLE,
+  dr1 = fr2 + ARM_FP_DOUBLE,
+  dr2 = fr4 + ARM_FP_DOUBLE,
+  dr3 = fr6 + ARM_FP_DOUBLE,
+  dr4 = fr8 + ARM_FP_DOUBLE,
+  dr5 = fr10 + ARM_FP_DOUBLE,
+  dr6 = fr12 + ARM_FP_DOUBLE,
+  dr7 = fr14 + ARM_FP_DOUBLE,
+  dr8 = fr16 + ARM_FP_DOUBLE,
+  dr9 = fr18 + ARM_FP_DOUBLE,
+  dr10 = fr20 + ARM_FP_DOUBLE,
+  dr11 = fr22 + ARM_FP_DOUBLE,
+  dr12 = fr24 + ARM_FP_DOUBLE,
+  dr13 = fr26 + ARM_FP_DOUBLE,
+  dr14 = fr28 + ARM_FP_DOUBLE,
+  dr15 = fr30 + ARM_FP_DOUBLE,
 };
 
 /* Target-independent aliases */
-#define rARG0 r0
-#define rARG1 r1
-#define rARG2 r2
-#define rARG3 r3
-#define rFARG0 r0
-#define rFARG1 r1
-#define rFARG2 r2
-#define rFARG3 r3
-#define rRET0 r0
-#define rRET1 r1
-#define rINVOKE_TGT rLR
-#define rCOUNT INVALID_REG
+#define rARM_ARG0 r0
+#define rARM_ARG1 r1
+#define rARM_ARG2 r2
+#define rARM_ARG3 r3
+#define rARM_FARG0 r0
+#define rARM_FARG1 r1
+#define rARM_FARG2 r2
+#define rARM_FARG3 r3
+#define rARM_RET0 r0
+#define rARM_RET1 r1
+#define rARM_INVOKE_TGT rARM_LR
+#define rARM_COUNT INVALID_REG
 
 /* Shift encodings */
 enum ArmShiftEncodings {
diff --git a/src/compiler/codegen/arm/ArmRallocUtil.cc b/src/compiler/codegen/arm/ArmRallocUtil.cc
index bf7c1c7..05fe7fa 100644
--- a/src/compiler/codegen/arm/ArmRallocUtil.cc
+++ b/src/compiler/codegen/arm/ArmRallocUtil.cc
@@ -35,7 +35,7 @@
 
 void oatAdjustSpillMask(CompilationUnit* cUnit)
 {
-  cUnit->coreSpillMask |= (1 << rLR);
+  cUnit->coreSpillMask |= (1 << rARM_LR);
   cUnit->numCoreSpills++;
 }
 
@@ -47,8 +47,8 @@
  */
 void oatMarkPreservedSingle(CompilationUnit* cUnit, int vReg, int reg)
 {
-  DCHECK_GE(reg, FP_REG_MASK + FP_CALLEE_SAVE_BASE);
-  reg = (reg & FP_REG_MASK) - FP_CALLEE_SAVE_BASE;
+  DCHECK_GE(reg, ARM_FP_REG_MASK + ARM_FP_CALLEE_SAVE_BASE);
+  reg = (reg & ARM_FP_REG_MASK) - ARM_FP_CALLEE_SAVE_BASE;
   // Ensure fpVmapTable is large enough
   int tableSize = cUnit->fpVmapTable.size();
   for (int i = tableSize; i < (reg + 1); i++) {
@@ -58,7 +58,7 @@
   cUnit->fpVmapTable[reg] = vReg;
   // Size of fpVmapTable is high-water mark, use to set mask
   cUnit->numFPSpills = cUnit->fpVmapTable.size();
-  cUnit->fpSpillMask = ((1 << cUnit->numFPSpills) - 1) << FP_CALLEE_SAVE_BASE;
+  cUnit->fpSpillMask = ((1 << cUnit->numFPSpills) - 1) << ARM_FP_CALLEE_SAVE_BASE;
 }
 
 void oatFlushRegWide(CompilationUnit* cUnit, int reg1, int reg2)
@@ -80,7 +80,7 @@
       SRegToVReg(cUnit, info1->sReg))
       info1 = info2;
     int vReg = SRegToVReg(cUnit, info1->sReg);
-    oatFlushRegWideImpl(cUnit, rSP, oatVRegOffset(cUnit, vReg),
+    oatFlushRegWideImpl(cUnit, rARM_SP, oatVRegOffset(cUnit, vReg),
                         info1->reg, info1->partner);
   }
 }
@@ -91,17 +91,17 @@
   if (info->live && info->dirty) {
     info->dirty = false;
     int vReg = SRegToVReg(cUnit, info->sReg);
-    oatFlushRegImpl(cUnit, rSP, oatVRegOffset(cUnit, vReg), reg, kWord);
+    oatFlushRegImpl(cUnit, rARM_SP, oatVRegOffset(cUnit, vReg), reg, kWord);
   }
 }
 
 /* Give access to the target-dependent FP register encoding to common code */
 bool oatIsFpReg(int reg) {
-  return FPREG(reg);
+  return ARM_FPREG(reg);
 }
 
 uint32_t oatFpRegMask() {
-  return FP_REG_MASK;
+  return ARM_FP_REG_MASK;
 }
 
 /* Clobber all regs that might be used by an external C call */
@@ -133,7 +133,7 @@
 
 extern RegLocation oatGetReturnWideAlt(CompilationUnit* cUnit)
 {
-  RegLocation res = LOC_C_RETURN_WIDE;
+  RegLocation res = locCReturnWide();
   res.lowReg = r2;
   res.highReg = r3;
   oatClobber(cUnit, r2);
@@ -146,7 +146,7 @@
 
 extern RegLocation oatGetReturnAlt(CompilationUnit* cUnit)
 {
-  RegLocation res = LOC_C_RETURN;
+  RegLocation res = locCReturn();
   res.lowReg = r1;
   oatClobber(cUnit, r1);
   oatMarkInUse(cUnit, r1);
@@ -155,7 +155,7 @@
 
 extern RegisterInfo* oatGetRegInfo(CompilationUnit* cUnit, int reg)
 {
-  return FPREG(reg) ? &cUnit->regPool->FPRegs[reg & FP_REG_MASK]
+  return ARM_FPREG(reg) ? &cUnit->regPool->FPRegs[reg & ARM_FP_REG_MASK]
       : &cUnit->regPool->coreRegs[reg];
 }
 
diff --git a/src/compiler/codegen/arm/Assemble.cc b/src/compiler/codegen/arm/Assemble.cc
index 759ffd3..765a8ff 100644
--- a/src/compiler/codegen/arm/Assemble.cc
+++ b/src/compiler/codegen/arm/Assemble.cc
@@ -1051,12 +1051,12 @@
             ((lir->opcode == kThumb2Vldrs) && (delta > 1020)) ||
             ((lir->opcode == kThumb2Vldrd) && (delta > 1020))) {
           /*
-           * Note: because rLR may be used to fix up out-of-range
+           * Note: because rARM_LR may be used to fix up out-of-range
            * vldrs/vldrd we include REG_DEF_LR in the resource
            * masks for these instructions.
            */
           int baseReg = (lir->opcode == kThumb2LdrPcRel12) ?
-            lir->operands[0] : rLR;
+            lir->operands[0] : rARM_LR;
 
           // Add new Adr to generate the address
           LIR* newAdr = rawLIR(cUnit, lir->dalvikOffset, kThumb2Adr,
@@ -1219,7 +1219,7 @@
                      0, lir->target);
           oatInsertLIRBefore((LIR*)lir, (LIR*)newMov16H);
           lir->opcode = kThumb2AddRRR;
-          lir->operands[1] = rPC;
+          lir->operands[1] = rARM_PC;
           lir->operands[2] = lir->operands[0];
           oatSetupResourceMasks(cUnit, lir);
           res = kRetryAll;
@@ -1304,9 +1304,9 @@
           bits |= value;
           break;
         case kFmtDfp: {
-          DCHECK(DOUBLEREG(operand));
+          DCHECK(ARM_DOUBLEREG(operand));
           DCHECK_EQ((operand & 0x1), 0U);
-          int regName = (operand & FP_REG_MASK) >> 1;
+          int regName = (operand & ARM_FP_REG_MASK) >> 1;
           /* Snag the 1-bit slice and position it */
           value = ((regName & 0x10) >> 4) << encoder->fieldLoc[i].end;
           /* Extract and position the 4-bit slice */
@@ -1315,7 +1315,7 @@
           break;
         }
         case kFmtSfp:
-          DCHECK(SINGLEREG(operand));
+          DCHECK(ARM_SINGLEREG(operand));
           /* Snag the 1-bit slice and position it */
           value = (operand & 0x1) << encoder->fieldLoc[i].end;
           /* Extract and position the 4-bit slice */
diff --git a/src/compiler/codegen/arm/FP/Thumb2VFP.cc b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
index 3ea28c9..1774a5b 100644
--- a/src/compiler/codegen/arm/FP/Thumb2VFP.cc
+++ b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
@@ -98,9 +98,9 @@
   rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
   DCHECK(rlDest.wide);
   DCHECK(rlResult.wide);
-  newLIR3(cUnit, (ArmOpcode)op, S2D(rlResult.lowReg, rlResult.highReg),
-          S2D(rlSrc1.lowReg, rlSrc1.highReg),
-          S2D(rlSrc2.lowReg, rlSrc2.highReg));
+  newLIR3(cUnit, (ArmOpcode)op, s2d(rlResult.lowReg, rlResult.highReg),
+          s2d(rlSrc1.lowReg, rlSrc1.highReg),
+          s2d(rlSrc2.lowReg, rlSrc2.highReg));
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -141,14 +141,14 @@
   }
   if (rlSrc.wide) {
     rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
-    srcReg = S2D(rlSrc.lowReg, rlSrc.highReg);
+    srcReg = s2d(rlSrc.lowReg, rlSrc.highReg);
   } else {
     rlSrc = loadValue(cUnit, rlSrc, kFPReg);
     srcReg = rlSrc.lowReg;
   }
   if (rlDest.wide) {
     rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
-    newLIR2(cUnit, (ArmOpcode)op, S2D(rlResult.lowReg, rlResult.highReg),
+    newLIR2(cUnit, (ArmOpcode)op, s2d(rlResult.lowReg, rlResult.highReg),
             srcReg);
     storeValueWide(cUnit, rlDest, rlResult);
   } else {
@@ -171,8 +171,8 @@
     rlSrc2 = oatGetSrcWide(cUnit, mir, 2);
     rlSrc1 = loadValueWide(cUnit, rlSrc1, kFPReg);
     rlSrc2 = loadValueWide(cUnit, rlSrc2, kFPReg);
-    newLIR2(cUnit, kThumb2Vcmpd, S2D(rlSrc1.lowReg, r1Src2.highReg),
-            S2D(rlSrc2.lowReg, rlSrc2.highReg));
+    newLIR2(cUnit, kThumb2Vcmpd, s2d(rlSrc1.lowReg, rlSrc2.highReg),
+            s2d(rlSrc2.lowReg, rlSrc2.highReg));
   } else {
     rlSrc1 = oatGetSrc(cUnit, mir, 0);
     rlSrc2 = oatGetSrc(cUnit, mir, 1);
@@ -246,8 +246,8 @@
     oatClobberSReg(cUnit, rlDest.sRegLow);
     rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
     loadConstant(cUnit, rlResult.lowReg, defaultResult);
-    newLIR2(cUnit, kThumb2Vcmpd, S2D(rlSrc1.lowReg, r1Src2.highReg),
-            S2D(rlSrc2.lowReg, rlSrc2.highReg));
+    newLIR2(cUnit, kThumb2Vcmpd, s2d(rlSrc1.lowReg, rlSrc2.highReg),
+            s2d(rlSrc2.lowReg, rlSrc2.highReg));
   } else {
     rlSrc1 = loadValue(cUnit, rlSrc1, kFPReg);
     rlSrc2 = loadValue(cUnit, rlSrc2, kFPReg);
@@ -256,7 +256,7 @@
     loadConstant(cUnit, rlResult.lowReg, defaultResult);
     newLIR2(cUnit, kThumb2Vcmps, rlSrc1.lowReg, rlSrc2.lowReg);
   }
-  DCHECK(!FPREG(rlResult.lowReg));
+  DCHECK(!ARM_FPREG(rlResult.lowReg));
   newLIR0(cUnit, kThumb2Fmstat);
 
   opIT(cUnit, (defaultResult == -1) ? kArmCondGt : kArmCondMi, "");
diff --git a/src/compiler/codegen/arm/Thumb2/Factory.cc b/src/compiler/codegen/arm/Thumb2/Factory.cc
index c373e35..fc3aaa0 100644
--- a/src/compiler/codegen/arm/Thumb2/Factory.cc
+++ b/src/compiler/codegen/arm/Thumb2/Factory.cc
@@ -18,9 +18,9 @@
 
 /* This file contains codegen for the Thumb ISA. */
 
-static int coreRegs[] = {r0, r1, r2, r3, rSUSPEND, r5, r6, r7, r8, rSELF, r10,
-                         r11, r12, rSP, rLR, rPC};
-static int reservedRegs[] = {rSUSPEND, rSELF, rSP, rLR, rPC};
+static int coreRegs[] = {r0, r1, r2, r3, rARM_SUSPEND, r5, r6, r7, r8, rARM_SELF, r10,
+                         r11, r12, rARM_SP, rARM_LR, rARM_PC};
+static int reservedRegs[] = {rARM_SUSPEND, rARM_SELF, rARM_SP, rARM_LR, rARM_PC};
 static int fpRegs[] = {fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
                        fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
                        fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
@@ -54,7 +54,7 @@
 LIR* loadFPConstantValue(CompilationUnit* cUnit, int rDest, int value)
 {
   int encodedImm = encodeImmSingle(value);
-  DCHECK(SINGLEREG(rDest));
+  DCHECK(ARM_SINGLEREG(rDest));
   if (encodedImm >= 0) {
     return newLIR2(cUnit, kThumb2Vmovs_IMM8, rDest, encodedImm);
   }
@@ -136,12 +136,12 @@
   LIR* res;
   int modImm;
 
-  if (FPREG(rDest)) {
+  if (ARM_FPREG(rDest)) {
     return loadFPConstantValue(cUnit, rDest, value);
   }
 
   /* See if the value can be constructed cheaply */
-  if (LOWREG(rDest) && (value >= 0) && (value <= 255)) {
+  if (ARM_LOWREG(rDest) && (value >= 0) && (value <= 255)) {
     return newLIR2(cUnit, kThumbMovImm, rDest, value);
   }
   /* Check Modified immediate special cases */
@@ -212,7 +212,7 @@
 LIR* opRegRegShift(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
                    int rSrc2, int shift)
 {
-  bool thumbForm = ((shift == 0) && LOWREG(rDestSrc1) && LOWREG(rSrc2));
+  bool thumbForm = ((shift == 0) && ARM_LOWREG(rDestSrc1) && ARM_LOWREG(rSrc2));
   ArmOpcode opcode = kThumbBkpt;
   switch (op) {
     case kOpAdc:
@@ -231,9 +231,9 @@
     case kOpCmp:
       if (thumbForm)
         opcode = kThumbCmpRR;
-      else if ((shift == 0) && !LOWREG(rDestSrc1) && !LOWREG(rSrc2))
+      else if ((shift == 0) && !ARM_LOWREG(rDestSrc1) && !ARM_LOWREG(rSrc2))
         opcode = kThumbCmpHH;
-      else if ((shift == 0) && LOWREG(rDestSrc1))
+      else if ((shift == 0) && ARM_LOWREG(rDestSrc1))
         opcode = kThumbCmpLH;
       else if (shift == 0)
         opcode = kThumbCmpHL;
@@ -245,11 +245,11 @@
       break;
     case kOpMov:
       DCHECK_EQ(shift, 0);
-      if (LOWREG(rDestSrc1) && LOWREG(rSrc2))
+      if (ARM_LOWREG(rDestSrc1) && ARM_LOWREG(rSrc2))
         opcode = kThumbMovRR;
-      else if (!LOWREG(rDestSrc1) && !LOWREG(rSrc2))
+      else if (!ARM_LOWREG(rDestSrc1) && !ARM_LOWREG(rSrc2))
         opcode = kThumbMovRR_H2H;
-      else if (LOWREG(rDestSrc1))
+      else if (ARM_LOWREG(rDestSrc1))
         opcode = kThumbMovRR_H2L;
       else
         opcode = kThumbMovRR_L2H;
@@ -334,8 +334,8 @@
             int rSrc2, int shift)
 {
   ArmOpcode opcode = kThumbBkpt;
-  bool thumbForm = (shift == 0) && LOWREG(rDest) && LOWREG(rSrc1) &&
-      LOWREG(rSrc2);
+  bool thumbForm = (shift == 0) && ARM_LOWREG(rDest) && ARM_LOWREG(rSrc1) &&
+      ARM_LOWREG(rSrc2);
   switch (op) {
     case kOpAdd:
       opcode = (thumbForm) ? kThumbAddRRR : kThumb2AddRRR;
@@ -411,7 +411,7 @@
   int absValue = (neg) ? -value : value;
   ArmOpcode opcode = kThumbBkpt;
   ArmOpcode altOpcode = kThumbBkpt;
-  bool allLowRegs = (LOWREG(rDest) && LOWREG(rSrc1));
+  bool allLowRegs = (ARM_LOWREG(rDest) && ARM_LOWREG(rSrc1));
   int modImm = modifiedImmediate(value);
   int modImmNeg = modifiedImmediate(-value);
 
@@ -434,10 +434,10 @@
     case kOpRor:
       return newLIR3(cUnit, kThumb2RorRRI5, rDest, rSrc1, value);
     case kOpAdd:
-      if (LOWREG(rDest) && (rSrc1 == r13sp) &&
+      if (ARM_LOWREG(rDest) && (rSrc1 == r13sp) &&
         (value <= 1020) && ((value & 0x3)==0)) {
         return newLIR3(cUnit, kThumbAddSpRel, rDest, rSrc1, value >> 2);
-      } else if (LOWREG(rDest) && (rSrc1 == r15pc) &&
+      } else if (ARM_LOWREG(rDest) && (rSrc1 == r15pc) &&
           (value <= 1020) && ((value & 0x3)==0)) {
         return newLIR3(cUnit, kThumbAddPcRel, rDest, rSrc1, value >> 2);
       }
@@ -529,7 +529,7 @@
 {
   bool neg = (value < 0);
   int absValue = (neg) ? -value : value;
-  bool shortForm = (((absValue & 0xff) == absValue) && LOWREG(rDestSrc1));
+  bool shortForm = (((absValue & 0xff) == absValue) && ARM_LOWREG(rDestSrc1));
   ArmOpcode opcode = kThumbBkpt;
   switch (op) {
     case kOpAdd:
@@ -549,9 +549,9 @@
       }
       break;
     case kOpCmp:
-      if (LOWREG(rDestSrc1) && shortForm)
+      if (ARM_LOWREG(rDestSrc1) && shortForm)
         opcode = (shortForm) ?  kThumbCmpRI8 : kThumbCmpRR;
-      else if (LOWREG(rDestSrc1))
+      else if (ARM_LOWREG(rDestSrc1))
         opcode = kThumbCmpRR;
       else {
         shortForm = false;
@@ -609,9 +609,9 @@
 {
   int encodedImm = encodeImmDouble(valLo, valHi);
   LIR* res;
-  if (FPREG(rDestLo)) {
+  if (ARM_FPREG(rDestLo)) {
     if (encodedImm >= 0) {
-      res = newLIR2(cUnit, kThumb2Vmovd_IMM8, S2D(rDestLo, rDestHi),
+      res = newLIR2(cUnit, kThumb2Vmovd_IMM8, s2d(rDestLo, rDestHi),
               encodedImm);
     } else {
       LIR* dataTarget = scanLiteralPoolWide(cUnit->literalList, valLo, valHi);
@@ -620,7 +620,7 @@
       }
       LIR* loadPcRel =
           rawLIR(cUnit, cUnit->currentDalvikOffset, kThumb2Vldrd,
-                 S2D(rDestLo, rDestHi), r15pc, 0, 0, 0, dataTarget);
+                 s2d(rDestLo, rDestHi), r15pc, 0, 0, 0, dataTarget);
       setMemRefType(loadPcRel, true, kLiteral);
       loadPcRel->aliasInfo = (intptr_t)dataTarget;
       oatAppendLIR(cUnit, (LIR* ) loadPcRel);
@@ -640,19 +640,19 @@
 LIR* loadBaseIndexed(CompilationUnit* cUnit, int rBase, int rIndex, int rDest,
                      int scale, OpSize size)
 {
-  bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rDest);
+  bool allLowRegs = ARM_LOWREG(rBase) && ARM_LOWREG(rIndex) && ARM_LOWREG(rDest);
   LIR* load;
   ArmOpcode opcode = kThumbBkpt;
   bool thumbForm = (allLowRegs && (scale == 0));
   int regPtr;
 
-  if (FPREG(rDest)) {
-    if (SINGLEREG(rDest)) {
+  if (ARM_FPREG(rDest)) {
+    if (ARM_SINGLEREG(rDest)) {
       DCHECK((size == kWord) || (size == kSingle));
       opcode = kThumb2Vldrs;
       size = kSingle;
     } else {
-      DCHECK(DOUBLEREG(rDest));
+      DCHECK(ARM_DOUBLEREG(rDest));
       DCHECK((size == kLong) || (size == kDouble));
       DCHECK_EQ((rDest & 0x1), 0);
       opcode = kThumb2Vldrd;
@@ -705,19 +705,19 @@
 LIR* storeBaseIndexed(CompilationUnit* cUnit, int rBase, int rIndex, int rSrc,
                       int scale, OpSize size)
 {
-  bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rSrc);
+  bool allLowRegs = ARM_LOWREG(rBase) && ARM_LOWREG(rIndex) && ARM_LOWREG(rSrc);
   LIR* store;
   ArmOpcode opcode = kThumbBkpt;
   bool thumbForm = (allLowRegs && (scale == 0));
   int regPtr;
 
-  if (FPREG(rSrc)) {
-    if (SINGLEREG(rSrc)) {
+  if (ARM_FPREG(rSrc)) {
+    if (ARM_SINGLEREG(rSrc)) {
       DCHECK((size == kWord) || (size == kSingle));
       opcode = kThumb2Vstrs;
       size = kSingle;
     } else {
-      DCHECK(DOUBLEREG(rSrc));
+      DCHECK(ARM_DOUBLEREG(rSrc));
       DCHECK((size == kLong) || (size == kDouble));
       DCHECK_EQ((rSrc & 0x1), 0);
       opcode = kThumb2Vstrd;
@@ -777,17 +777,17 @@
   ArmOpcode opcode = kThumbBkpt;
   bool shortForm = false;
   bool thumb2Form = (displacement < 4092 && displacement >= 0);
-  bool allLowRegs = (LOWREG(rBase) && LOWREG(rDest));
+  bool allLowRegs = (ARM_LOWREG(rBase) && ARM_LOWREG(rDest));
   int encodedDisp = displacement;
   bool is64bit = false;
   switch (size) {
     case kDouble:
     case kLong:
       is64bit = true;
-      if (FPREG(rDest)) {
-        if (SINGLEREG(rDest)) {
-          DCHECK(FPREG(rDestHi));
-          rDest = S2D(rDest, rDestHi);
+      if (ARM_FPREG(rDest)) {
+        if (ARM_SINGLEREG(rDest)) {
+          DCHECK(ARM_FPREG(rDestHi));
+          rDest = s2d(rDest, rDestHi);
         }
         opcode = kThumb2Vldrd;
         if (displacement <= 1020) {
@@ -804,7 +804,7 @@
       }
     case kSingle:
     case kWord:
-      if (FPREG(rDest)) {
+      if (ARM_FPREG(rDest)) {
         opcode = kThumb2Vldrs;
         if (displacement <= 1020) {
           shortForm = true;
@@ -812,12 +812,12 @@
         }
         break;
       }
-      if (LOWREG(rDest) && (rBase == r15pc) &&
+      if (ARM_LOWREG(rDest) && (rBase == r15pc) &&
           (displacement <= 1020) && (displacement >= 0)) {
         shortForm = true;
         encodedDisp >>= 2;
         opcode = kThumbLdrPcRel;
-      } else if (LOWREG(rDest) && (rBase == r13sp) &&
+      } else if (ARM_LOWREG(rDest) && (rBase == r13sp) &&
           (displacement <= 1020) && (displacement >= 0)) {
         shortForm = true;
         encodedDisp >>= 2;
@@ -878,7 +878,7 @@
   }
 
   // TODO: in future may need to differentiate Dalvik accesses w/ spills
-  if (rBase == rSP) {
+  if (rBase == rARM_SP) {
     annotateDalvikRegAccess(load, displacement >> 2, true /* isLoad */, is64bit);
   }
   return load;
@@ -906,21 +906,21 @@
   ArmOpcode opcode = kThumbBkpt;
   bool shortForm = false;
   bool thumb2Form = (displacement < 4092 && displacement >= 0);
-  bool allLowRegs = (LOWREG(rBase) && LOWREG(rSrc));
+  bool allLowRegs = (ARM_LOWREG(rBase) && ARM_LOWREG(rSrc));
   int encodedDisp = displacement;
   bool is64bit = false;
   switch (size) {
     case kLong:
     case kDouble:
       is64bit = true;
-      if (!FPREG(rSrc)) {
+      if (!ARM_FPREG(rSrc)) {
         res = storeBaseDispBody(cUnit, rBase, displacement, rSrc, -1, kWord);
         storeBaseDispBody(cUnit, rBase, displacement + 4, rSrcHi, -1, kWord);
         return res;
       }
-      if (SINGLEREG(rSrc)) {
-        DCHECK(FPREG(rSrcHi));
-        rSrc = S2D(rSrc, rSrcHi);
+      if (ARM_SINGLEREG(rSrc)) {
+        DCHECK(ARM_FPREG(rSrcHi));
+        rSrc = s2d(rSrc, rSrcHi);
       }
       opcode = kThumb2Vstrd;
       if (displacement <= 1020) {
@@ -930,8 +930,8 @@
       break;
     case kSingle:
     case kWord:
-      if (FPREG(rSrc)) {
-        DCHECK(SINGLEREG(rSrc));
+      if (ARM_FPREG(rSrc)) {
+        DCHECK(ARM_SINGLEREG(rSrc));
         opcode = kThumb2Vstrs;
         if (displacement <= 1020) {
           shortForm = true;
@@ -984,7 +984,7 @@
   }
 
   // TODO: In future, may need to differentiate Dalvik & spill accesses
-  if (rBase == rSP) {
+  if (rBase == rARM_SP) {
     annotateDalvikRegAccess(store, displacement >> 2, false /* isLoad */,
                             is64bit);
   }
@@ -1011,14 +1011,14 @@
 LIR* fpRegCopy(CompilationUnit* cUnit, int rDest, int rSrc)
 {
   int opcode;
-  DCHECK_EQ(DOUBLEREG(rDest), DOUBLEREG(rSrc));
-  if (DOUBLEREG(rDest)) {
+  DCHECK_EQ(ARM_DOUBLEREG(rDest), ARM_DOUBLEREG(rSrc));
+  if (ARM_DOUBLEREG(rDest)) {
     opcode = kThumb2Vmovd;
   } else {
-    if (SINGLEREG(rDest)) {
-      opcode = SINGLEREG(rSrc) ? kThumb2Vmovs : kThumb2Fmsr;
+    if (ARM_SINGLEREG(rDest)) {
+      opcode = ARM_SINGLEREG(rSrc) ? kThumb2Vmovs : kThumb2Fmsr;
     } else {
-      DCHECK(SINGLEREG(rSrc));
+      DCHECK(ARM_SINGLEREG(rSrc));
       opcode = kThumb2Fmrs;
     }
   }
diff --git a/src/compiler/codegen/arm/Thumb2/Gen.cc b/src/compiler/codegen/arm/Thumb2/Gen.cc
index cbe6b14..0a8e579 100644
--- a/src/compiler/codegen/arm/Thumb2/Gen.cc
+++ b/src/compiler/codegen/arm/Thumb2/Gen.cc
@@ -42,7 +42,7 @@
       // Bad case - half in register, half in frame.  Just punt
       loc.location = kLocInvalid;
     } else if (argNum < 2) {
-      loc.lowReg = rARG1 + argNum;
+      loc.lowReg = rARM_ARG1 + argNum;
       loc.highReg = loc.lowReg + 1;
       loc.location = kLocPhysReg;
     } else {
@@ -50,7 +50,7 @@
     }
   } else {
     if (argNum < 3) {
-      loc.lowReg = rARG1 + argNum;
+      loc.lowReg = rARM_ARG1 + argNum;
       loc.location = kLocPhysReg;
     } else {
       loc.location = kLocDalvikFrame;
@@ -69,10 +69,10 @@
   if (loc.location == kLocDalvikFrame) {
     int start = (inPosition(cUnit, loc.sRegLow) + 1) * sizeof(uint32_t);
     loc.lowReg = oatAllocTemp(cUnit);
-    loadWordDisp(cUnit, rSP, start, loc.lowReg);
+    loadWordDisp(cUnit, rARM_SP, start, loc.lowReg);
     if (loc.wide) {
       loc.highReg = oatAllocTemp(cUnit);
-      loadWordDisp(cUnit, rSP, start + sizeof(uint32_t), loc.highReg);
+      loadWordDisp(cUnit, rARM_SP, start + sizeof(uint32_t), loc.highReg);
     }
     loc.location = kLocPhysReg;
   }
@@ -88,7 +88,7 @@
     int vReg = SRegToVReg(cUnit, mir->ssaRep->uses[i]);
     int inPosition = vReg - firstIn;
     if (inPosition < numArgRegs) {
-      oatLockTemp(cUnit, rARG1 + inPosition);
+      oatLockTemp(cUnit, rARM_ARG1 + inPosition);
     }
   }
 }
@@ -239,7 +239,7 @@
        break;
      case kConstFunction:
        genPrintLabel(cUnit, mir);
-       loadConstant(cUnit, rRET0, mir->dalvikInsn.vB);
+       loadConstant(cUnit, rARM_RET0, mir->dalvikInsn.vB);
        nextMir = getNextMir(cUnit, &bb, mir);
        break;
      case kIGet:
@@ -291,7 +291,7 @@
     if (specialCase != kIdentity) {
       genPrintLabel(cUnit, nextMir);
     }
-    newLIR1(cUnit, kThumbBx, rLR);
+    newLIR1(cUnit, kThumbBx, rARM_LR);
     cUnit->coreSpillMask = 0;
     cUnit->numCoreSpills = 0;
     cUnit->fpSpillMask = 0;
@@ -356,14 +356,14 @@
  * The test loop will look something like:
  *
  *   adr   rBase, <table>
- *   ldr   rVal, [rSP, vRegOff]
+ *   ldr   rVal, [rARM_SP, vRegOff]
  *   mov   rIdx, #tableSize
  * lp:
  *   ldmia rBase!, {rKey, rDisp}
  *   sub   rIdx, #1
  *   cmp   rVal, rKey
  *   ifeq
- *   add   rPC, rDisp   ; This is the branch from which we compute displacement
+ *   add   rARM_PC, rDisp   ; This is the branch from which we compute displacement
  *   cbnz  rIdx, lp
  */
 void genSparseSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
@@ -488,12 +488,12 @@
   // Making a call - use explicit registers
   oatFlushAllRegs(cUnit);   /* Everything to home location */
   loadValueDirectFixed(cUnit, rlSrc, r0);
-  loadWordDisp(cUnit, rSELF, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode),
-               rLR);
+  loadWordDisp(cUnit, rARM_SELF, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode),
+               rARM_LR);
   // Materialize a pointer to the fill data image
   newLIR3(cUnit, kThumb2Adr, r1, 0, (intptr_t)tabRec);
   oatClobberCalleeSave(cUnit);
-  LIR* callInst = opReg(cUnit, kOpBlx, rLR);
+  LIR* callInst = opReg(cUnit, kOpBlx, rARM_LR);
   markSafepointPC(cUnit, callInst);
 }
 
@@ -511,8 +511,8 @@
   RegLocation rlResult;
   rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
   rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
-  newLIR2(cUnit, kThumb2Vnegd, S2D(rlResult.lowReg, rlResult.highReg),
-          S2D(rlSrc.lowReg, rlSrc.highReg));
+  newLIR2(cUnit, kThumb2Vnegd, s2d(rlResult.lowReg, rlResult.highReg),
+          s2d(rlSrc.lowReg, rlSrc.highReg));
   storeValueWide(cUnit, rlDest, rlResult);
 }
 
@@ -549,7 +549,7 @@
   loadValueDirectFixed(cUnit, rlSrc, r0);  // Get obj
   oatLockCallTemps(cUnit);  // Prepare for explicit register usage
   genNullCheck(cUnit, rlSrc.sRegLow, r0, optFlags);
-  loadWordDisp(cUnit, rSELF, Thread::ThinLockIdOffset().Int32Value(), r2);
+  loadWordDisp(cUnit, rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), r2);
   newLIR3(cUnit, kThumb2Ldrex, r1, r0,
           Object::MonitorOffset().Int32Value() >> 2); // Get object->lock
   // Align owner
@@ -564,9 +564,9 @@
   opRegImm(cUnit, kOpCmp, r1, 0);
   opIT(cUnit, kArmCondNe, "T");
   // Go expensive route - artLockObjectFromCode(self, obj);
-  loadWordDisp(cUnit, rSELF, ENTRYPOINT_OFFSET(pLockObjectFromCode), rLR);
+  loadWordDisp(cUnit, rARM_SELF, ENTRYPOINT_OFFSET(pLockObjectFromCode), rARM_LR);
   oatClobberCalleeSave(cUnit);
-  LIR* callInst = opReg(cUnit, kOpBlx, rLR);
+  LIR* callInst = opReg(cUnit, kOpBlx, rARM_LR);
   markSafepointPC(cUnit, callInst);
   oatGenMemBarrier(cUnit, kSY);
 }
@@ -585,7 +585,7 @@
   oatLockCallTemps(cUnit);  // Prepare for explicit register usage
   genNullCheck(cUnit, rlSrc.sRegLow, r0, optFlags);
   loadWordDisp(cUnit, r0, Object::MonitorOffset().Int32Value(), r1); // Get lock
-  loadWordDisp(cUnit, rSELF, Thread::ThinLockIdOffset().Int32Value(), r2);
+  loadWordDisp(cUnit, rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), r2);
   // Is lock unheld on lock or held by us (==threadId) on unlock?
   opRegRegImm(cUnit, kOpAnd, r3, r1,
               (LW_HASH_STATE_MASK << LW_HASH_STATE_SHIFT));
@@ -596,9 +596,9 @@
   opIT(cUnit, kArmCondEq, "EE");
   storeWordDisp(cUnit, r0, Object::MonitorOffset().Int32Value(), r3);
   // Go expensive route - UnlockObjectFromCode(obj);
-  loadWordDisp(cUnit, rSELF, ENTRYPOINT_OFFSET(pUnlockObjectFromCode), rLR);
+  loadWordDisp(cUnit, rARM_SELF, ENTRYPOINT_OFFSET(pUnlockObjectFromCode), rARM_LR);
   oatClobberCalleeSave(cUnit);
-  LIR* callInst = opReg(cUnit, kOpBlx, rLR);
+  LIR* callInst = opReg(cUnit, kOpBlx, rARM_LR);
   markSafepointPC(cUnit, callInst);
   oatGenMemBarrier(cUnit, kSY);
 }
@@ -643,7 +643,7 @@
 
   target1 = newLIR0(cUnit, kPseudoTargetLabel);
 
-  RegLocation rlTemp = LOC_C_RETURN; // Just using as template, will change
+  RegLocation rlTemp = locCReturn(); // Just using as template, will change
   rlTemp.lowReg = tReg;
   storeValue(cUnit, rlDest, rlTemp);
   oatFreeTemp(cUnit, tReg);
@@ -708,13 +708,13 @@
   LIR* branch;
   int modImm;
   ArmConditionCode armCond = oatArmConditionEncoding(cond);
-  if ((LOWREG(reg)) && (checkValue == 0) &&
+  if ((ARM_LOWREG(reg)) && (checkValue == 0) &&
      ((armCond == kArmCondEq) || (armCond == kArmCondNe))) {
     branch = newLIR2(cUnit, (armCond == kArmCondEq) ? kThumb2Cbz : kThumb2Cbnz,
                      reg, 0);
   } else {
     modImm = modifiedImmediate(checkValue);
-    if (LOWREG(reg) && ((checkValue & 0xff) == checkValue)) {
+    if (ARM_LOWREG(reg) && ((checkValue & 0xff) == checkValue)) {
       newLIR2(cUnit, kThumbCmpRI8, reg, checkValue);
     } else if (modImm >= 0) {
       newLIR2(cUnit, kThumb2CmpRI8, reg, modImm);
@@ -732,13 +732,13 @@
 {
   LIR* res;
   int opcode;
-  if (FPREG(rDest) || FPREG(rSrc))
+  if (ARM_FPREG(rDest) || ARM_FPREG(rSrc))
     return fpRegCopy(cUnit, rDest, rSrc);
-  if (LOWREG(rDest) && LOWREG(rSrc))
+  if (ARM_LOWREG(rDest) && ARM_LOWREG(rSrc))
     opcode = kThumbMovRR;
-  else if (!LOWREG(rDest) && !LOWREG(rSrc))
+  else if (!ARM_LOWREG(rDest) && !ARM_LOWREG(rSrc))
      opcode = kThumbMovRR_H2H;
-  else if (LOWREG(rDest))
+  else if (ARM_LOWREG(rDest))
      opcode = kThumbMovRR_H2L;
   else
      opcode = kThumbMovRR_L2H;
@@ -759,19 +759,19 @@
 void opRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
                int srcLo, int srcHi)
 {
-  bool destFP = FPREG(destLo) && FPREG(destHi);
-  bool srcFP = FPREG(srcLo) && FPREG(srcHi);
-  DCHECK_EQ(FPREG(srcLo), FPREG(srcHi));
-  DCHECK_EQ(FPREG(destLo), FPREG(destHi));
+  bool destFP = ARM_FPREG(destLo) && ARM_FPREG(destHi);
+  bool srcFP = ARM_FPREG(srcLo) && ARM_FPREG(srcHi);
+  DCHECK_EQ(ARM_FPREG(srcLo), ARM_FPREG(srcHi));
+  DCHECK_EQ(ARM_FPREG(destLo), ARM_FPREG(destHi));
   if (destFP) {
     if (srcFP) {
-      opRegCopy(cUnit, S2D(destLo, destHi), S2D(srcLo, srcHi));
+      opRegCopy(cUnit, s2d(destLo, destHi), s2d(srcLo, srcHi));
     } else {
-      newLIR3(cUnit, kThumb2Fmdrr, S2D(destLo, destHi), srcLo, srcHi);
+      newLIR3(cUnit, kThumb2Fmdrr, s2d(destLo, destHi), srcLo, srcHi);
     }
   } else {
     if (srcFP) {
-      newLIR3(cUnit, kThumb2Fmrrd, destLo, destHi, S2D(srcLo, srcHi));
+      newLIR3(cUnit, kThumb2Fmrrd, destLo, destHi, s2d(srcLo, srcHi));
     } else {
       // Handle overlap
       if (srcHi == destLo) {
@@ -872,7 +872,7 @@
   int regCardBase = oatAllocTemp(cUnit);
   int regCardNo = oatAllocTemp(cUnit);
   LIR* branchOver = opCmpImmBranch(cUnit, kCondEq, valReg, 0, NULL);
-  loadWordDisp(cUnit, rSELF, Thread::CardTableOffset().Int32Value(), regCardBase);
+  loadWordDisp(cUnit, rARM_SELF, Thread::CardTableOffset().Int32Value(), regCardBase);
   opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, CardTable::kCardShift);
   storeBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
                    kUnsignedByte);
@@ -994,18 +994,18 @@
   RegLocation rlDest = inlineTargetWide(cUnit, info);  // double place for result
   rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
   RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
-  newLIR2(cUnit, kThumb2Vsqrtd, S2D(rlResult.lowReg, rlResult.highReg),
-          S2D(rlSrc.lowReg, rlSrc.highReg));
-  newLIR2(cUnit, kThumb2Vcmpd, S2D(rlResult.lowReg, rlResult.highReg),
-          S2D(rlResult.lowReg, rlResult.highReg));
+  newLIR2(cUnit, kThumb2Vsqrtd, s2d(rlResult.lowReg, rlResult.highReg),
+          s2d(rlSrc.lowReg, rlSrc.highReg));
+  newLIR2(cUnit, kThumb2Vcmpd, s2d(rlResult.lowReg, rlResult.highReg),
+          s2d(rlResult.lowReg, rlResult.highReg));
   newLIR0(cUnit, kThumb2Fmstat);
   branch = newLIR2(cUnit, kThumbBCond, 0, kArmCondEq);
   oatClobberCalleeSave(cUnit);
   oatLockCallTemps(cUnit);  // Using fixed registers
   int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pSqrt));
-  newLIR3(cUnit, kThumb2Fmrrd, r0, r1, S2D(rlSrc.lowReg, rlSrc.highReg));
+  newLIR3(cUnit, kThumb2Fmrrd, r0, r1, s2d(rlSrc.lowReg, rlSrc.highReg));
   newLIR1(cUnit, kThumbBlxR, rTgt);
-  newLIR3(cUnit, kThumb2Fmdrr, S2D(rlResult.lowReg, rlResult.highReg), r0, r1);
+  newLIR3(cUnit, kThumb2Fmdrr, s2d(rlResult.lowReg, rlResult.highReg), r0, r1);
   branch->target = newLIR0(cUnit, kPseudoTargetLabel);
   storeValueWide(cUnit, rlDest, rlResult);
   return true;
@@ -1048,7 +1048,7 @@
 // Test suspend flag, return target of taken suspend branch
 LIR* opTestSuspend(CompilationUnit* cUnit, LIR* target)
 {
-  newLIR2(cUnit, kThumbSubRI8, rSUSPEND, 1);
+  newLIR2(cUnit, kThumbSubRI8, rARM_SUSPEND, 1);
   return opCondBranch(cUnit, (target == NULL) ? kCondEq : kCondNe, target);
 }
 
diff --git a/src/compiler/codegen/arm/Thumb2/Ralloc.cc b/src/compiler/codegen/arm/Thumb2/Ralloc.cc
index 894488a..ab5cf33 100644
--- a/src/compiler/codegen/arm/Thumb2/Ralloc.cc
+++ b/src/compiler/codegen/arm/Thumb2/Ralloc.cc
@@ -68,7 +68,7 @@
   oatInitPool(pool->FPRegs, fpRegs, pool->numFPRegs);
   // Keep special registers from being allocated
   for (int i = 0; i < numReserved; i++) {
-    if (NO_SUSPEND && (reservedRegs[i] == rSUSPEND)) {
+    if (NO_SUSPEND && (reservedRegs[i] == rARM_SUSPEND)) {
       //To measure cost of suspend check
       continue;
     }
diff --git a/src/compiler/codegen/mips/ArchFactory.cc b/src/compiler/codegen/mips/ArchFactory.cc
index e5dc98f..90c0ede 100644
--- a/src/compiler/codegen/mips/ArchFactory.cc
+++ b/src/compiler/codegen/mips/ArchFactory.cc
@@ -99,7 +99,7 @@
  */
 int loadHelper(CompilationUnit* cUnit, int offset)
 {
-  loadWordDisp(cUnit, rSELF, offset, r_T9);
+  loadWordDisp(cUnit, rMIPS_SELF, offset, r_T9);
   return r_T9;
 }
 
@@ -110,11 +110,11 @@
   }
   uint32_t mask = cUnit->coreSpillMask;
   int offset = cUnit->numCoreSpills * 4;
-  opRegImm(cUnit, kOpSub, rSP, offset);
+  opRegImm(cUnit, kOpSub, rMIPS_SP, offset);
   for (int reg = 0; mask; mask >>= 1, reg++) {
     if (mask & 0x1) {
       offset -= 4;
-      storeWordDisp(cUnit, rSP, offset, reg);
+      storeWordDisp(cUnit, rMIPS_SP, offset, reg);
     }
   }
 }
@@ -129,10 +129,10 @@
   for (int reg = 0; mask; mask >>= 1, reg++) {
     if (mask & 0x1) {
       offset -= 4;
-      loadWordDisp(cUnit, rSP, offset, reg);
+      loadWordDisp(cUnit, rMIPS_SP, offset, reg);
     }
   }
-  opRegImm(cUnit, kOpAdd, rSP, cUnit->frameSize);
+  opRegImm(cUnit, kOpAdd, rMIPS_SP, cUnit->frameSize);
 }
 
 void genEntrySequence(CompilationUnit* cUnit, RegLocation* argLocs,
@@ -140,15 +140,15 @@
 {
   int spillCount = cUnit->numCoreSpills + cUnit->numFPSpills;
   /*
-   * On entry, rARG0, rARG1, rARG2 & rARG3 are live.  Let the register
+   * On entry, rMIPS_ARG0, rMIPS_ARG1, rMIPS_ARG2 & rMIPS_ARG3 are live.  Let the register
    * allocation mechanism know so it doesn't try to use any of them when
    * expanding the frame or flushing.  This leaves the utility
    * code with a single temp: r12.  This should be enough.
    */
-  oatLockTemp(cUnit, rARG0);
-  oatLockTemp(cUnit, rARG1);
-  oatLockTemp(cUnit, rARG2);
-  oatLockTemp(cUnit, rARG3);
+  oatLockTemp(cUnit, rMIPS_ARG0);
+  oatLockTemp(cUnit, rMIPS_ARG1);
+  oatLockTemp(cUnit, rMIPS_ARG2);
+  oatLockTemp(cUnit, rMIPS_ARG3);
 
   /*
    * We can safely skip the stack overflow check if we're
@@ -161,36 +161,36 @@
   int newSP = oatAllocTemp(cUnit);
   if (!skipOverflowCheck) {
     /* Load stack limit */
-    loadWordDisp(cUnit, rSELF, Thread::StackEndOffset().Int32Value(), checkReg);
+    loadWordDisp(cUnit, rMIPS_SELF, Thread::StackEndOffset().Int32Value(), checkReg);
   }
   /* Spill core callee saves */
   spillCoreRegs(cUnit);
   /* NOTE: promotion of FP regs currently unsupported, thus no FP spill */
   DCHECK_EQ(cUnit->numFPSpills, 0);
   if (!skipOverflowCheck) {
-    opRegRegImm(cUnit, kOpSub, newSP, rSP, cUnit->frameSize - (spillCount * 4));
+    opRegRegImm(cUnit, kOpSub, newSP, rMIPS_SP, cUnit->frameSize - (spillCount * 4));
     genRegRegCheck(cUnit, kCondCc, newSP, checkReg, kThrowStackOverflow);
-    opRegCopy(cUnit, rSP, newSP);     // Establish stack
+    opRegCopy(cUnit, rMIPS_SP, newSP);     // Establish stack
   } else {
-    opRegImm(cUnit, kOpSub, rSP, cUnit->frameSize - (spillCount * 4));
+    opRegImm(cUnit, kOpSub, rMIPS_SP, cUnit->frameSize - (spillCount * 4));
   }
 
   flushIns(cUnit, argLocs, rlMethod);
 
-  oatFreeTemp(cUnit, rARG0);
-  oatFreeTemp(cUnit, rARG1);
-  oatFreeTemp(cUnit, rARG2);
-  oatFreeTemp(cUnit, rARG3);
+  oatFreeTemp(cUnit, rMIPS_ARG0);
+  oatFreeTemp(cUnit, rMIPS_ARG1);
+  oatFreeTemp(cUnit, rMIPS_ARG2);
+  oatFreeTemp(cUnit, rMIPS_ARG3);
 }
 
 void genExitSequence(CompilationUnit* cUnit)
 {
   /*
-   * In the exit path, rRET0/rRET1 are live - make sure they aren't
+   * In the exit path, rMIPS_RET0/rMIPS_RET1 are live - make sure they aren't
    * allocated by the register utilities as temps.
    */
-  oatLockTemp(cUnit, rRET0);
-  oatLockTemp(cUnit, rRET1);
+  oatLockTemp(cUnit, rMIPS_RET0);
+  oatLockTemp(cUnit, rMIPS_RET1);
 
   newLIR0(cUnit, kPseudoMethodExit);
   unSpillCoreRegs(cUnit);
diff --git a/src/compiler/codegen/mips/ArchUtility.cc b/src/compiler/codegen/mips/ArchUtility.cc
index 9a2b923..3063e69 100644
--- a/src/compiler/codegen/mips/ArchUtility.cc
+++ b/src/compiler/codegen/mips/ArchUtility.cc
@@ -22,6 +22,91 @@
 
 namespace art {
 
+RegLocation locCReturn()
+{
+  RegLocation res = MIPS_LOC_C_RETURN;
+  return res;
+}
+
+RegLocation locCReturnWide()
+{
+  RegLocation res = MIPS_LOC_C_RETURN_WIDE;
+  return res;
+}
+
+RegLocation locCReturnFloat()
+{
+  RegLocation res = MIPS_LOC_C_RETURN_FLOAT;
+  return res;
+}
+
+RegLocation locCReturnDouble()
+{
+  RegLocation res = MIPS_LOC_C_RETURN_DOUBLE;
+  return res;
+}
+
+// Return a target-dependent special register.
+int targetReg(SpecialTargetRegister reg) {
+  int res = INVALID_REG;
+  switch (reg) {
+    case kSelf: res = rMIPS_SELF; break;
+    case kSuspend: res =  rMIPS_SUSPEND; break;
+    case kLr: res =  rMIPS_LR; break;
+    case kPc: res =  rMIPS_PC; break;
+    case kSp: res =  rMIPS_SP; break;
+    case kArg0: res = rMIPS_ARG0; break;
+    case kArg1: res = rMIPS_ARG1; break;
+    case kArg2: res = rMIPS_ARG2; break;
+    case kArg3: res = rMIPS_ARG3; break;
+    case kFArg0: res = rMIPS_FARG0; break;
+    case kFArg1: res = rMIPS_FARG1; break;
+    case kFArg2: res = rMIPS_FARG2; break;
+    case kFArg3: res = rMIPS_FARG3; break;
+    case kRet0: res = rMIPS_RET0; break;
+    case kRet1: res = rMIPS_RET1; break;
+    case kInvokeTgt: res = rMIPS_INVOKE_TGT; break;
+    case kCount: res = rMIPS_COUNT; break;
+  }
+  return res;
+}
+
+// Create a double from a pair of singles.
+int s2d(int lowReg, int highReg)
+{
+  return MIPS_S2D(lowReg, highReg);
+}
+
+// Is reg a single or double?
+bool fpReg(int reg)
+{
+  return MIPS_FPREG(reg);
+}
+
+// Is reg a single?
+bool singleReg(int reg)
+{
+  return MIPS_SINGLEREG(reg);
+}
+
+// Is reg a double?
+bool doubleReg(int reg)
+{
+  return MIPS_DOUBLEREG(reg);
+}
+
+// Return mask to strip off fp reg flags and bias.
+uint32_t fpRegMask()
+{
+  return MIPS_FP_REG_MASK;
+}
+
+// True if both regs single, both core or both double.
+bool sameRegType(int reg1, int reg2)
+{
+  return (MIPS_REGTYPE(reg1) == MIPS_REGTYPE(reg2));
+}
+
 /*
  * Decode the register id.
  */
@@ -34,9 +119,9 @@
 
   regId = reg & 0x1f;
   /* Each double register is equal to a pair of single-precision FP registers */
-  seed = DOUBLEREG(reg) ? 3 : 1;
+  seed = MIPS_DOUBLEREG(reg) ? 3 : 1;
   /* FP register starts at bit position 16 */
-  shift = FPREG(reg) ? kMipsFPReg0 : 0;
+  shift = MIPS_FPREG(reg) ? kMipsFPReg0 : 0;
   /* Expand the double register id into single offset */
   shift += regId;
   return (seed << shift);
@@ -109,11 +194,11 @@
              }
              break;
            case 's':
-             sprintf(tbuf,"$f%d",operand & FP_REG_MASK);
+             sprintf(tbuf,"$f%d",operand & MIPS_FP_REG_MASK);
              break;
            case 'S':
-             DCHECK_EQ(((operand & FP_REG_MASK) & 1), 0);
-             sprintf(tbuf,"$f%d",operand & FP_REG_MASK);
+             DCHECK_EQ(((operand & MIPS_FP_REG_MASK) & 1), 0);
+             sprintf(tbuf,"$f%d",operand & MIPS_FP_REG_MASK);
              break;
            case 'h':
              sprintf(tbuf,"%04x", operand);
diff --git a/src/compiler/codegen/mips/Assemble.cc b/src/compiler/codegen/mips/Assemble.cc
index 9f8a686..e9dd219 100644
--- a/src/compiler/codegen/mips/Assemble.cc
+++ b/src/compiler/codegen/mips/Assemble.cc
@@ -677,16 +677,16 @@
           bits |= (value << encoder->fieldLoc[i].end);
           break;
         case kFmtDfp: {
-          DCHECK(DOUBLEREG(operand));
+          DCHECK(MIPS_DOUBLEREG(operand));
           DCHECK_EQ((operand & 0x1), 0U);
-          value = ((operand & FP_REG_MASK) << encoder->fieldLoc[i].start) &
+          value = ((operand & MIPS_FP_REG_MASK) << encoder->fieldLoc[i].start) &
               ((1 << (encoder->fieldLoc[i].end + 1)) - 1);
           bits |= value;
           break;
         }
         case kFmtSfp:
-          DCHECK(SINGLEREG(operand));
-          value = ((operand & FP_REG_MASK) << encoder->fieldLoc[i].start) &
+          DCHECK(MIPS_SINGLEREG(operand));
+          value = ((operand & MIPS_FP_REG_MASK) << encoder->fieldLoc[i].start) &
               ((1 << (encoder->fieldLoc[i].end + 1)) - 1);
           bits |= value;
           break;
diff --git a/src/compiler/codegen/mips/FP/MipsFP.cc b/src/compiler/codegen/mips/FP/MipsFP.cc
index 990c71f..fb6c8df 100644
--- a/src/compiler/codegen/mips/FP/MipsFP.cc
+++ b/src/compiler/codegen/mips/FP/MipsFP.cc
@@ -107,9 +107,9 @@
   rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
   DCHECK(rlDest.wide);
   DCHECK(rlResult.wide);
-  newLIR3(cUnit, (MipsOpCode)op, S2D(rlResult.lowReg, rlResult.highReg),
-          S2D(rlSrc1.lowReg, rlSrc1.highReg),
-          S2D(rlSrc2.lowReg, rlSrc2.highReg));
+  newLIR3(cUnit, (MipsOpCode)op, s2d(rlResult.lowReg, rlResult.highReg),
+          s2d(rlSrc1.lowReg, rlSrc1.highReg),
+          s2d(rlSrc2.lowReg, rlSrc2.highReg));
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 #else
@@ -149,14 +149,14 @@
   }
   if (rlSrc.wide) {
     rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
-    srcReg = S2D(rlSrc.lowReg, rlSrc.highReg);
+    srcReg = s2d(rlSrc.lowReg, rlSrc.highReg);
   } else {
     rlSrc = loadValue(cUnit, rlSrc, kFPReg);
     srcReg = rlSrc.lowReg;
   }
   if (rlDest.wide) {
     rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
-    newLIR2(cUnit, (MipsOpCode)op, S2D(rlResult.lowReg, rlResult.highReg),
+    newLIR2(cUnit, (MipsOpCode)op, s2d(rlResult.lowReg, rlResult.highReg),
             srcReg);
     storeValueWide(cUnit, rlDest, rlResult);
   } else {
@@ -197,11 +197,11 @@
   oatFlushAllRegs(cUnit);
   oatLockCallTemps(cUnit);
   if (wide) {
-    loadValueDirectWideFixed(cUnit, rlSrc1, rFARG0, rFARG1);
-    loadValueDirectWideFixed(cUnit, rlSrc2, rFARG2, rFARG3);
+    loadValueDirectWideFixed(cUnit, rlSrc1, rMIPS_FARG0, rMIPS_FARG1);
+    loadValueDirectWideFixed(cUnit, rlSrc2, rMIPS_FARG2, rMIPS_FARG3);
   } else {
-    loadValueDirectFixed(cUnit, rlSrc1, rFARG0);
-    loadValueDirectFixed(cUnit, rlSrc2, rFARG2);
+    loadValueDirectFixed(cUnit, rlSrc1, rMIPS_FARG0);
+    loadValueDirectFixed(cUnit, rlSrc2, rMIPS_FARG2);
   }
   int rTgt = loadHelper(cUnit, offset);
   // NOTE: not a safepoint
diff --git a/src/compiler/codegen/mips/Mips32/Factory.cc b/src/compiler/codegen/mips/Mips32/Factory.cc
index 2f0d460..0a0d906 100644
--- a/src/compiler/codegen/mips/Mips32/Factory.cc
+++ b/src/compiler/codegen/mips/Mips32/Factory.cc
@@ -46,12 +46,12 @@
 {
   int opcode;
   /* must be both DOUBLE or both not DOUBLE */
-  DCHECK_EQ(DOUBLEREG(rDest),DOUBLEREG(rSrc));
-  if (DOUBLEREG(rDest)) {
+  DCHECK_EQ(MIPS_DOUBLEREG(rDest),MIPS_DOUBLEREG(rSrc));
+  if (MIPS_DOUBLEREG(rDest)) {
     opcode = kMipsFmovd;
   } else {
-    if (SINGLEREG(rDest)) {
-      if (SINGLEREG(rSrc)) {
+    if (MIPS_SINGLEREG(rDest)) {
+      if (MIPS_SINGLEREG(rSrc)) {
         opcode = kMipsFmovs;
       } else {
         /* note the operands are swapped for the mtc1 instr */
@@ -61,7 +61,7 @@
         opcode = kMipsMtc1;
       }
     } else {
-      DCHECK(SINGLEREG(rSrc));
+      DCHECK(MIPS_SINGLEREG(rSrc));
       opcode = kMipsMfc1;
     }
   }
@@ -88,9 +88,9 @@
 
 #ifdef __mips_hard_float
   int rDestSave = rDest;
-  int isFpReg = FPREG(rDest);
+  int isFpReg = MIPS_FPREG(rDest);
   if (isFpReg) {
-    DCHECK(SINGLEREG(rDest));
+    DCHECK(MIPS_SINGLEREG(rDest));
     rDest = oatAllocTemp(cUnit);
   }
 #endif
@@ -372,8 +372,8 @@
   int tReg = oatAllocTemp(cUnit);
 
 #ifdef __mips_hard_float
-  if (FPREG(rDest)) {
-    DCHECK(SINGLEREG(rDest));
+  if (MIPS_FPREG(rDest)) {
+    DCHECK(MIPS_SINGLEREG(rDest));
     DCHECK((size == kWord) || (size == kSingle));
     size = kSingle;
   } else {
@@ -429,8 +429,8 @@
   int tReg = oatAllocTemp(cUnit);
 
 #ifdef __mips_hard_float
-  if (FPREG(rSrc)) {
-    DCHECK(SINGLEREG(rSrc));
+  if (MIPS_FPREG(rSrc)) {
+    DCHECK(MIPS_SINGLEREG(rSrc));
     DCHECK((size == kWord) || (size == kSingle));
     size = kSingle;
   } else {
@@ -540,12 +540,12 @@
       pair = true;
       opcode = kMipsLw;
 #ifdef __mips_hard_float
-      if (FPREG(rDest)) {
+      if (MIPS_FPREG(rDest)) {
         opcode = kMipsFlwc1;
-        if (DOUBLEREG(rDest)) {
-          rDest = rDest - FP_DOUBLE;
+        if (MIPS_DOUBLEREG(rDest)) {
+          rDest = rDest - MIPS_FP_DOUBLE;
         } else {
-          DCHECK(FPREG(rDestHi));
+          DCHECK(MIPS_FPREG(rDestHi));
           DCHECK(rDest == (rDestHi - 1));
         }
         rDestHi = rDest + 1;
@@ -558,9 +558,9 @@
     case kSingle:
       opcode = kMipsLw;
 #ifdef __mips_hard_float
-      if (FPREG(rDest)) {
+      if (MIPS_FPREG(rDest)) {
         opcode = kMipsFlwc1;
-        DCHECK(SINGLEREG(rDest));
+        DCHECK(MIPS_SINGLEREG(rDest));
       }
 #endif
       DCHECK_EQ((displacement & 0x3), 0);
@@ -608,7 +608,7 @@
     }
   }
 
-  if (rBase == rSP) {
+  if (rBase == rMIPS_SP) {
     annotateDalvikRegAccess(load,
                             (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2,
                             true /* isLoad */, pair /* is64bit */);
@@ -650,12 +650,12 @@
       pair = true;
       opcode = kMipsSw;
 #ifdef __mips_hard_float
-      if (FPREG(rSrc)) {
+      if (MIPS_FPREG(rSrc)) {
         opcode = kMipsFswc1;
-        if (DOUBLEREG(rSrc)) {
-          rSrc = rSrc - FP_DOUBLE;
+        if (MIPS_DOUBLEREG(rSrc)) {
+          rSrc = rSrc - MIPS_FP_DOUBLE;
         } else {
-          DCHECK(FPREG(rSrcHi));
+          DCHECK(MIPS_FPREG(rSrcHi));
           DCHECK_EQ(rSrc, (rSrcHi - 1));
         }
         rSrcHi = rSrc + 1;
@@ -668,9 +668,9 @@
     case kSingle:
       opcode = kMipsSw;
 #ifdef __mips_hard_float
-      if (FPREG(rSrc)) {
+      if (MIPS_FPREG(rSrc)) {
         opcode = kMipsFswc1;
-        DCHECK(SINGLEREG(rSrc));
+        DCHECK(MIPS_SINGLEREG(rSrc));
       }
 #endif
       DCHECK_EQ((displacement & 0x3), 0);
@@ -709,7 +709,7 @@
     oatFreeTemp(cUnit, rScratch);
   }
 
-  if (rBase == rSP) {
+  if (rBase == rMIPS_SP) {
     annotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0))
                             >> 2, false /* isLoad */, pair /* is64bit */);
     if (pair) {
diff --git a/src/compiler/codegen/mips/Mips32/Gen.cc b/src/compiler/codegen/mips/Mips32/Gen.cc
index 22c8b84..a772c09 100644
--- a/src/compiler/codegen/mips/Mips32/Gen.cc
+++ b/src/compiler/codegen/mips/Mips32/Gen.cc
@@ -238,7 +238,7 @@
   // Making a call - use explicit registers
   oatFlushAllRegs(cUnit);   /* Everything to home location */
   oatLockCallTemps(cUnit);
-  loadValueDirectFixed(cUnit, rlSrc, rARG0);
+  loadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0);
 
   // Must prevent code motion for the curr pc pair
   genBarrier(cUnit);
@@ -251,7 +251,7 @@
   LIR* baseLabel = newLIR0(cUnit, kPseudoTargetLabel);
 
   // Materialize a pointer to the fill data image
-  newLIR4(cUnit, kMipsDelta, rARG1, 0, (intptr_t)baseLabel, (intptr_t)tabRec);
+  newLIR4(cUnit, kMipsDelta, rMIPS_ARG1, 0, (intptr_t)baseLabel, (intptr_t)tabRec);
 
   // And go...
   oatClobberCalleeSave(cUnit);
@@ -284,9 +284,9 @@
 void genMonitorEnter(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
 {
   oatFlushAllRegs(cUnit);
-  loadValueDirectFixed(cUnit, rlSrc, rARG0);  // Get obj
+  loadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0);  // Get obj
   oatLockCallTemps(cUnit);  // Prepare for explicit register usage
-  genNullCheck(cUnit, rlSrc.sRegLow, rARG0, optFlags);
+  genNullCheck(cUnit, rlSrc.sRegLow, rMIPS_ARG0, optFlags);
   // Go expensive route - artLockObjectFromCode(self, obj);
   int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pLockObjectFromCode));
   oatClobberCalleeSave(cUnit);
@@ -300,9 +300,9 @@
 void genMonitorExit(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
 {
   oatFlushAllRegs(cUnit);
-  loadValueDirectFixed(cUnit, rlSrc, rARG0);  // Get obj
+  loadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0);  // Get obj
   oatLockCallTemps(cUnit);  // Prepare for explicit register usage
-  genNullCheck(cUnit, rlSrc.sRegLow, rARG0, optFlags);
+  genNullCheck(cUnit, rlSrc.sRegLow, rMIPS_ARG0, optFlags);
   // Go expensive route - UnlockObjectFromCode(obj);
   int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pUnlockObjectFromCode));
   oatClobberCalleeSave(cUnit);
@@ -453,7 +453,7 @@
 LIR* opRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
 {
 #ifdef __mips_hard_float
-  if (FPREG(rDest) || FPREG(rSrc))
+  if (MIPS_FPREG(rDest) || MIPS_FPREG(rSrc))
     return fpRegCopy(cUnit, rDest, rSrc);
 #endif
   LIR* res = rawLIR(cUnit, cUnit->currentDalvikOffset, kMipsMove,
@@ -475,13 +475,13 @@
           int srcLo, int srcHi)
 {
 #ifdef __mips_hard_float
-  bool destFP = FPREG(destLo) && FPREG(destHi);
-  bool srcFP = FPREG(srcLo) && FPREG(srcHi);
-  assert(FPREG(srcLo) == FPREG(srcHi));
-  assert(FPREG(destLo) == FPREG(destHi));
+  bool destFP = MIPS_FPREG(destLo) && MIPS_FPREG(destHi);
+  bool srcFP = MIPS_FPREG(srcLo) && MIPS_FPREG(srcHi);
+  assert(MIPS_FPREG(srcLo) == MIPS_FPREG(srcHi));
+  assert(MIPS_FPREG(destLo) == MIPS_FPREG(destHi));
   if (destFP) {
     if (srcFP) {
-      opRegCopy(cUnit, S2D(destLo, destHi), S2D(srcLo, srcHi));
+      opRegCopy(cUnit, s2d(destLo, destHi), s2d(srcLo, srcHi));
     } else {
        /* note the operands are swapped for the mtc1 instr */
       newLIR2(cUnit, kMipsMtc1, srcLo, destLo);
@@ -561,7 +561,7 @@
   int regCardBase = oatAllocTemp(cUnit);
   int regCardNo = oatAllocTemp(cUnit);
   LIR* branchOver = opCmpImmBranch(cUnit, kCondEq, valReg, 0, NULL);
-  loadWordDisp(cUnit, rSELF, Thread::CardTableOffset().Int32Value(), regCardBase);
+  loadWordDisp(cUnit, rMIPS_SELF, Thread::CardTableOffset().Int32Value(), regCardBase);
   opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, CardTable::kCardShift);
   storeBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
                    kUnsignedByte);
@@ -638,8 +638,8 @@
 // Test suspend flag, return target of taken suspend branch
 LIR* opTestSuspend(CompilationUnit* cUnit, LIR* target)
 {
-  opRegImm(cUnit, kOpSub, rSUSPEND, 1);
-  return opCmpImmBranch(cUnit, (target == NULL) ? kCondEq : kCondNe, rSUSPEND, 0, target);
+  opRegImm(cUnit, kOpSub, rMIPS_SUSPEND, 1);
+  return opCmpImmBranch(cUnit, (target == NULL) ? kCondEq : kCondNe, rMIPS_SUSPEND, 0, target);
 }
 
 // Decrement register and branch on condition
diff --git a/src/compiler/codegen/mips/Mips32/Ralloc.cc b/src/compiler/codegen/mips/Mips32/Ralloc.cc
index e7ad60c..b913bfb 100644
--- a/src/compiler/codegen/mips/Mips32/Ralloc.cc
+++ b/src/compiler/codegen/mips/Mips32/Ralloc.cc
@@ -82,7 +82,7 @@
   oatInitPool(pool->FPRegs, fpRegs, pool->numFPRegs);
   // Keep special registers from being allocated
   for (int i = 0; i < numReserved; i++) {
-    if (NO_SUSPEND && (reservedRegs[i] == rSUSPEND)) {
+    if (NO_SUSPEND && (reservedRegs[i] == rMIPS_SUSPEND)) {
       //To measure cost of suspend check
       continue;
     }
diff --git a/src/compiler/codegen/mips/MipsLIR.h b/src/compiler/codegen/mips/MipsLIR.h
index b8e5801..c0fde46 100644
--- a/src/compiler/codegen/mips/MipsLIR.h
+++ b/src/compiler/codegen/mips/MipsLIR.h
@@ -31,8 +31,8 @@
  * a0-a3 are scratch (normally hold subroutine arguments)
  * t0-t8 are scratch
  * t9 is scratch (normally used for function calls)
- * s0 (rSUSPEND) is reserved [holds suspend-check counter]
- * s1 (rSELF) is reserved [holds current &Thread]
+ * s0 (rMIPS_SUSPEND) is reserved [holds suspend-check counter]
+ * s1 (rMIPS_SELF) is reserved [holds current &Thread]
  * s2-s7 are callee save (promotion target)
  * k0, k1 are reserved for use by interrupt handlers
  * gp is reserved for global pointer
@@ -88,18 +88,17 @@
  */
 
 /* Offset to distingish FP regs */
-#define FP_REG_OFFSET 32
+#define MIPS_FP_REG_OFFSET 32
 /* Offset to distinguish DP FP regs */
-#define FP_DOUBLE 64
+#define MIPS_FP_DOUBLE 64
 /* Offset to distingish the extra regs */
-#define EXTRA_REG_OFFSET 128
+#define MIPS_EXTRA_REG_OFFSET 128
 /* Reg types */
-#define REGTYPE(x) (x & (FP_REG_OFFSET | FP_DOUBLE))
-#define FPREG(x) ((x & FP_REG_OFFSET) == FP_REG_OFFSET)
-#define EXTRAREG(x) ((x & EXTRA_REG_OFFSET) == EXTRA_REG_OFFSET)
-#define LOWREG(x) ((x & 0x1f) == x)
-#define DOUBLEREG(x) ((x & FP_DOUBLE) == FP_DOUBLE)
-#define SINGLEREG(x) (FPREG(x) && !DOUBLEREG(x))
+#define MIPS_REGTYPE(x) (x & (MIPS_FP_REG_OFFSET | MIPS_FP_DOUBLE))
+#define MIPS_FPREG(x) ((x & MIPS_FP_REG_OFFSET) == MIPS_FP_REG_OFFSET)
+#define MIPS_EXTRAREG(x) ((x & MIPS_EXTRA_REG_OFFSET) == MIPS_EXTRA_REG_OFFSET)
+#define MIPS_DOUBLEREG(x) ((x & MIPS_FP_DOUBLE) == MIPS_FP_DOUBLE)
+#define MIPS_SINGLEREG(x) (MIPS_FPREG(x) && !MIPS_DOUBLEREG(x))
 /*
  * Note: the low register of a floating point pair is sufficient to
  * create the name of a double, but require both names to be passed to
@@ -107,13 +106,9 @@
  * rework is done in this area.  Also, it is a good reminder in the calling
  * code that reg locations always describe doubles as a pair of singles.
  */
-#define S2D(x,y) ((x) | FP_DOUBLE)
+#define MIPS_S2D(x,y) ((x) | MIPS_FP_DOUBLE)
 /* Mask to strip off fp flags */
-#define FP_REG_MASK (FP_REG_OFFSET-1)
-/* non-existent Dalvik register */
-#define vNone   (-1)
-/* non-existant physical register */
-#define rNone   (-1)
+#define MIPS_FP_REG_MASK (MIPS_FP_REG_OFFSET-1)
 
 #ifdef HAVE_LITTLE_ENDIAN
 #define LOWORD_OFFSET 0
@@ -144,16 +139,17 @@
 #define r_FRESULT1 r_F1
 
 /* Regs not used for Mips */
-#define rLR INVALID_REG
+#define rMIPS_LR INVALID_REG
+#define rMIPS_PC INVALID_REG
 
 /* RegisterLocation templates return values (r_V0, or r_V0/r_V1) */
-#define LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r_V0, INVALID_REG, \
-                      INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_FLOAT {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r_FRESULT0, \
-                            INVALID_REG, INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r_RESULT0, \
-                           r_RESULT1, INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_WIDE_DOUBLE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r_FRESULT0,\
+#define MIPS_LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r_V0, INVALID_REG, \
+                           INVALID_SREG, INVALID_SREG}
+#define MIPS_LOC_C_RETURN_FLOAT {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r_FRESULT0, \
+                                 INVALID_REG, INVALID_SREG, INVALID_SREG}
+#define MIPS_LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r_RESULT0, \
+                                r_RESULT1, INVALID_SREG, INVALID_SREG}
+#define MIPS_LOC_C_RETURN_DOUBLE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r_FRESULT0,\
                                   r_FRESULT1, INVALID_SREG, INVALID_SREG}
 
 enum MipsResourceEncodingPos {
@@ -177,7 +173,7 @@
  * Annotate special-purpose core registers:
  */
 
-enum NativeRegisterPool {
+enum MipsNativeRegisterPool {
   r_ZERO = 0,
   r_AT = 1,
   r_V0 = 2,
@@ -211,7 +207,7 @@
   r_FP = 30,
   r_RA = 31,
 
-  r_F0 = 0 + FP_REG_OFFSET,
+  r_F0 = 0 + MIPS_FP_REG_OFFSET,
   r_F1,
   r_F2,
   r_F3,
@@ -245,25 +241,25 @@
   r_F30,
   r_F31,
 #endif
-  r_DF0 = r_F0 + FP_DOUBLE,
-  r_DF1 = r_F2 + FP_DOUBLE,
-  r_DF2 = r_F4 + FP_DOUBLE,
-  r_DF3 = r_F6 + FP_DOUBLE,
-  r_DF4 = r_F8 + FP_DOUBLE,
-  r_DF5 = r_F10 + FP_DOUBLE,
-  r_DF6 = r_F12 + FP_DOUBLE,
-  r_DF7 = r_F14 + FP_DOUBLE,
+  r_DF0 = r_F0 + MIPS_FP_DOUBLE,
+  r_DF1 = r_F2 + MIPS_FP_DOUBLE,
+  r_DF2 = r_F4 + MIPS_FP_DOUBLE,
+  r_DF3 = r_F6 + MIPS_FP_DOUBLE,
+  r_DF4 = r_F8 + MIPS_FP_DOUBLE,
+  r_DF5 = r_F10 + MIPS_FP_DOUBLE,
+  r_DF6 = r_F12 + MIPS_FP_DOUBLE,
+  r_DF7 = r_F14 + MIPS_FP_DOUBLE,
 #if 0 /* only 16 fp regs supported currently */
-  r_DF8 = r_F16 + FP_DOUBLE,
-  r_DF9 = r_F18 + FP_DOUBLE,
-  r_DF10 = r_F20 + FP_DOUBLE,
-  r_DF11 = r_F22 + FP_DOUBLE,
-  r_DF12 = r_F24 + FP_DOUBLE,
-  r_DF13 = r_F26 + FP_DOUBLE,
-  r_DF14 = r_F28 + FP_DOUBLE,
-  r_DF15 = r_F30 + FP_DOUBLE,
+  r_DF8 = r_F16 + MIPS_FP_DOUBLE,
+  r_DF9 = r_F18 + MIPS_FP_DOUBLE,
+  r_DF10 = r_F20 + MIPS_FP_DOUBLE,
+  r_DF11 = r_F22 + MIPS_FP_DOUBLE,
+  r_DF12 = r_F24 + MIPS_FP_DOUBLE,
+  r_DF13 = r_F26 + MIPS_FP_DOUBLE,
+  r_DF14 = r_F28 + MIPS_FP_DOUBLE,
+  r_DF15 = r_F30 + MIPS_FP_DOUBLE,
 #endif
-  r_HI = EXTRA_REG_OFFSET,
+  r_HI = MIPS_EXTRA_REG_OFFSET,
   r_LO,
   r_PC,
 };
@@ -272,21 +268,21 @@
  * Target-independent aliases
  */
 
-#define rSUSPEND r_S0
-#define rSELF r_S1
-#define rSP r_SP
-#define rARG0 r_ARG0
-#define rARG1 r_ARG1
-#define rARG2 r_ARG2
-#define rARG3 r_ARG3
-#define rFARG0 r_FARG0
-#define rFARG1 r_FARG1
-#define rFARG2 r_FARG2
-#define rFARG3 r_FARG3
-#define rRET0 r_RESULT0
-#define rRET1 r_RESULT1
-#define rINVOKE_TGT r_T9
-#define rCOUNT INVALID_REG
+#define rMIPS_SUSPEND r_S0
+#define rMIPS_SELF r_S1
+#define rMIPS_SP r_SP
+#define rMIPS_ARG0 r_ARG0
+#define rMIPS_ARG1 r_ARG1
+#define rMIPS_ARG2 r_ARG2
+#define rMIPS_ARG3 r_ARG3
+#define rMIPS_FARG0 r_FARG0
+#define rMIPS_FARG1 r_FARG1
+#define rMIPS_FARG2 r_FARG2
+#define rMIPS_FARG3 r_FARG3
+#define rMIPS_RET0 r_RESULT0
+#define rMIPS_RET1 r_RESULT1
+#define rMIPS_INVOKE_TGT r_T9
+#define rMIPS_COUNT INVALID_REG
 
 /* Shift encodings */
 enum MipsShiftEncodings {
diff --git a/src/compiler/codegen/mips/MipsRallocUtil.cc b/src/compiler/codegen/mips/MipsRallocUtil.cc
index bd9f97e..4979ae0 100644
--- a/src/compiler/codegen/mips/MipsRallocUtil.cc
+++ b/src/compiler/codegen/mips/MipsRallocUtil.cc
@@ -68,7 +68,7 @@
     if (SRegToVReg(cUnit, info2->sReg) < SRegToVReg(cUnit, info1->sReg))
       info1 = info2;
     int vReg = SRegToVReg(cUnit, info1->sReg);
-    oatFlushRegWideImpl(cUnit, rSP, oatVRegOffset(cUnit, vReg), info1->reg,
+    oatFlushRegWideImpl(cUnit, rMIPS_SP, oatVRegOffset(cUnit, vReg), info1->reg,
                         info1->partner);
   }
 }
@@ -79,17 +79,17 @@
   if (info->live && info->dirty) {
     info->dirty = false;
     int vReg = SRegToVReg(cUnit, info->sReg);
-    oatFlushRegImpl(cUnit, rSP, oatVRegOffset(cUnit, vReg), reg, kWord);
+    oatFlushRegImpl(cUnit, rMIPS_SP, oatVRegOffset(cUnit, vReg), reg, kWord);
   }
 }
 
 /* Give access to the target-dependent FP register encoding to common code */
 bool oatIsFpReg(int reg) {
-  return FPREG(reg);
+  return MIPS_FPREG(reg);
 }
 
 uint32_t oatFpRegMask() {
-  return FP_REG_MASK;
+  return MIPS_FP_REG_MASK;
 }
 
 /* Clobber all regs that might be used by an external C call */
@@ -139,39 +139,39 @@
 extern RegLocation oatGetReturnWideAlt(CompilationUnit* cUnit)
 {
   UNIMPLEMENTED(FATAL) << "No oatGetReturnWideAlt for MIPS";
-  RegLocation res = LOC_C_RETURN_WIDE;
+  RegLocation res = locCReturnWide();
   return res;
 }
 
 extern RegLocation oatGetReturnAlt(CompilationUnit* cUnit)
 {
   UNIMPLEMENTED(FATAL) << "No oatGetReturnAlt for MIPS";
-  RegLocation res = LOC_C_RETURN;
+  RegLocation res = locCReturn();
   return res;
 }
 
 extern RegisterInfo* oatGetRegInfo(CompilationUnit* cUnit, int reg)
 {
-  return FPREG(reg) ? &cUnit->regPool->FPRegs[reg & FP_REG_MASK]
+  return MIPS_FPREG(reg) ? &cUnit->regPool->FPRegs[reg & MIPS_FP_REG_MASK]
             : &cUnit->regPool->coreRegs[reg];
 }
 
 /* To be used when explicitly managing register use */
 extern void oatLockCallTemps(CompilationUnit* cUnit)
 {
-  oatLockTemp(cUnit, rARG0);
-  oatLockTemp(cUnit, rARG1);
-  oatLockTemp(cUnit, rARG2);
-  oatLockTemp(cUnit, rARG3);
+  oatLockTemp(cUnit, rMIPS_ARG0);
+  oatLockTemp(cUnit, rMIPS_ARG1);
+  oatLockTemp(cUnit, rMIPS_ARG2);
+  oatLockTemp(cUnit, rMIPS_ARG3);
 }
 
 /* To be used when explicitly managing register use */
 extern void oatFreeCallTemps(CompilationUnit* cUnit)
 {
-  oatFreeTemp(cUnit, rARG0);
-  oatFreeTemp(cUnit, rARG1);
-  oatFreeTemp(cUnit, rARG2);
-  oatFreeTemp(cUnit, rARG3);
+  oatFreeTemp(cUnit, rMIPS_ARG0);
+  oatFreeTemp(cUnit, rMIPS_ARG1);
+  oatFreeTemp(cUnit, rMIPS_ARG2);
+  oatFreeTemp(cUnit, rMIPS_ARG3);
 }
 
 /* Convert an instruction to a NOP */
diff --git a/src/compiler/codegen/x86/ArchFactory.cc b/src/compiler/codegen/x86/ArchFactory.cc
index 1fc1034..0ed6848 100644
--- a/src/compiler/codegen/x86/ArchFactory.cc
+++ b/src/compiler/codegen/x86/ArchFactory.cc
@@ -123,7 +123,7 @@
   int offset = cUnit->frameSize - (4 * cUnit->numCoreSpills);
   for (int reg = 0; mask; mask >>= 1, reg++) {
     if (mask & 0x1) {
-      storeWordDisp(cUnit, rSP, offset, reg);
+      storeWordDisp(cUnit, rX86_SP, offset, reg);
       offset += 4;
     }
   }
@@ -138,7 +138,7 @@
   int offset = cUnit->frameSize - (4 * cUnit->numCoreSpills);
   for (int reg = 0; mask; mask >>= 1, reg++) {
     if (mask & 0x1) {
-      loadWordDisp(cUnit, rSP, offset, reg);
+      loadWordDisp(cUnit, rX86_SP, offset, reg);
       offset += 4;
     }
   }
@@ -159,17 +159,17 @@
                       RegLocation rlMethod)
 {
   /*
-   * On entry, rARG0, rARG1, rARG2 are live.  Let the register
+   * On entry, rX86_ARG0, rX86_ARG1, rX86_ARG2 are live.  Let the register
    * allocation mechanism know so it doesn't try to use any of them when
    * expanding the frame or flushing.  This leaves the utility
    * code with no spare temps.
    */
-  oatLockTemp(cUnit, rARG0);
-  oatLockTemp(cUnit, rARG1);
-  oatLockTemp(cUnit, rARG2);
+  oatLockTemp(cUnit, rX86_ARG0);
+  oatLockTemp(cUnit, rX86_ARG1);
+  oatLockTemp(cUnit, rX86_ARG2);
 
   /* Build frame, return address already on stack */
-  opRegImm(cUnit, kOpSub, rSP, cUnit->frameSize - 4);
+  opRegImm(cUnit, kOpSub, rX86_SP, cUnit->frameSize - 4);
 
   /*
    * We can safely skip the stack overflow check if we're
@@ -184,9 +184,9 @@
   /* NOTE: promotion of FP regs currently unsupported, thus no FP spill */
   DCHECK_EQ(cUnit->numFPSpills, 0);
   if (!skipOverflowCheck) {
-    // cmp rSP, fs:[stack_end_]; jcc throw_launchpad
+    // cmp rX86_SP, fs:[stack_end_]; jcc throw_launchpad
     LIR* tgt = rawLIR(cUnit, 0, kPseudoThrowTarget, kThrowStackOverflow, 0, 0, 0, 0);
-    opRegThreadMem(cUnit, kOpCmp, rSP, Thread::StackEndOffset().Int32Value());
+    opRegThreadMem(cUnit, kOpCmp, rX86_SP, Thread::StackEndOffset().Int32Value());
     opCondBranch(cUnit, kCondUlt, tgt);
     // Remember branch target - will process later
     oatInsertGrowableList(cUnit, &cUnit->throwLaunchpads, (intptr_t)tgt);
@@ -194,23 +194,23 @@
 
   flushIns(cUnit, argLocs, rlMethod);
 
-  oatFreeTemp(cUnit, rARG0);
-  oatFreeTemp(cUnit, rARG1);
-  oatFreeTemp(cUnit, rARG2);
+  oatFreeTemp(cUnit, rX86_ARG0);
+  oatFreeTemp(cUnit, rX86_ARG1);
+  oatFreeTemp(cUnit, rX86_ARG2);
 }
 
 void genExitSequence(CompilationUnit* cUnit) {
   /*
-   * In the exit path, rRET0/rRET1 are live - make sure they aren't
+   * In the exit path, rX86_RET0/rX86_RET1 are live - make sure they aren't
    * allocated by the register utilities as temps.
    */
-  oatLockTemp(cUnit, rRET0);
-  oatLockTemp(cUnit, rRET1);
+  oatLockTemp(cUnit, rX86_RET0);
+  oatLockTemp(cUnit, rX86_RET1);
 
   newLIR0(cUnit, kPseudoMethodExit);
   unSpillCoreRegs(cUnit);
   /* Remove frame except for return address */
-  opRegImm(cUnit, kOpAdd, rSP, cUnit->frameSize - 4);
+  opRegImm(cUnit, kOpAdd, rX86_SP, cUnit->frameSize - 4);
   newLIR0(cUnit, kX86Ret);
 }
 
diff --git a/src/compiler/codegen/x86/ArchUtility.cc b/src/compiler/codegen/x86/ArchUtility.cc
index 953ce4a..32dd811 100644
--- a/src/compiler/codegen/x86/ArchUtility.cc
+++ b/src/compiler/codegen/x86/ArchUtility.cc
@@ -22,6 +22,91 @@
 
 namespace art {
 
+RegLocation locCReturn()
+{
+  RegLocation res = X86_LOC_C_RETURN;
+  return res;
+}
+
+RegLocation locCReturnWide()
+{
+  RegLocation res = X86_LOC_C_RETURN_WIDE;
+  return res;
+}
+
+RegLocation locCReturnFloat()
+{
+  RegLocation res = X86_LOC_C_RETURN_FLOAT;
+  return res;
+}
+
+RegLocation locCReturnDouble()
+{
+  RegLocation res = X86_LOC_C_RETURN_DOUBLE;
+  return res;
+}
+
+// Return a target-dependent special register.
+int targetReg(SpecialTargetRegister reg) {
+  int res = INVALID_REG;
+  switch (reg) {
+    case kSelf: res = rX86_SELF; break;
+    case kSuspend: res =  rX86_SUSPEND; break;
+    case kLr: res =  rX86_LR; break;
+    case kPc: res =  rX86_PC; break;
+    case kSp: res =  rX86_SP; break;
+    case kArg0: res = rX86_ARG0; break;
+    case kArg1: res = rX86_ARG1; break;
+    case kArg2: res = rX86_ARG2; break;
+    case kArg3: res = rX86_ARG3; break;
+    case kFArg0: res = rX86_FARG0; break;
+    case kFArg1: res = rX86_FARG1; break;
+    case kFArg2: res = rX86_FARG2; break;
+    case kFArg3: res = rX86_FARG3; break;
+    case kRet0: res = rX86_RET0; break;
+    case kRet1: res = rX86_RET1; break;
+    case kInvokeTgt: res = rX86_INVOKE_TGT; break;
+    case kCount: res = rX86_COUNT; break;
+  }
+  return res;
+}
+
+// Create a double from a pair of singles.
+int s2d(int lowReg, int highReg)
+{
+  return X86_S2D(lowReg, highReg);
+}
+
+// Is reg a single or double?
+bool fpReg(int reg)
+{
+  return X86_FPREG(reg);
+}
+
+// Is reg a single?
+bool singleReg(int reg)
+{
+  return X86_SINGLEREG(reg);
+}
+
+// Is reg a double?
+bool doubleReg(int reg)
+{
+  return X86_DOUBLEREG(reg);
+}
+
+// Return mask to strip off fp reg flags and bias.
+uint32_t fpRegMask()
+{
+  return X86_FP_REG_MASK;
+}
+
+// True if both regs single, both core or both double.
+bool sameRegType(int reg1, int reg2)
+{
+  return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2));
+}
+
 /*
  * Decode the register id.
  */
@@ -35,7 +120,7 @@
   /* Double registers in x86 are just a single FP register */
   seed = 1;
   /* FP register starts at bit position 16 */
-  shift = FPREG(reg) ? kX86FPReg0 : 0;
+  shift = X86_FPREG(reg) ? kX86FPReg0 : 0;
   /* Expand the double register id into single offset */
   shift += regId;
   return (seed << shift);
@@ -149,8 +234,8 @@
             break;
           }
           case 'r':
-            if (FPREG(operand) || DOUBLEREG(operand)) {
-              int fp_reg = operand & FP_REG_MASK;
+            if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) {
+              int fp_reg = operand & X86_FP_REG_MASK;
               buf += StringPrintf("xmm%d", fp_reg);
             } else {
               DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName));
diff --git a/src/compiler/codegen/x86/Assemble.cc b/src/compiler/codegen/x86/Assemble.cc
index 71fcdc8..a5388e8 100644
--- a/src/compiler/codegen/x86/Assemble.cc
+++ b/src/compiler/codegen/x86/Assemble.cc
@@ -376,7 +376,7 @@
       int disp = lir->operands[1];
       // SP requires a special extra SIB byte. BP requires explicit disp,
       // so add a byte for disp 0 which would normally be omitted.
-      return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);
+      return computeSize(entry, disp, false) + ((base == rX86_SP) || (base == rBP && disp == 0) ? 1 : 0);
     }
     case kArray:  // lir operands - 0: base, 1: index, 2: scale, 3: disp
       return computeSize(entry, lir->operands[3], true);
@@ -385,7 +385,7 @@
       int disp = lir->operands[1];
       // SP requires a special extra SIB byte. BP requires explicit disp,
       // so add a byte for disp 0 which would normally be omitted.
-      return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);
+      return computeSize(entry, disp, false) + ((base == rX86_SP) || (base == rBP && disp == 0) ? 1 : 0);
     }
     case kArrayReg:  // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg
       return computeSize(entry, lir->operands[3], true);
@@ -400,7 +400,7 @@
       int disp = lir->operands[2];
       // SP requires a special extra SIB byte. BP requires explicit disp,
       // so add a byte for disp 0 which would normally be omitted.
-      return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);
+      return computeSize(entry, disp, false) + ((base == rX86_SP) || (base == rBP && disp == 0) ? 1 : 0);
     }
     case kRegArray:  { // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp
       int base = lir->operands[1];
@@ -421,7 +421,7 @@
       }
     }
     case kMemImm:  // lir operands - 0: base, 1: disp, 2: immediate
-      CHECK_NE(lir->operands[0], static_cast<int>(rSP));  // TODO: add extra SIB byte
+      CHECK_NE(lir->operands[0], static_cast<int>(rX86_SP));  // TODO: add extra SIB byte
       return computeSize(entry, lir->operands[1], false);
     case kArrayImm:  // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate
       return computeSize(entry, lir->operands[3], true);
@@ -430,7 +430,7 @@
     case kRegRegImm:  // lir operands - 0: reg, 1: reg, 2: imm
       return computeSize(entry, 0, false);
     case kRegMemImm:  // lir operands - 0: reg, 1: base, 2: disp, 3: imm
-      CHECK_NE(lir->operands[1], static_cast<int>(rSP));  // TODO: add extra SIB byte
+      CHECK_NE(lir->operands[1], static_cast<int>(rX86_SP));  // TODO: add extra SIB byte
       return computeSize(entry, lir->operands[2], false);
     case kRegArrayImm:  // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm
       return computeSize(entry, lir->operands[4], true);
@@ -440,7 +440,7 @@
       // Shift by immediate one has a shorter opcode.
       return computeSize(entry, 0, false) - (lir->operands[1] == 1 ? 1 : 0);
     case kShiftMemImm:  // lir operands - 0: base, 1: disp, 2: immediate
-      CHECK_NE(lir->operands[0], static_cast<int>(rSP));  // TODO: add extra SIB byte
+      CHECK_NE(lir->operands[0], static_cast<int>(rX86_SP));  // TODO: add extra SIB byte
       // Shift by immediate one has a shorter opcode.
       return computeSize(entry, lir->operands[1], false) - (lir->operands[2] == 1 ? 1 : 0);
     case kShiftArrayImm:  // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate
@@ -449,14 +449,14 @@
     case kShiftRegCl:
       return computeSize(entry, 0, false);
     case kShiftMemCl:  // lir operands - 0: base, 1: disp, 2: cl
-      CHECK_NE(lir->operands[0], static_cast<int>(rSP));  // TODO: add extra SIB byte
+      CHECK_NE(lir->operands[0], static_cast<int>(rX86_SP));  // TODO: add extra SIB byte
       return computeSize(entry, lir->operands[1], false);
     case kShiftArrayCl:  // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg
       return computeSize(entry, lir->operands[3], true);
     case kRegCond:  // lir operands - 0: reg, 1: cond
       return computeSize(entry, 0, false);
     case kMemCond:  // lir operands - 0: base, 1: disp, 2: cond
-      CHECK_NE(lir->operands[0], static_cast<int>(rSP));  // TODO: add extra SIB byte
+      CHECK_NE(lir->operands[0], static_cast<int>(rX86_SP));  // TODO: add extra SIB byte
       return computeSize(entry, lir->operands[1], false);
     case kArrayCond:  // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond
       return computeSize(entry, lir->operands[3], true);
@@ -555,8 +555,8 @@
     DCHECK_EQ(0, entry->skeleton.extra_opcode1);
     DCHECK_EQ(0, entry->skeleton.extra_opcode2);
   }
-  if (FPREG(reg)) {
-    reg = reg & FP_REG_MASK;
+  if (X86_FPREG(reg)) {
+    reg = reg & X86_FP_REG_MASK;
   }
   if (reg >= 4) {
     DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg
@@ -612,8 +612,8 @@
     DCHECK_EQ(0, entry->skeleton.extra_opcode1);
     DCHECK_EQ(0, entry->skeleton.extra_opcode2);
   }
-  if (FPREG(reg)) {
-    reg = reg & FP_REG_MASK;
+  if (X86_FPREG(reg)) {
+    reg = reg & X86_FP_REG_MASK;
   }
   if (reg >= 4) {
     DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg
@@ -623,9 +623,9 @@
   DCHECK_LT(base, 8);
   uint8_t modrm = (modrmForDisp(base, disp) << 6) | (reg << 3) | base;
   cUnit->codeBuffer.push_back(modrm);
-  if (base == rSP) {
+  if (base == rX86_SP) {
     // Special SIB for SP base
-    cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);
+    cUnit->codeBuffer.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);
   }
   emitDisp(cUnit, base, disp);
   DCHECK_EQ(0, entry->skeleton.modrm_opcode);
@@ -661,11 +661,11 @@
     DCHECK_EQ(0, entry->skeleton.extra_opcode1);
     DCHECK_EQ(0, entry->skeleton.extra_opcode2);
   }
-  if (FPREG(reg)) {
-    reg = reg & FP_REG_MASK;
+  if (X86_FPREG(reg)) {
+    reg = reg & X86_FP_REG_MASK;
   }
   DCHECK_LT(reg, 8);
-  uint8_t modrm = (modrmForDisp(base, disp) << 6) | (reg << 3) | rSP;
+  uint8_t modrm = (modrmForDisp(base, disp) << 6) | (reg << 3) | rX86_SP;
   cUnit->codeBuffer.push_back(modrm);
   DCHECK_LT(scale, 4);
   DCHECK_LT(index, 8);
@@ -703,8 +703,8 @@
     DCHECK_EQ(0, entry->skeleton.extra_opcode1);
     DCHECK_EQ(0, entry->skeleton.extra_opcode2);
   }
-  if (FPREG(reg)) {
-    reg = reg & FP_REG_MASK;
+  if (X86_FPREG(reg)) {
+    reg = reg & X86_FP_REG_MASK;
   }
   if (reg >= 4) {
     DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg
@@ -744,11 +744,11 @@
     DCHECK_EQ(0, entry->skeleton.extra_opcode1);
     DCHECK_EQ(0, entry->skeleton.extra_opcode2);
   }
-  if (FPREG(reg1)) {
-    reg1 = reg1 & FP_REG_MASK;
+  if (X86_FPREG(reg1)) {
+    reg1 = reg1 & X86_FP_REG_MASK;
   }
-  if (FPREG(reg2)) {
-    reg2 = reg2 & FP_REG_MASK;
+  if (X86_FPREG(reg2)) {
+    reg2 = reg2 & X86_FP_REG_MASK;
   }
   DCHECK_LT(reg1, 8);
   DCHECK_LT(reg2, 8);
@@ -781,11 +781,11 @@
     DCHECK_EQ(0, entry->skeleton.extra_opcode1);
     DCHECK_EQ(0, entry->skeleton.extra_opcode2);
   }
-  if (FPREG(reg1)) {
-    reg1 = reg1 & FP_REG_MASK;
+  if (X86_FPREG(reg1)) {
+    reg1 = reg1 & X86_FP_REG_MASK;
   }
-  if (FPREG(reg2)) {
-    reg2 = reg2 & FP_REG_MASK;
+  if (X86_FPREG(reg2)) {
+    reg2 = reg2 & X86_FP_REG_MASK;
   }
   DCHECK_LT(reg1, 8);
   DCHECK_LT(reg2, 8);
@@ -841,8 +841,8 @@
       DCHECK_EQ(0, entry->skeleton.extra_opcode1);
       DCHECK_EQ(0, entry->skeleton.extra_opcode2);
     }
-    if (FPREG(reg)) {
-      reg = reg & FP_REG_MASK;
+    if (X86_FPREG(reg)) {
+      reg = reg & X86_FP_REG_MASK;
     }
     uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;
     cUnit->codeBuffer.push_back(modrm);
@@ -1079,9 +1079,9 @@
   }
   uint8_t modrm = (modrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;
   cUnit->codeBuffer.push_back(modrm);
-  if (base == rSP) {
+  if (base == rX86_SP) {
     // Special SIB for SP base
-    cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);
+    cUnit->codeBuffer.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);
   }
   emitDisp(cUnit, base, disp);
   DCHECK_EQ(0, entry->skeleton.ax_opcode);
@@ -1135,15 +1135,15 @@
   } else {
     DCHECK_EQ(0, entry->skeleton.prefix2);
   }
-  if (FPREG(reg)) {
-    reg = reg & FP_REG_MASK;
+  if (X86_FPREG(reg)) {
+    reg = reg & X86_FP_REG_MASK;
   }
   DCHECK_LT(reg, 8);
   if (entry->opcode == kX86PcRelLoadRA) {
     cUnit->codeBuffer.push_back(entry->skeleton.opcode);
     DCHECK_EQ(0, entry->skeleton.extra_opcode1);
     DCHECK_EQ(0, entry->skeleton.extra_opcode2);
-    uint8_t modrm = (2 << 6) | (reg << 3) | rSP;
+    uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP;
     cUnit->codeBuffer.push_back(modrm);
     DCHECK_LT(scale, 4);
     DCHECK_LT(index, 8);
diff --git a/src/compiler/codegen/x86/FP/X86FP.cc b/src/compiler/codegen/x86/FP/X86FP.cc
index af6ddb0..5e97a50 100644
--- a/src/compiler/codegen/x86/FP/X86FP.cc
+++ b/src/compiler/codegen/x86/FP/X86FP.cc
@@ -104,11 +104,11 @@
   rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
   DCHECK(rlDest.wide);
   DCHECK(rlResult.wide);
-  int rDest = S2D(rlResult.lowReg, rlResult.highReg);
-  int rSrc1 = S2D(rlSrc1.lowReg, rlSrc1.highReg);
-  int rSrc2 = S2D(rlSrc2.lowReg, rlSrc2.highReg);
+  int rDest = s2d(rlResult.lowReg, rlResult.highReg);
+  int rSrc1 = s2d(rlSrc1.lowReg, rlSrc1.highReg);
+  int rSrc2 = s2d(rlSrc2.lowReg, rlSrc2.highReg);
   if (rDest == rSrc2) {
-    rSrc2 = oatAllocTempDouble(cUnit) | FP_DOUBLE;
+    rSrc2 = oatAllocTempDouble(cUnit) | X86_FP_DOUBLE;
     opRegCopy(cUnit, rSrc2, rDest);
   }
   opRegCopy(cUnit, rDest, rSrc1);
@@ -166,7 +166,7 @@
       srcReg = rlSrc.lowReg;
       oatClobberSReg(cUnit, rlDest.sRegLow);
       rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
-      int tempReg = oatAllocTempDouble(cUnit) | FP_DOUBLE;
+      int tempReg = oatAllocTempDouble(cUnit) | X86_FP_DOUBLE;
 
       loadConstant(cUnit, rlResult.lowReg, 0x7fffffff);
       newLIR2(cUnit, kX86Cvtsi2sdRR, tempReg, rlResult.lowReg);
@@ -193,14 +193,14 @@
   }
   if (rlSrc.wide) {
     rlSrc = loadValueWide(cUnit, rlSrc, rcSrc);
-    srcReg = S2D(rlSrc.lowReg, rlSrc.highReg);
+    srcReg = s2d(rlSrc.lowReg, rlSrc.highReg);
   } else {
     rlSrc = loadValue(cUnit, rlSrc, rcSrc);
     srcReg = rlSrc.lowReg;
   }
   if (rlDest.wide) {
     rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
-    newLIR2(cUnit, op, S2D(rlResult.lowReg, rlResult.highReg), srcReg);
+    newLIR2(cUnit, op, s2d(rlResult.lowReg, rlResult.highReg), srcReg);
     storeValueWide(cUnit, rlDest, rlResult);
   } else {
     rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
@@ -223,9 +223,9 @@
     srcReg2 = rlSrc2.lowReg;
   } else {
     rlSrc1 = loadValueWide(cUnit, rlSrc1, kFPReg);
-    srcReg1 = S2D(rlSrc1.lowReg, rlSrc1.highReg);
+    srcReg1 = s2d(rlSrc1.lowReg, rlSrc1.highReg);
     rlSrc2 = loadValueWide(cUnit, rlSrc2, kFPReg);
-    srcReg2 = S2D(rlSrc2.lowReg, rlSrc2.highReg);
+    srcReg2 = s2d(rlSrc2.lowReg, rlSrc2.highReg);
   }
   oatClobberSReg(cUnit, rlDest.sRegLow);
   RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
@@ -274,8 +274,8 @@
     rlSrc2 = oatGetSrcWide(cUnit, mir, 2);
     rlSrc1 = loadValueWide(cUnit, rlSrc1, kFPReg);
     rlSrc2 = loadValueWide(cUnit, rlSrc2, kFPReg);
-    newLIR2(cUnit, kX86UcomisdRR, S2D(rlSrc1.lowReg, rlSrc1.highReg),
-            S2D(rlSrc2.lowReg, rlSrc2.highReg));
+    newLIR2(cUnit, kX86UcomisdRR, s2d(rlSrc1.lowReg, rlSrc1.highReg),
+            s2d(rlSrc2.lowReg, rlSrc2.highReg));
   } else {
     rlSrc1 = oatGetSrc(cUnit, mir, 0);
     rlSrc2 = oatGetSrc(cUnit, mir, 1);
diff --git a/src/compiler/codegen/x86/X86/Factory.cc b/src/compiler/codegen/x86/X86/Factory.cc
index 040ef17..454b98d 100644
--- a/src/compiler/codegen/x86/X86/Factory.cc
+++ b/src/compiler/codegen/x86/X86/Factory.cc
@@ -20,12 +20,12 @@
 
 //FIXME: restore "static" when usage uncovered
 /*static*/ int coreRegs[] = {
-  rAX, rCX, rDX, rBX, rSP, rBP, rSI, rDI
+  rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI
 #ifdef TARGET_REX_SUPPORT
   r8, r9, r10, r11, r12, r13, r14, 15
 #endif
 };
-/*static*/ int reservedRegs[] = {rSP};
+/*static*/ int reservedRegs[] = {rX86_SP};
 /*static*/ int coreTemps[] = {rAX, rCX, rDX, rBX};
 /*static*/ int fpRegs[] = {
   fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
@@ -52,18 +52,18 @@
 {
   int opcode;
   /* must be both DOUBLE or both not DOUBLE */
-  DCHECK_EQ(DOUBLEREG(rDest), DOUBLEREG(rSrc));
-  if (DOUBLEREG(rDest)) {
+  DCHECK_EQ(X86_DOUBLEREG(rDest), X86_DOUBLEREG(rSrc));
+  if (X86_DOUBLEREG(rDest)) {
     opcode = kX86MovsdRR;
   } else {
-    if (SINGLEREG(rDest)) {
-      if (SINGLEREG(rSrc)) {
+    if (X86_SINGLEREG(rDest)) {
+      if (X86_SINGLEREG(rSrc)) {
         opcode = kX86MovssRR;
       } else {  // Fpr <- Gpr
         opcode = kX86MovdxrRR;
       }
     } else {  // Gpr <- Fpr
-      DCHECK(SINGLEREG(rSrc));
+      DCHECK(X86_SINGLEREG(rSrc));
       opcode = kX86MovdrxRR;
     }
   }
@@ -87,11 +87,11 @@
 LIR *loadConstantNoClobber(CompilationUnit *cUnit, int rDest, int value)
 {
   int rDestSave = rDest;
-  if (FPREG(rDest)) {
+  if (X86_FPREG(rDest)) {
     if (value == 0) {
       return newLIR2(cUnit, kX86XorpsRR, rDest, rDest);
     }
-    DCHECK(SINGLEREG(rDest));
+    DCHECK(X86_SINGLEREG(rDest));
     rDest = oatAllocTemp(cUnit);
   }
 
@@ -103,7 +103,7 @@
     res = newLIR2(cUnit, kX86Mov32RI, rDest, value);
   }
 
-  if (FPREG(rDestSave)) {
+  if (X86_FPREG(rDestSave)) {
     newLIR2(cUnit, kX86MovdxrRR, rDestSave, rDest);
     oatFreeTemp(cUnit, rDest);
   }
@@ -145,7 +145,7 @@
 {
   X86OpCode opcode = kX86Bkpt;
   bool byteImm = IS_SIMM8(value);
-  DCHECK(!FPREG(rDestSrc1));
+  DCHECK(!X86_FPREG(rDestSrc1));
   switch (op) {
     case kOpLsl: opcode = kX86Sal32RI; break;
     case kOpLsr: opcode = kX86Shr32RI; break;
@@ -342,8 +342,8 @@
                            int rDestHi, int valLo, int valHi)
 {
     LIR *res;
-    if (FPREG(rDestLo)) {
-      DCHECK(FPREG(rDestHi));  // ignore rDestHi
+    if (X86_FPREG(rDestLo)) {
+      DCHECK(X86_FPREG(rDestHi));  // ignore rDestHi
       if (valLo == 0 && valHi == 0) {
         return newLIR2(cUnit, kX86XorpsRR, rDestLo, rDestLo);
       } else {
@@ -393,12 +393,12 @@
     case kLong:
     case kDouble:
       is64bit = true;
-      if (FPREG(rDest)) {
+      if (X86_FPREG(rDest)) {
         opcode = isArray ? kX86MovsdRA : kX86MovsdRM;
-        if (SINGLEREG(rDest)) {
-          DCHECK(FPREG(rDestHi));
+        if (X86_SINGLEREG(rDest)) {
+          DCHECK(X86_FPREG(rDestHi));
           DCHECK_EQ(rDest, (rDestHi - 1));
-          rDest = S2D(rDest, rDestHi);
+          rDest = s2d(rDest, rDestHi);
         }
         rDestHi = rDest + 1;
       } else {
@@ -411,9 +411,9 @@
     case kWord:
     case kSingle:
       opcode = isArray ? kX86Mov32RA : kX86Mov32RM;
-      if (FPREG(rDest)) {
+      if (X86_FPREG(rDest)) {
         opcode = isArray ? kX86MovssRA : kX86MovssRM;
-        DCHECK(SINGLEREG(rDest));
+        DCHECK(X86_SINGLEREG(rDest));
       }
       DCHECK_EQ((displacement & 0x3), 0);
       break;
@@ -449,7 +449,7 @@
                         displacement + HIWORD_OFFSET);
       }
     }
-    if (rBase == rSP) {
+    if (rBase == rX86_SP) {
       annotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0))
                               >> 2, true /* isLoad */, is64bit);
       if (pair) {
@@ -516,12 +516,12 @@
     case kLong:
     case kDouble:
       is64bit = true;
-      if (FPREG(rSrc)) {
+      if (X86_FPREG(rSrc)) {
         opcode = isArray ? kX86MovsdAR : kX86MovsdMR;
-        if (SINGLEREG(rSrc)) {
-          DCHECK(FPREG(rSrcHi));
+        if (X86_SINGLEREG(rSrc)) {
+          DCHECK(X86_FPREG(rSrcHi));
           DCHECK_EQ(rSrc, (rSrcHi - 1));
-          rSrc = S2D(rSrc, rSrcHi);
+          rSrc = s2d(rSrc, rSrcHi);
         }
         rSrcHi = rSrc + 1;
       } else {
@@ -534,9 +534,9 @@
     case kWord:
     case kSingle:
       opcode = isArray ? kX86Mov32AR : kX86Mov32MR;
-      if (FPREG(rSrc)) {
+      if (X86_FPREG(rSrc)) {
         opcode = isArray ? kX86MovssAR : kX86MovssMR;
-        DCHECK(SINGLEREG(rSrc));
+        DCHECK(X86_SINGLEREG(rSrc));
       }
       DCHECK_EQ((displacement & 0x3), 0);
       break;
@@ -560,7 +560,7 @@
       store = newLIR3(cUnit, opcode, rBase, displacement + LOWORD_OFFSET, rSrc);
       store2 = newLIR3(cUnit, opcode, rBase, displacement + HIWORD_OFFSET, rSrcHi);
     }
-    if (rBase == rSP) {
+    if (rBase == rX86_SP) {
       annotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0))
                               >> 2, false /* isLoad */, is64bit);
       if (pair) {
diff --git a/src/compiler/codegen/x86/X86/Gen.cc b/src/compiler/codegen/x86/X86/Gen.cc
index b57acac..37cd725 100644
--- a/src/compiler/codegen/x86/X86/Gen.cc
+++ b/src/compiler/codegen/x86/X86/Gen.cc
@@ -163,12 +163,12 @@
 
   // Making a call - use explicit registers
   oatFlushAllRegs(cUnit);   /* Everything to home location */
-  loadValueDirectFixed(cUnit, rlSrc, rARG0);
+  loadValueDirectFixed(cUnit, rlSrc, rX86_ARG0);
   // Materialize a pointer to the fill data image
-  newLIR1(cUnit, kX86StartOfMethod, rARG2);
-  newLIR2(cUnit, kX86PcRelAdr, rARG1, (intptr_t)tabRec);
-  newLIR2(cUnit, kX86Add32RR, rARG1, rARG2);
-  callRuntimeHelperRegReg(cUnit, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode), rARG0, rARG1,
+  newLIR1(cUnit, kX86StartOfMethod, rX86_ARG2);
+  newLIR2(cUnit, kX86PcRelAdr, rX86_ARG1, (intptr_t)tabRec);
+  newLIR2(cUnit, kX86Add32RR, rX86_ARG1, rX86_ARG2);
+  callRuntimeHelperRegReg(cUnit, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode), rX86_ARG0, rX86_ARG1,
                           true);
 }
 
@@ -266,7 +266,7 @@
   newLIR2(cUnit, kX86Set8R, r0, kX86CondNz);  // r0 = (r1:r0) != (r3:r2) ? 1 : 0
   newLIR2(cUnit, kX86Movzx8RR, r0, r0);
   opRegReg(cUnit, kOpOr, r0, r2);   // r0 = r0 | r2
-  RegLocation rlResult = LOC_C_RETURN;
+  RegLocation rlResult = locCReturn();
   storeValue(cUnit, rlDest, rlResult);
 }
 
@@ -320,7 +320,7 @@
 
 LIR* opRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
 {
-  if (FPREG(rDest) || FPREG(rSrc))
+  if (X86_FPREG(rDest) || X86_FPREG(rSrc))
     return fpRegCopy(cUnit, rDest, rSrc);
   LIR* res = rawLIR(cUnit, cUnit->currentDalvikOffset, kX86Mov32RR,
                     rDest, rSrc);
@@ -340,13 +340,13 @@
 void opRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
                    int srcLo, int srcHi)
 {
-  bool destFP = FPREG(destLo) && FPREG(destHi);
-  bool srcFP = FPREG(srcLo) && FPREG(srcHi);
-  assert(FPREG(srcLo) == FPREG(srcHi));
-  assert(FPREG(destLo) == FPREG(destHi));
+  bool destFP = X86_FPREG(destLo) && X86_FPREG(destHi);
+  bool srcFP = X86_FPREG(srcLo) && X86_FPREG(srcHi);
+  assert(X86_FPREG(srcLo) == X86_FPREG(srcHi));
+  assert(X86_FPREG(destLo) == X86_FPREG(destHi));
   if (destFP) {
     if (srcFP) {
-      opRegCopy(cUnit, S2D(destLo, destHi), S2D(srcLo, srcHi));
+      opRegCopy(cUnit, s2d(destLo, destHi), s2d(srcLo, srcHi));
     } else {
       // TODO: Prevent this from happening in the code. The result is often
       // unused or could have been loaded more easily from memory.
diff --git a/src/compiler/codegen/x86/X86LIR.h b/src/compiler/codegen/x86/X86LIR.h
index 59b1859..bccd365 100644
--- a/src/compiler/codegen/x86/X86LIR.h
+++ b/src/compiler/codegen/x86/X86LIR.h
@@ -105,18 +105,17 @@
  */
 
 /* Offset to distingish FP regs */
-#define FP_REG_OFFSET 32
+#define X86_FP_REG_OFFSET 32
 /* Offset to distinguish DP FP regs */
-#define FP_DOUBLE (FP_REG_OFFSET + 16)
+#define X86_FP_DOUBLE (X86_FP_REG_OFFSET + 16)
 /* Offset to distingish the extra regs */
-#define EXTRA_REG_OFFSET (FP_DOUBLE + 16)
+#define X86_EXTRA_REG_OFFSET (X86_FP_DOUBLE + 16)
 /* Reg types */
-#define REGTYPE(x) (x & (FP_REG_OFFSET | FP_DOUBLE))
-#define FPREG(x) ((x & FP_REG_OFFSET) == FP_REG_OFFSET)
-#define EXTRAREG(x) ((x & EXTRA_REG_OFFSET) == EXTRA_REG_OFFSET)
-#define LOWREG(x) ((x & 0x1f) == x)
-#define DOUBLEREG(x) ((x & FP_DOUBLE) == FP_DOUBLE)
-#define SINGLEREG(x) (FPREG(x) && !DOUBLEREG(x))
+#define X86_REGTYPE(x) (x & (X86_FP_REG_OFFSET | X86_FP_DOUBLE))
+#define X86_FPREG(x) ((x & X86_FP_REG_OFFSET) == X86_FP_REG_OFFSET)
+#define X86_EXTRAREG(x) ((x & X86_EXTRA_REG_OFFSET) == X86_EXTRA_REG_OFFSET)
+#define X86_DOUBLEREG(x) ((x & X86_FP_DOUBLE) == X86_FP_DOUBLE)
+#define X86_SINGLEREG(x) (X86_FPREG(x) && !X86_DOUBLEREG(x))
 
 /*
  * Note: the low register of a floating point pair is sufficient to
@@ -125,20 +124,16 @@
  * rework is done in this area.  Also, it is a good reminder in the calling
  * code that reg locations always describe doubles as a pair of singles.
  */
-#define S2D(x,y) ((x) | FP_DOUBLE)
+#define X86_S2D(x,y) ((x) | X86_FP_DOUBLE)
 /* Mask to strip off fp flags */
-#define FP_REG_MASK 0xF
-/* non-existent Dalvik register */
-#define vNone   (-1)
-/* non-existant physical register */
-#define rNone   (-1)
+#define X86_FP_REG_MASK 0xF
 
 /* RegisterLocation templates return values (rAX, rAX/rDX or XMM0) */
 //                               location,     wide, defined, const, fp, core, ref, highWord, home, lowReg, highReg,     sRegLow
-#define LOC_C_RETURN             {kLocPhysReg, 0,    0,       0,     0,  0,    0,   0,        1,    rAX,    INVALID_REG, INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_WIDE        {kLocPhysReg, 1,    0,       0,     0,  0,    0,   0,        1,    rAX,    rDX,         INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_FLOAT       {kLocPhysReg, 0,    0,       0,     1,  0,    0,   0,        1,    fr0,    INVALID_REG, INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_WIDE_DOUBLE {kLocPhysReg, 1,    0,       0,     1,  0,    0,   0,        1,    fr0,    fr1,         INVALID_SREG, INVALID_SREG}
+#define X86_LOC_C_RETURN             {kLocPhysReg, 0,    0,       0,     0,  0,    0,   0,        1,    rAX,    INVALID_REG, INVALID_SREG, INVALID_SREG}
+#define X86_LOC_C_RETURN_WIDE        {kLocPhysReg, 1,    0,       0,     0,  0,    0,   0,        1,    rAX,    rDX,         INVALID_SREG, INVALID_SREG}
+#define X86_LOC_C_RETURN_FLOAT       {kLocPhysReg, 0,    0,       0,     1,  0,    0,   0,        1,    fr0,    INVALID_REG, INVALID_SREG, INVALID_SREG}
+#define X86_LOC_C_RETURN_DOUBLE      {kLocPhysReg, 1,    0,       0,     1,  0,    0,   0,        1,    fr0,    fr1,         INVALID_SREG, INVALID_SREG}
 
 enum X86ResourceEncodingPos {
   kX86GPReg0   = 0,
@@ -155,7 +150,7 @@
  * Annotate special-purpose core registers:
  */
 
-enum NativeRegisterPool {
+enum X86NativeRegisterPool {
   r0     = 0,
   rAX    = r0,
   r1     = 1,
@@ -165,7 +160,7 @@
   r3     = 3,
   rBX    = r3,
   r4sp   = 4,
-  rSP    = r4sp,
+  rX86_SP    = r4sp,
   r4sib_no_index = r4sp,
   r5     = 5,
   rBP    = r5,
@@ -187,43 +182,44 @@
   r15    = 15,
   rRET   = 16,  // fake return address register for core spill mask
 #endif
-  fr0  =  0 + FP_REG_OFFSET,
-  fr1  =  1 + FP_REG_OFFSET,
-  fr2  =  2 + FP_REG_OFFSET,
-  fr3  =  3 + FP_REG_OFFSET,
-  fr4  =  4 + FP_REG_OFFSET,
-  fr5  =  5 + FP_REG_OFFSET,
-  fr6  =  6 + FP_REG_OFFSET,
-  fr7  =  7 + FP_REG_OFFSET,
-  fr8  =  8 + FP_REG_OFFSET,
-  fr9  =  9 + FP_REG_OFFSET,
-  fr10 = 10 + FP_REG_OFFSET,
-  fr11 = 11 + FP_REG_OFFSET,
-  fr12 = 12 + FP_REG_OFFSET,
-  fr13 = 13 + FP_REG_OFFSET,
-  fr14 = 14 + FP_REG_OFFSET,
-  fr15 = 15 + FP_REG_OFFSET,
+  fr0  =  0 + X86_FP_REG_OFFSET,
+  fr1  =  1 + X86_FP_REG_OFFSET,
+  fr2  =  2 + X86_FP_REG_OFFSET,
+  fr3  =  3 + X86_FP_REG_OFFSET,
+  fr4  =  4 + X86_FP_REG_OFFSET,
+  fr5  =  5 + X86_FP_REG_OFFSET,
+  fr6  =  6 + X86_FP_REG_OFFSET,
+  fr7  =  7 + X86_FP_REG_OFFSET,
+  fr8  =  8 + X86_FP_REG_OFFSET,
+  fr9  =  9 + X86_FP_REG_OFFSET,
+  fr10 = 10 + X86_FP_REG_OFFSET,
+  fr11 = 11 + X86_FP_REG_OFFSET,
+  fr12 = 12 + X86_FP_REG_OFFSET,
+  fr13 = 13 + X86_FP_REG_OFFSET,
+  fr14 = 14 + X86_FP_REG_OFFSET,
+  fr15 = 15 + X86_FP_REG_OFFSET,
 };
 
 /*
  * Target-independent aliases
  */
 
-#define rARG0 rAX
-#define rARG1 rCX
-#define rARG2 rDX
-#define rARG3 rBX
-#define rFARG0 rAX
-#define rFARG1 rCX
-#define rFARG2 rDX
-#define rFARG3 rBX
-#define rRET0 rAX
-#define rRET1 rDX
-#define rINVOKE_TGT rAX
-#define rLR INVALID_REG
-#define rSUSPEND INVALID_REG
-#define rSELF INVALID_REG
-#define rCOUNT rCX
+#define rX86_ARG0 rAX
+#define rX86_ARG1 rCX
+#define rX86_ARG2 rDX
+#define rX86_ARG3 rBX
+#define rX86_FARG0 rAX
+#define rX86_FARG1 rCX
+#define rX86_FARG2 rDX
+#define rX86_FARG3 rBX
+#define rX86_RET0 rAX
+#define rX86_RET1 rDX
+#define rX86_INVOKE_TGT rAX
+#define rX86_LR INVALID_REG
+#define rX86_SUSPEND INVALID_REG
+#define rX86_SELF INVALID_REG
+#define rX86_COUNT rCX
+#define rX86_PC INVALID_REG
 
 #define isPseudoOpcode(opCode) ((int)(opCode) < 0)
 
diff --git a/src/compiler/codegen/x86/X86RallocUtil.cc b/src/compiler/codegen/x86/X86RallocUtil.cc
index 58ad25a..caf4e08 100644
--- a/src/compiler/codegen/x86/X86RallocUtil.cc
+++ b/src/compiler/codegen/x86/X86RallocUtil.cc
@@ -65,7 +65,7 @@
     if (SRegToVReg(cUnit, info2->sReg) < SRegToVReg(cUnit, info1->sReg))
       info1 = info2;
     int vReg = SRegToVReg(cUnit, info1->sReg);
-    oatFlushRegWideImpl(cUnit, rSP, oatVRegOffset(cUnit, vReg),
+    oatFlushRegWideImpl(cUnit, rX86_SP, oatVRegOffset(cUnit, vReg),
                         info1->reg, info1->partner);
   }
 }
@@ -76,17 +76,17 @@
   if (info->live && info->dirty) {
     info->dirty = false;
     int vReg = SRegToVReg(cUnit, info->sReg);
-    oatFlushRegImpl(cUnit, rSP, oatVRegOffset(cUnit, vReg), reg, kWord);
+    oatFlushRegImpl(cUnit, rX86_SP, oatVRegOffset(cUnit, vReg), reg, kWord);
   }
 }
 
 /* Give access to the target-dependent FP register encoding to common code */
 bool oatIsFpReg(int reg) {
-  return FPREG(reg);
+  return X86_FPREG(reg);
 }
 
 uint32_t oatFpRegMask() {
-  return FP_REG_MASK;
+  return X86_FP_REG_MASK;
 }
 
 /* Clobber all regs that might be used by an external C call */
@@ -98,7 +98,7 @@
 }
 
 extern RegLocation oatGetReturnWideAlt(CompilationUnit* cUnit) {
-  RegLocation res = LOC_C_RETURN_WIDE;
+  RegLocation res = locCReturnWide();
   CHECK(res.lowReg == rAX);
   CHECK(res.highReg == rDX);
   oatClobber(cUnit, rAX);
@@ -111,7 +111,7 @@
 
 extern RegLocation oatGetReturnAlt(CompilationUnit* cUnit)
 {
-  RegLocation res = LOC_C_RETURN;
+  RegLocation res = locCReturn();
   res.lowReg = rDX;
   oatClobber(cUnit, rDX);
   oatMarkInUse(cUnit, rDX);
@@ -120,26 +120,26 @@
 
 extern RegisterInfo* oatGetRegInfo(CompilationUnit* cUnit, int reg)
 {
-  return FPREG(reg) ? &cUnit->regPool->FPRegs[reg & FP_REG_MASK]
+  return X86_FPREG(reg) ? &cUnit->regPool->FPRegs[reg & X86_FP_REG_MASK]
                     : &cUnit->regPool->coreRegs[reg];
 }
 
 /* To be used when explicitly managing register use */
 extern void oatLockCallTemps(CompilationUnit* cUnit)
 {
-  oatLockTemp(cUnit, rARG0);
-  oatLockTemp(cUnit, rARG1);
-  oatLockTemp(cUnit, rARG2);
-  oatLockTemp(cUnit, rARG3);
+  oatLockTemp(cUnit, rX86_ARG0);
+  oatLockTemp(cUnit, rX86_ARG1);
+  oatLockTemp(cUnit, rX86_ARG2);
+  oatLockTemp(cUnit, rX86_ARG3);
 }
 
 /* To be used when explicitly managing register use */
 extern void oatFreeCallTemps(CompilationUnit* cUnit)
 {
-  oatFreeTemp(cUnit, rARG0);
-  oatFreeTemp(cUnit, rARG1);
-  oatFreeTemp(cUnit, rARG2);
-  oatFreeTemp(cUnit, rARG3);
+  oatFreeTemp(cUnit, rX86_ARG0);
+  oatFreeTemp(cUnit, rX86_ARG1);
+  oatFreeTemp(cUnit, rX86_ARG2);
+  oatFreeTemp(cUnit, rX86_ARG3);
 }
 
 /* Convert an instruction to a NOP */