Quick Compiler: Shoot the Camel
Another step towards moving the Quick Compiler from the old
Dalvik coding style to Art's coding style. In this CL, Camel-case
locals, struct variables and arguments are converted to lower-case
with underscore names. Most of the name changes were formulistic,
but I also took this opportunity to change the old "printMe" into
the more traditional "verbose", and shorten cUnit to cu.
No logic changes.
Change-Id: I64b69b28a8357d5cc0abc1dc975954c91abd9b45
diff --git a/src/compiler/codegen/arm/target_arm.cc b/src/compiler/codegen/arm/target_arm.cc
index f5d13d3..9c12237 100644
--- a/src/compiler/codegen/arm/target_arm.cc
+++ b/src/compiler/codegen/arm/target_arm.cc
@@ -23,15 +23,15 @@
namespace art {
-static int coreRegs[] = {r0, r1, r2, r3, rARM_SUSPEND, r5, r6, r7, r8, rARM_SELF, r10,
+static int core_regs[] = {r0, r1, r2, r3, rARM_SUSPEND, r5, r6, r7, r8, rARM_SELF, r10,
r11, r12, rARM_SP, rARM_LR, rARM_PC};
static int ReservedRegs[] = {rARM_SUSPEND, rARM_SELF, rARM_SP, rARM_LR, rARM_PC};
static int FpRegs[] = {fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31};
-static int coreTemps[] = {r0, r1, r2, r3, r12};
-static int fpTemps[] = {fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
+static int core_temps[] = {r0, r1, r2, r3, r12};
+static int fp_temps[] = {fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15};
RegLocation LocCReturn()
@@ -85,9 +85,9 @@
// Create a double from a pair of singles.
-int S2d(int lowReg, int highReg)
+int S2d(int low_reg, int high_reg)
{
- return ARM_S2D(lowReg, highReg);
+ return ARM_S2D(low_reg, high_reg);
}
// Is reg a single or double?
@@ -123,20 +123,20 @@
/*
* Decode the register id.
*/
-uint64_t GetRegMaskCommon(CompilationUnit* cUnit, int reg)
+uint64_t GetRegMaskCommon(CompilationUnit* cu, int reg)
{
uint64_t seed;
int shift;
- int regId;
+ int reg_id;
- regId = reg & 0x1f;
+ reg_id = reg & 0x1f;
/* Each double register is equal to a pair of single-precision FP registers */
seed = ARM_DOUBLEREG(reg) ? 3 : 1;
/* FP register starts at bit position 16 */
shift = ARM_FPREG(reg) ? kArmFPReg0 : 0;
/* Expand the double register id into single offset */
- shift += regId;
+ shift += reg_id;
return (seed << shift);
}
@@ -145,79 +145,79 @@
return ENCODE_ARM_REG_PC;
}
-void SetupTargetResourceMasks(CompilationUnit* cUnit, LIR* lir)
+void SetupTargetResourceMasks(CompilationUnit* cu, LIR* lir)
{
- DCHECK_EQ(cUnit->instructionSet, kThumb2);
+ DCHECK_EQ(cu->instruction_set, kThumb2);
// Thumb2 specific setup
uint64_t flags = EncodingMap[lir->opcode].flags;
int opcode = lir->opcode;
if (flags & REG_DEF_SP) {
- lir->defMask |= ENCODE_ARM_REG_SP;
+ lir->def_mask |= ENCODE_ARM_REG_SP;
}
if (flags & REG_USE_SP) {
- lir->useMask |= ENCODE_ARM_REG_SP;
+ lir->use_mask |= ENCODE_ARM_REG_SP;
}
if (flags & REG_DEF_LIST0) {
- lir->defMask |= ENCODE_ARM_REG_LIST(lir->operands[0]);
+ lir->def_mask |= ENCODE_ARM_REG_LIST(lir->operands[0]);
}
if (flags & REG_DEF_LIST1) {
- lir->defMask |= ENCODE_ARM_REG_LIST(lir->operands[1]);
+ lir->def_mask |= ENCODE_ARM_REG_LIST(lir->operands[1]);
}
if (flags & REG_DEF_FPCS_LIST0) {
- lir->defMask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]);
+ lir->def_mask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]);
}
if (flags & REG_DEF_FPCS_LIST2) {
for (int i = 0; i < lir->operands[2]; i++) {
- SetupRegMask(cUnit, &lir->defMask, lir->operands[1] + i);
+ SetupRegMask(cu, &lir->def_mask, lir->operands[1] + i);
}
}
if (flags & REG_USE_PC) {
- lir->useMask |= ENCODE_ARM_REG_PC;
+ lir->use_mask |= ENCODE_ARM_REG_PC;
}
/* Conservatively treat the IT block */
if (flags & IS_IT) {
- lir->defMask = ENCODE_ALL;
+ lir->def_mask = ENCODE_ALL;
}
if (flags & REG_USE_LIST0) {
- lir->useMask |= ENCODE_ARM_REG_LIST(lir->operands[0]);
+ lir->use_mask |= ENCODE_ARM_REG_LIST(lir->operands[0]);
}
if (flags & REG_USE_LIST1) {
- lir->useMask |= ENCODE_ARM_REG_LIST(lir->operands[1]);
+ lir->use_mask |= ENCODE_ARM_REG_LIST(lir->operands[1]);
}
if (flags & REG_USE_FPCS_LIST0) {
- lir->useMask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]);
+ lir->use_mask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]);
}
if (flags & REG_USE_FPCS_LIST2) {
for (int i = 0; i < lir->operands[2]; i++) {
- SetupRegMask(cUnit, &lir->useMask, lir->operands[1] + i);
+ SetupRegMask(cu, &lir->use_mask, lir->operands[1] + i);
}
}
/* Fixup for kThumbPush/lr and kThumbPop/pc */
if (opcode == kThumbPush || opcode == kThumbPop) {
- uint64_t r8Mask = GetRegMaskCommon(cUnit, r8);
- if ((opcode == kThumbPush) && (lir->useMask & r8Mask)) {
- lir->useMask &= ~r8Mask;
- lir->useMask |= ENCODE_ARM_REG_LR;
- } else if ((opcode == kThumbPop) && (lir->defMask & r8Mask)) {
- lir->defMask &= ~r8Mask;
- lir->defMask |= ENCODE_ARM_REG_PC;
+ uint64_t r8Mask = GetRegMaskCommon(cu, r8);
+ if ((opcode == kThumbPush) && (lir->use_mask & r8Mask)) {
+ lir->use_mask &= ~r8Mask;
+ lir->use_mask |= ENCODE_ARM_REG_LR;
+ } else if ((opcode == kThumbPop) && (lir->def_mask & r8Mask)) {
+ lir->def_mask &= ~r8Mask;
+ lir->def_mask |= ENCODE_ARM_REG_PC;
}
}
if (flags & REG_DEF_LR) {
- lir->defMask |= ENCODE_ARM_REG_LR;
+ lir->def_mask |= ENCODE_ARM_REG_LR;
}
}
@@ -248,7 +248,7 @@
return res;
}
-static const char* coreRegNames[16] = {
+static const char* core_reg_names[16] = {
"r0",
"r1",
"r2",
@@ -268,7 +268,7 @@
};
-static const char* shiftNames[4] = {
+static const char* shift_names[4] = {
"lsl",
"lsr",
"asr",
@@ -282,17 +282,17 @@
buf[0] = 0;
for (i = 0; i < 16; i++, vector >>= 1) {
if (vector & 0x1) {
- int regId = i;
+ int reg_id = i;
if (opcode == kThumbPush && i == 8) {
- regId = r14lr;
+ reg_id = r14lr;
} else if (opcode == kThumbPop && i == 8) {
- regId = r15pc;
+ reg_id = r15pc;
}
if (printed) {
- sprintf(buf + strlen(buf), ", r%d", regId);
+ sprintf(buf + strlen(buf), ", r%d", reg_id);
} else {
printed = true;
- sprintf(buf, "r%d", regId);
+ sprintf(buf, "r%d", reg_id);
}
}
}
@@ -328,36 +328,36 @@
return bits >> (((value & 0xf80) >> 7) - 8);
}
-const char* ccNames[] = {"eq","ne","cs","cc","mi","pl","vs","vc",
+const char* cc_names[] = {"eq","ne","cs","cc","mi","pl","vs","vc",
"hi","ls","ge","lt","gt","le","al","nv"};
/*
* Interpret a format string and build a string no longer than size
* See format key in Assemble.c.
*/
-std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* baseAddr)
+std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr)
{
std::string buf;
int i;
- const char* fmtEnd = &fmt[strlen(fmt)];
+ const char* fmt_end = &fmt[strlen(fmt)];
char tbuf[256];
const char* name;
char nc;
- while (fmt < fmtEnd) {
+ while (fmt < fmt_end) {
int operand;
if (*fmt == '!') {
fmt++;
- DCHECK_LT(fmt, fmtEnd);
+ DCHECK_LT(fmt, fmt_end);
nc = *fmt++;
if (nc=='!') {
strcpy(tbuf, "!");
} else {
- DCHECK_LT(fmt, fmtEnd);
+ DCHECK_LT(fmt, fmt_end);
DCHECK_LT(static_cast<unsigned>(nc-'0'), 4U);
operand = lir->operands[nc-'0'];
switch (*fmt++) {
case 'H':
if (operand != 0) {
- sprintf(tbuf, ", %s %d",shiftNames[operand & 0x3], operand >> 2);
+ sprintf(tbuf, ", %s %d",shift_names[operand & 0x3], operand >> 2);
} else {
strcpy(tbuf,"");
}
@@ -418,8 +418,8 @@
break;
case 'C':
DCHECK_LT(operand, static_cast<int>(
- sizeof(coreRegNames)/sizeof(coreRegNames[0])));
- sprintf(tbuf,"%s",coreRegNames[operand]);
+ sizeof(core_reg_names)/sizeof(core_reg_names[0])));
+ sprintf(tbuf,"%s",core_reg_names[operand]);
break;
case 'E':
sprintf(tbuf,"%d", operand*4);
@@ -428,11 +428,11 @@
sprintf(tbuf,"%d", operand*2);
break;
case 'c':
- strcpy(tbuf, ccNames[operand]);
+ strcpy(tbuf, cc_names[operand]);
break;
case 't':
sprintf(tbuf,"0x%08x (L%p)",
- reinterpret_cast<uintptr_t>(baseAddr) + lir->offset + 4 +
+ reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4 +
(operand << 1),
lir->target);
break;
@@ -440,7 +440,7 @@
int offset_1 = lir->operands[0];
int offset_2 = NEXT_LIR(lir)->operands[0];
uintptr_t target =
- (((reinterpret_cast<uintptr_t>(baseAddr) + lir->offset + 4) &
+ (((reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4) &
~3) + (offset_1 << 21 >> 9) + (offset_2 << 1)) &
0xfffffffc;
sprintf(tbuf, "%p", reinterpret_cast<void *>(target));
@@ -473,7 +473,7 @@
return buf;
}
-void DumpResourceMask(LIR* armLIR, uint64_t mask, const char* prefix)
+void DumpResourceMask(LIR* arm_lir, uint64_t mask, const char* prefix)
{
char buf[256];
buf[0] = 0;
@@ -499,9 +499,9 @@
}
/* Memory bits */
- if (armLIR && (mask & ENCODE_DALVIK_REG)) {
- sprintf(buf + strlen(buf), "dr%d%s", armLIR->aliasInfo & 0xffff,
- (armLIR->aliasInfo & 0x80000000) ? "(+1)" : "");
+ if (arm_lir && (mask & ENCODE_DALVIK_REG)) {
+ sprintf(buf + strlen(buf), "dr%d%s", arm_lir->alias_info & 0xffff,
+ (arm_lir->alias_info & 0x80000000) ? "(+1)" : "");
}
if (mask & ENCODE_LITERAL) {
strcat(buf, "lit ");
@@ -550,105 +550,105 @@
* Alloc a pair of core registers, or a double. Low reg in low byte,
* high reg in next byte.
*/
-int AllocTypedTempPair(CompilationUnit* cUnit, bool fpHint, int regClass)
+int AllocTypedTempPair(CompilationUnit* cu, bool fp_hint, int reg_class)
{
- int highReg;
- int lowReg;
+ int high_reg;
+ int low_reg;
int res = 0;
- if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg)) {
- lowReg = AllocTempDouble(cUnit);
- highReg = lowReg + 1;
+ if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
+ low_reg = AllocTempDouble(cu);
+ high_reg = low_reg + 1;
} else {
- lowReg = AllocTemp(cUnit);
- highReg = AllocTemp(cUnit);
+ low_reg = AllocTemp(cu);
+ high_reg = AllocTemp(cu);
}
- res = (lowReg & 0xff) | ((highReg & 0xff) << 8);
+ res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
return res;
}
-int AllocTypedTemp(CompilationUnit* cUnit, bool fpHint, int regClass)
+int AllocTypedTemp(CompilationUnit* cu, bool fp_hint, int reg_class)
{
- if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg))
- return AllocTempFloat(cUnit);
- return AllocTemp(cUnit);
+ if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg))
+ return AllocTempFloat(cu);
+ return AllocTemp(cu);
}
-void CompilerInitializeRegAlloc(CompilationUnit* cUnit)
+void CompilerInitializeRegAlloc(CompilationUnit* cu)
{
- int numRegs = sizeof(coreRegs)/sizeof(*coreRegs);
- int numReserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs);
- int numTemps = sizeof(coreTemps)/sizeof(*coreTemps);
- int numFPRegs = sizeof(FpRegs)/sizeof(*FpRegs);
- int numFPTemps = sizeof(fpTemps)/sizeof(*fpTemps);
+ int num_regs = sizeof(core_regs)/sizeof(*core_regs);
+ int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs);
+ int num_temps = sizeof(core_temps)/sizeof(*core_temps);
+ int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs);
+ int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps);
RegisterPool *pool =
- static_cast<RegisterPool*>(NewMem(cUnit, sizeof(*pool), true, kAllocRegAlloc));
- cUnit->regPool = pool;
- pool->numCoreRegs = numRegs;
- pool->coreRegs = reinterpret_cast<RegisterInfo*>
- (NewMem(cUnit, numRegs * sizeof(*cUnit->regPool->coreRegs), true, kAllocRegAlloc));
- pool->numFPRegs = numFPRegs;
+ static_cast<RegisterPool*>(NewMem(cu, sizeof(*pool), true, kAllocRegAlloc));
+ cu->reg_pool = pool;
+ pool->num_core_regs = num_regs;
+ pool->core_regs = reinterpret_cast<RegisterInfo*>
+ (NewMem(cu, num_regs * sizeof(*cu->reg_pool->core_regs), true, kAllocRegAlloc));
+ pool->num_fp_regs = num_fp_regs;
pool->FPRegs = static_cast<RegisterInfo*>
- (NewMem(cUnit, numFPRegs * sizeof(*cUnit->regPool->FPRegs), true, kAllocRegAlloc));
- CompilerInitPool(pool->coreRegs, coreRegs, pool->numCoreRegs);
- CompilerInitPool(pool->FPRegs, FpRegs, pool->numFPRegs);
+ (NewMem(cu, num_fp_regs * sizeof(*cu->reg_pool->FPRegs), true, kAllocRegAlloc));
+ CompilerInitPool(pool->core_regs, core_regs, pool->num_core_regs);
+ CompilerInitPool(pool->FPRegs, FpRegs, pool->num_fp_regs);
// Keep special registers from being allocated
- for (int i = 0; i < numReserved; i++) {
+ for (int i = 0; i < num_reserved; i++) {
if (NO_SUSPEND && (ReservedRegs[i] == rARM_SUSPEND)) {
//To measure cost of suspend check
continue;
}
- MarkInUse(cUnit, ReservedRegs[i]);
+ MarkInUse(cu, ReservedRegs[i]);
}
// Mark temp regs - all others not in use can be used for promotion
- for (int i = 0; i < numTemps; i++) {
- MarkTemp(cUnit, coreTemps[i]);
+ for (int i = 0; i < num_temps; i++) {
+ MarkTemp(cu, core_temps[i]);
}
- for (int i = 0; i < numFPTemps; i++) {
- MarkTemp(cUnit, fpTemps[i]);
+ for (int i = 0; i < num_fp_temps; i++) {
+ MarkTemp(cu, fp_temps[i]);
}
// Start allocation at r2 in an attempt to avoid clobbering return values
- pool->nextCoreReg = r2;
+ pool->next_core_reg = r2;
// Construct the alias map.
- cUnit->phiAliasMap = static_cast<int*>
- (NewMem(cUnit, cUnit->numSSARegs * sizeof(cUnit->phiAliasMap[0]), false, kAllocDFInfo));
- for (int i = 0; i < cUnit->numSSARegs; i++) {
- cUnit->phiAliasMap[i] = i;
+ cu->phi_alias_map = static_cast<int*>
+ (NewMem(cu, cu->num_ssa_regs * sizeof(cu->phi_alias_map[0]), false, kAllocDFInfo));
+ for (int i = 0; i < cu->num_ssa_regs; i++) {
+ cu->phi_alias_map[i] = i;
}
- for (MIR* phi = cUnit->phiList; phi; phi = phi->meta.phiNext) {
- int defReg = phi->ssaRep->defs[0];
- for (int i = 0; i < phi->ssaRep->numUses; i++) {
- for (int j = 0; j < cUnit->numSSARegs; j++) {
- if (cUnit->phiAliasMap[j] == phi->ssaRep->uses[i]) {
- cUnit->phiAliasMap[j] = defReg;
+ for (MIR* phi = cu->phi_list; phi; phi = phi->meta.phi_next) {
+ int def_reg = phi->ssa_rep->defs[0];
+ for (int i = 0; i < phi->ssa_rep->num_uses; i++) {
+ for (int j = 0; j < cu->num_ssa_regs; j++) {
+ if (cu->phi_alias_map[j] == phi->ssa_rep->uses[i]) {
+ cu->phi_alias_map[j] = def_reg;
}
}
}
}
}
-void FreeRegLocTemps(CompilationUnit* cUnit, RegLocation rlKeep,
- RegLocation rlFree)
+void FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep,
+ RegLocation rl_free)
{
- if ((rlFree.lowReg != rlKeep.lowReg) && (rlFree.lowReg != rlKeep.highReg) &&
- (rlFree.highReg != rlKeep.lowReg) && (rlFree.highReg != rlKeep.highReg)) {
+ if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) &&
+ (rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) {
// No overlap, free both
- FreeTemp(cUnit, rlFree.lowReg);
- FreeTemp(cUnit, rlFree.highReg);
+ FreeTemp(cu, rl_free.low_reg);
+ FreeTemp(cu, rl_free.high_reg);
}
}
/*
- * TUNING: is leaf? Can't just use "hasInvoke" to determine as some
+ * TUNING: is leaf? Can't just use "has_invoke" to determine as some
* instructions might call out to C/assembly helper functions. Until
* machinery is in place, always spill lr.
*/
-void AdjustSpillMask(CompilationUnit* cUnit)
+void AdjustSpillMask(CompilationUnit* cu)
{
- cUnit->coreSpillMask |= (1 << rARM_LR);
- cUnit->numCoreSpills++;
+ cu->core_spill_mask |= (1 << rARM_LR);
+ cu->num_core_spills++;
}
/*
@@ -657,52 +657,52 @@
* include any holes in the mask. Associate holes with
* Dalvik register INVALID_VREG (0xFFFFU).
*/
-void MarkPreservedSingle(CompilationUnit* cUnit, int vReg, int reg)
+void MarkPreservedSingle(CompilationUnit* cu, int v_reg, int reg)
{
DCHECK_GE(reg, ARM_FP_REG_MASK + ARM_FP_CALLEE_SAVE_BASE);
reg = (reg & ARM_FP_REG_MASK) - ARM_FP_CALLEE_SAVE_BASE;
- // Ensure fpVmapTable is large enough
- int tableSize = cUnit->fpVmapTable.size();
- for (int i = tableSize; i < (reg + 1); i++) {
- cUnit->fpVmapTable.push_back(INVALID_VREG);
+ // Ensure fp_vmap_table is large enough
+ int table_size = cu->fp_vmap_table.size();
+ for (int i = table_size; i < (reg + 1); i++) {
+ cu->fp_vmap_table.push_back(INVALID_VREG);
}
// Add the current mapping
- cUnit->fpVmapTable[reg] = vReg;
- // Size of fpVmapTable is high-water mark, use to set mask
- cUnit->numFPSpills = cUnit->fpVmapTable.size();
- cUnit->fpSpillMask = ((1 << cUnit->numFPSpills) - 1) << ARM_FP_CALLEE_SAVE_BASE;
+ cu->fp_vmap_table[reg] = v_reg;
+ // Size of fp_vmap_table is high-water mark, use to set mask
+ cu->num_fp_spills = cu->fp_vmap_table.size();
+ cu->fp_spill_mask = ((1 << cu->num_fp_spills) - 1) << ARM_FP_CALLEE_SAVE_BASE;
}
-void FlushRegWide(CompilationUnit* cUnit, int reg1, int reg2)
+void FlushRegWide(CompilationUnit* cu, int reg1, int reg2)
{
- RegisterInfo* info1 = GetRegInfo(cUnit, reg1);
- RegisterInfo* info2 = GetRegInfo(cUnit, reg2);
+ RegisterInfo* info1 = GetRegInfo(cu, reg1);
+ RegisterInfo* info2 = GetRegInfo(cu, reg2);
DCHECK(info1 && info2 && info1->pair && info2->pair &&
(info1->partner == info2->reg) &&
(info2->partner == info1->reg));
if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) {
- if (!(info1->isTemp && info2->isTemp)) {
- /* Should not happen. If it does, there's a problem in evalLoc */
+ if (!(info1->is_temp && info2->is_temp)) {
+ /* Should not happen. If it does, there's a problem in eval_loc */
LOG(FATAL) << "Long half-temp, half-promoted";
}
info1->dirty = false;
info2->dirty = false;
- if (SRegToVReg(cUnit, info2->sReg) <
- SRegToVReg(cUnit, info1->sReg))
+ if (SRegToVReg(cu, info2->s_reg) <
+ SRegToVReg(cu, info1->s_reg))
info1 = info2;
- int vReg = SRegToVReg(cUnit, info1->sReg);
- StoreBaseDispWide(cUnit, rARM_SP, VRegOffset(cUnit, vReg), info1->reg, info1->partner);
+ int v_reg = SRegToVReg(cu, info1->s_reg);
+ StoreBaseDispWide(cu, rARM_SP, VRegOffset(cu, v_reg), info1->reg, info1->partner);
}
}
-void FlushReg(CompilationUnit* cUnit, int reg)
+void FlushReg(CompilationUnit* cu, int reg)
{
- RegisterInfo* info = GetRegInfo(cUnit, reg);
+ RegisterInfo* info = GetRegInfo(cu, reg);
if (info->live && info->dirty) {
info->dirty = false;
- int vReg = SRegToVReg(cUnit, info->sReg);
- StoreBaseDisp(cUnit, rARM_SP, VRegOffset(cUnit, vReg), reg, kWord);
+ int v_reg = SRegToVReg(cu, info->s_reg);
+ StoreBaseDisp(cu, rARM_SP, VRegOffset(cu, v_reg), reg, kWord);
}
}
@@ -712,81 +712,81 @@
}
/* Clobber all regs that might be used by an external C call */
-void ClobberCalleeSave(CompilationUnit *cUnit)
+void ClobberCalleeSave(CompilationUnit *cu)
{
- Clobber(cUnit, r0);
- Clobber(cUnit, r1);
- Clobber(cUnit, r2);
- Clobber(cUnit, r3);
- Clobber(cUnit, r12);
- Clobber(cUnit, r14lr);
- Clobber(cUnit, fr0);
- Clobber(cUnit, fr1);
- Clobber(cUnit, fr2);
- Clobber(cUnit, fr3);
- Clobber(cUnit, fr4);
- Clobber(cUnit, fr5);
- Clobber(cUnit, fr6);
- Clobber(cUnit, fr7);
- Clobber(cUnit, fr8);
- Clobber(cUnit, fr9);
- Clobber(cUnit, fr10);
- Clobber(cUnit, fr11);
- Clobber(cUnit, fr12);
- Clobber(cUnit, fr13);
- Clobber(cUnit, fr14);
- Clobber(cUnit, fr15);
+ Clobber(cu, r0);
+ Clobber(cu, r1);
+ Clobber(cu, r2);
+ Clobber(cu, r3);
+ Clobber(cu, r12);
+ Clobber(cu, r14lr);
+ Clobber(cu, fr0);
+ Clobber(cu, fr1);
+ Clobber(cu, fr2);
+ Clobber(cu, fr3);
+ Clobber(cu, fr4);
+ Clobber(cu, fr5);
+ Clobber(cu, fr6);
+ Clobber(cu, fr7);
+ Clobber(cu, fr8);
+ Clobber(cu, fr9);
+ Clobber(cu, fr10);
+ Clobber(cu, fr11);
+ Clobber(cu, fr12);
+ Clobber(cu, fr13);
+ Clobber(cu, fr14);
+ Clobber(cu, fr15);
}
-RegLocation GetReturnWideAlt(CompilationUnit* cUnit)
+RegLocation GetReturnWideAlt(CompilationUnit* cu)
{
RegLocation res = LocCReturnWide();
- res.lowReg = r2;
- res.highReg = r3;
- Clobber(cUnit, r2);
- Clobber(cUnit, r3);
- MarkInUse(cUnit, r2);
- MarkInUse(cUnit, r3);
- MarkPair(cUnit, res.lowReg, res.highReg);
+ res.low_reg = r2;
+ res.high_reg = r3;
+ Clobber(cu, r2);
+ Clobber(cu, r3);
+ MarkInUse(cu, r2);
+ MarkInUse(cu, r3);
+ MarkPair(cu, res.low_reg, res.high_reg);
return res;
}
-RegLocation GetReturnAlt(CompilationUnit* cUnit)
+RegLocation GetReturnAlt(CompilationUnit* cu)
{
RegLocation res = LocCReturn();
- res.lowReg = r1;
- Clobber(cUnit, r1);
- MarkInUse(cUnit, r1);
+ res.low_reg = r1;
+ Clobber(cu, r1);
+ MarkInUse(cu, r1);
return res;
}
-RegisterInfo* GetRegInfo(CompilationUnit* cUnit, int reg)
+RegisterInfo* GetRegInfo(CompilationUnit* cu, int reg)
{
- return ARM_FPREG(reg) ? &cUnit->regPool->FPRegs[reg & ARM_FP_REG_MASK]
- : &cUnit->regPool->coreRegs[reg];
+ return ARM_FPREG(reg) ? &cu->reg_pool->FPRegs[reg & ARM_FP_REG_MASK]
+ : &cu->reg_pool->core_regs[reg];
}
/* To be used when explicitly managing register use */
-void LockCallTemps(CompilationUnit* cUnit)
+void LockCallTemps(CompilationUnit* cu)
{
- LockTemp(cUnit, r0);
- LockTemp(cUnit, r1);
- LockTemp(cUnit, r2);
- LockTemp(cUnit, r3);
+ LockTemp(cu, r0);
+ LockTemp(cu, r1);
+ LockTemp(cu, r2);
+ LockTemp(cu, r3);
}
/* To be used when explicitly managing register use */
-void FreeCallTemps(CompilationUnit* cUnit)
+void FreeCallTemps(CompilationUnit* cu)
{
- FreeTemp(cUnit, r0);
- FreeTemp(cUnit, r1);
- FreeTemp(cUnit, r2);
- FreeTemp(cUnit, r3);
+ FreeTemp(cu, r0);
+ FreeTemp(cu, r1);
+ FreeTemp(cu, r2);
+ FreeTemp(cu, r3);
}
-int LoadHelper(CompilationUnit* cUnit, int offset)
+int LoadHelper(CompilationUnit* cu, int offset)
{
- LoadWordDisp(cUnit, rARM_SELF, offset, rARM_LR);
+ LoadWordDisp(cu, rARM_SELF, offset, rARM_LR);
return rARM_LR;
}