Quick Compiler: Shoot the Camel
Another step towards moving the Quick Compiler from the old
Dalvik coding style to Art's coding style. In this CL, Camel-case
locals, struct variables and arguments are converted to lower-case
with underscore names. Most of the name changes were formulistic,
but I also took this opportunity to change the old "printMe" into
the more traditional "verbose", and shorten cUnit to cu.
No logic changes.
Change-Id: I64b69b28a8357d5cc0abc1dc975954c91abd9b45
diff --git a/src/compiler/codegen/mips/assemble_mips.cc b/src/compiler/codegen/mips/assemble_mips.cc
index 9bee7af..b80784f 100644
--- a/src/compiler/codegen/mips/assemble_mips.cc
+++ b/src/compiler/codegen/mips/assemble_mips.cc
@@ -458,12 +458,12 @@
* NOTE: An out-of-range bal isn't supported because it should
* never happen with the current PIC model.
*/
-static void ConvertShortToLongBranch(CompilationUnit* cUnit, LIR* lir)
+static void ConvertShortToLongBranch(CompilationUnit* cu, LIR* lir)
{
// For conditional branches we'll need to reverse the sense
bool unconditional = false;
int opcode = lir->opcode;
- int dalvikOffset = lir->dalvikOffset;
+ int dalvik_offset = lir->dalvik_offset;
switch (opcode) {
case kMipsBal:
LOG(FATAL) << "long branch and link unsupported";
@@ -481,31 +481,31 @@
default:
LOG(FATAL) << "Unexpected branch kind " << opcode;
}
- LIR* hopTarget = NULL;
+ LIR* hop_target = NULL;
if (!unconditional) {
- hopTarget = RawLIR(cUnit, dalvikOffset, kPseudoTargetLabel);
- LIR* hopBranch = RawLIR(cUnit, dalvikOffset, opcode, lir->operands[0],
- lir->operands[1], 0, 0, 0, hopTarget);
- InsertLIRBefore(lir, hopBranch);
+ hop_target = RawLIR(cu, dalvik_offset, kPseudoTargetLabel);
+ LIR* hop_branch = RawLIR(cu, dalvik_offset, opcode, lir->operands[0],
+ lir->operands[1], 0, 0, 0, hop_target);
+ InsertLIRBefore(lir, hop_branch);
}
- LIR* currPC = RawLIR(cUnit, dalvikOffset, kMipsCurrPC);
- InsertLIRBefore(lir, currPC);
- LIR* anchor = RawLIR(cUnit, dalvikOffset, kPseudoTargetLabel);
- LIR* deltaHi = RawLIR(cUnit, dalvikOffset, kMipsDeltaHi, r_AT, 0,
+ LIR* curr_pc = RawLIR(cu, dalvik_offset, kMipsCurrPC);
+ InsertLIRBefore(lir, curr_pc);
+ LIR* anchor = RawLIR(cu, dalvik_offset, kPseudoTargetLabel);
+ LIR* delta_hi = RawLIR(cu, dalvik_offset, kMipsDeltaHi, r_AT, 0,
reinterpret_cast<uintptr_t>(anchor), 0, 0, lir->target);
- InsertLIRBefore(lir, deltaHi);
+ InsertLIRBefore(lir, delta_hi);
InsertLIRBefore(lir, anchor);
- LIR* deltaLo = RawLIR(cUnit, dalvikOffset, kMipsDeltaLo, r_AT, 0,
+ LIR* delta_lo = RawLIR(cu, dalvik_offset, kMipsDeltaLo, r_AT, 0,
reinterpret_cast<uintptr_t>(anchor), 0, 0, lir->target);
- InsertLIRBefore(lir, deltaLo);
- LIR* addu = RawLIR(cUnit, dalvikOffset, kMipsAddu, r_AT, r_AT, r_RA);
+ InsertLIRBefore(lir, delta_lo);
+ LIR* addu = RawLIR(cu, dalvik_offset, kMipsAddu, r_AT, r_AT, r_RA);
InsertLIRBefore(lir, addu);
- LIR* jr = RawLIR(cUnit, dalvikOffset, kMipsJr, r_AT);
+ LIR* jr = RawLIR(cu, dalvik_offset, kMipsJr, r_AT);
InsertLIRBefore(lir, jr);
if (!unconditional) {
- InsertLIRBefore(lir, hopTarget);
+ InsertLIRBefore(lir, hop_target);
}
- lir->flags.isNop = true;
+ lir->flags.is_nop = true;
}
/*
@@ -514,19 +514,19 @@
* instruction. In those cases we will try to substitute a new code
* sequence or request that the trace be shortened and retried.
*/
-AssemblerStatus AssembleInstructions(CompilationUnit *cUnit,
- uintptr_t startAddr)
+AssemblerStatus AssembleInstructions(CompilationUnit *cu,
+ uintptr_t start_addr)
{
LIR *lir;
AssemblerStatus res = kSuccess; // Assume success
- for (lir = cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {
+ for (lir = cu->first_lir_insn; lir; lir = NEXT_LIR(lir)) {
if (lir->opcode < 0) {
continue;
}
- if (lir->flags.isNop) {
+ if (lir->flags.is_nop) {
continue;
}
@@ -543,101 +543,101 @@
* then it is a Switch/Data table.
*/
int offset1 = (reinterpret_cast<LIR*>(lir->operands[2]))->offset;
- SwitchTable *tabRec = reinterpret_cast<SwitchTable*>(lir->operands[3]);
- int offset2 = tabRec ? tabRec->offset : lir->target->offset;
+ SwitchTable *tab_rec = reinterpret_cast<SwitchTable*>(lir->operands[3]);
+ int offset2 = tab_rec ? tab_rec->offset : lir->target->offset;
int delta = offset2 - offset1;
if ((delta & 0xffff) == delta && ((delta & 0x8000) == 0)) {
// Fits
lir->operands[1] = delta;
} else {
// Doesn't fit - must expand to kMipsDelta[Hi|Lo] pair
- LIR *newDeltaHi =
- RawLIR(cUnit, lir->dalvikOffset, kMipsDeltaHi,
+ LIR *new_delta_hi =
+ RawLIR(cu, lir->dalvik_offset, kMipsDeltaHi,
lir->operands[0], 0, lir->operands[2],
lir->operands[3], 0, lir->target);
- InsertLIRBefore(lir, newDeltaHi);
- LIR *newDeltaLo =
- RawLIR(cUnit, lir->dalvikOffset, kMipsDeltaLo,
+ InsertLIRBefore(lir, new_delta_hi);
+ LIR *new_delta_lo =
+ RawLIR(cu, lir->dalvik_offset, kMipsDeltaLo,
lir->operands[0], 0, lir->operands[2],
lir->operands[3], 0, lir->target);
- InsertLIRBefore(lir, newDeltaLo);
- LIR *newAddu =
- RawLIR(cUnit, lir->dalvikOffset, kMipsAddu,
+ InsertLIRBefore(lir, new_delta_lo);
+ LIR *new_addu =
+ RawLIR(cu, lir->dalvik_offset, kMipsAddu,
lir->operands[0], lir->operands[0], r_RA);
- InsertLIRBefore(lir, newAddu);
- lir->flags.isNop = true;
+ InsertLIRBefore(lir, new_addu);
+ lir->flags.is_nop = true;
res = kRetryAll;
}
} else if (lir->opcode == kMipsDeltaLo) {
int offset1 = (reinterpret_cast<LIR*>(lir->operands[2]))->offset;
- SwitchTable *tabRec = reinterpret_cast<SwitchTable*>(lir->operands[3]);
- int offset2 = tabRec ? tabRec->offset : lir->target->offset;
+ SwitchTable *tab_rec = reinterpret_cast<SwitchTable*>(lir->operands[3]);
+ int offset2 = tab_rec ? tab_rec->offset : lir->target->offset;
int delta = offset2 - offset1;
lir->operands[1] = delta & 0xffff;
} else if (lir->opcode == kMipsDeltaHi) {
int offset1 = (reinterpret_cast<LIR*>(lir->operands[2]))->offset;
- SwitchTable *tabRec = reinterpret_cast<SwitchTable*>(lir->operands[3]);
- int offset2 = tabRec ? tabRec->offset : lir->target->offset;
+ SwitchTable *tab_rec = reinterpret_cast<SwitchTable*>(lir->operands[3]);
+ int offset2 = tab_rec ? tab_rec->offset : lir->target->offset;
int delta = offset2 - offset1;
lir->operands[1] = (delta >> 16) & 0xffff;
} else if (lir->opcode == kMipsB || lir->opcode == kMipsBal) {
- LIR *targetLIR = lir->target;
+ LIR *target_lir = lir->target;
uintptr_t pc = lir->offset + 4;
- uintptr_t target = targetLIR->offset;
+ uintptr_t target = target_lir->offset;
int delta = target - pc;
if (delta & 0x3) {
LOG(FATAL) << "PC-rel offset not multiple of 4: " << delta;
}
if (delta > 131068 || delta < -131069) {
res = kRetryAll;
- ConvertShortToLongBranch(cUnit, lir);
+ ConvertShortToLongBranch(cu, lir);
} else {
lir->operands[0] = delta >> 2;
}
} else if (lir->opcode >= kMipsBeqz && lir->opcode <= kMipsBnez) {
- LIR *targetLIR = lir->target;
+ LIR *target_lir = lir->target;
uintptr_t pc = lir->offset + 4;
- uintptr_t target = targetLIR->offset;
+ uintptr_t target = target_lir->offset;
int delta = target - pc;
if (delta & 0x3) {
LOG(FATAL) << "PC-rel offset not multiple of 4: " << delta;
}
if (delta > 131068 || delta < -131069) {
res = kRetryAll;
- ConvertShortToLongBranch(cUnit, lir);
+ ConvertShortToLongBranch(cu, lir);
} else {
lir->operands[1] = delta >> 2;
}
} else if (lir->opcode == kMipsBeq || lir->opcode == kMipsBne) {
- LIR *targetLIR = lir->target;
+ LIR *target_lir = lir->target;
uintptr_t pc = lir->offset + 4;
- uintptr_t target = targetLIR->offset;
+ uintptr_t target = target_lir->offset;
int delta = target - pc;
if (delta & 0x3) {
LOG(FATAL) << "PC-rel offset not multiple of 4: " << delta;
}
if (delta > 131068 || delta < -131069) {
res = kRetryAll;
- ConvertShortToLongBranch(cUnit, lir);
+ ConvertShortToLongBranch(cu, lir);
} else {
lir->operands[2] = delta >> 2;
}
} else if (lir->opcode == kMipsJal) {
- uintptr_t curPC = (startAddr + lir->offset + 4) & ~3;
+ uintptr_t cur_pc = (start_addr + lir->offset + 4) & ~3;
uintptr_t target = lir->operands[0];
/* ensure PC-region branch can be used */
- DCHECK_EQ((curPC & 0xF0000000), (target & 0xF0000000));
+ DCHECK_EQ((cur_pc & 0xF0000000), (target & 0xF0000000));
if (target & 0x3) {
LOG(FATAL) << "Jump target not multiple of 4: " << target;
}
lir->operands[0] = target >> 2;
} else if (lir->opcode == kMipsLahi) { /* ld address hi (via lui) */
- LIR *targetLIR = lir->target;
- uintptr_t target = startAddr + targetLIR->offset;
+ LIR *target_lir = lir->target;
+ uintptr_t target = start_addr + target_lir->offset;
lir->operands[1] = target >> 16;
} else if (lir->opcode == kMipsLalo) { /* ld address lo (via ori) */
- LIR *targetLIR = lir->target;
- uintptr_t target = startAddr + targetLIR->offset;
+ LIR *target_lir = lir->target;
+ uintptr_t target = start_addr + target_lir->offset;
lir->operands[2] = lir->operands[2] + target;
}
}
@@ -657,54 +657,54 @@
uint32_t operand;
uint32_t value;
operand = lir->operands[i];
- switch (encoder->fieldLoc[i].kind) {
+ switch (encoder->field_loc[i].kind) {
case kFmtUnused:
break;
case kFmtBitBlt:
- if (encoder->fieldLoc[i].start == 0 && encoder->fieldLoc[i].end == 31) {
+ if (encoder->field_loc[i].start == 0 && encoder->field_loc[i].end == 31) {
value = operand;
} else {
- value = (operand << encoder->fieldLoc[i].start) &
- ((1 << (encoder->fieldLoc[i].end + 1)) - 1);
+ value = (operand << encoder->field_loc[i].start) &
+ ((1 << (encoder->field_loc[i].end + 1)) - 1);
}
bits |= value;
break;
case kFmtBlt5_2:
value = (operand & 0x1f);
- bits |= (value << encoder->fieldLoc[i].start);
- bits |= (value << encoder->fieldLoc[i].end);
+ bits |= (value << encoder->field_loc[i].start);
+ bits |= (value << encoder->field_loc[i].end);
break;
case kFmtDfp: {
DCHECK(MIPS_DOUBLEREG(operand));
DCHECK_EQ((operand & 0x1), 0U);
- value = ((operand & MIPS_FP_REG_MASK) << encoder->fieldLoc[i].start) &
- ((1 << (encoder->fieldLoc[i].end + 1)) - 1);
+ value = ((operand & MIPS_FP_REG_MASK) << encoder->field_loc[i].start) &
+ ((1 << (encoder->field_loc[i].end + 1)) - 1);
bits |= value;
break;
}
case kFmtSfp:
DCHECK(MIPS_SINGLEREG(operand));
- value = ((operand & MIPS_FP_REG_MASK) << encoder->fieldLoc[i].start) &
- ((1 << (encoder->fieldLoc[i].end + 1)) - 1);
+ value = ((operand & MIPS_FP_REG_MASK) << encoder->field_loc[i].start) &
+ ((1 << (encoder->field_loc[i].end + 1)) - 1);
bits |= value;
break;
default:
- LOG(FATAL) << "Bad encoder format: " << encoder->fieldLoc[i].kind;
+ LOG(FATAL) << "Bad encoder format: " << encoder->field_loc[i].kind;
}
}
// We only support little-endian MIPS.
- cUnit->codeBuffer.push_back(bits & 0xff);
- cUnit->codeBuffer.push_back((bits >> 8) & 0xff);
- cUnit->codeBuffer.push_back((bits >> 16) & 0xff);
- cUnit->codeBuffer.push_back((bits >> 24) & 0xff);
+ cu->code_buffer.push_back(bits & 0xff);
+ cu->code_buffer.push_back((bits >> 8) & 0xff);
+ cu->code_buffer.push_back((bits >> 16) & 0xff);
+ cu->code_buffer.push_back((bits >> 24) & 0xff);
// TUNING: replace with proper delay slot handling
if (encoder->size == 8) {
const MipsEncodingMap *encoder = &EncodingMap[kMipsNop];
uint32_t bits = encoder->skeleton;
- cUnit->codeBuffer.push_back(bits & 0xff);
- cUnit->codeBuffer.push_back((bits >> 8) & 0xff);
- cUnit->codeBuffer.push_back((bits >> 16) & 0xff);
- cUnit->codeBuffer.push_back((bits >> 24) & 0xff);
+ cu->code_buffer.push_back(bits & 0xff);
+ cu->code_buffer.push_back((bits >> 8) & 0xff);
+ cu->code_buffer.push_back((bits >> 16) & 0xff);
+ cu->code_buffer.push_back((bits >> 24) & 0xff);
}
}
return res;
@@ -718,23 +718,23 @@
* Target-dependent offset assignment.
* independent.
*/
-int AssignInsnOffsets(CompilationUnit* cUnit)
+int AssignInsnOffsets(CompilationUnit* cu)
{
- LIR* mipsLIR;
+ LIR* mips_lir;
int offset = 0;
- for (mipsLIR = cUnit->firstLIRInsn; mipsLIR; mipsLIR = NEXT_LIR(mipsLIR)) {
- mipsLIR->offset = offset;
- if (mipsLIR->opcode >= 0) {
- if (!mipsLIR->flags.isNop) {
- offset += mipsLIR->flags.size;
+ for (mips_lir = cu->first_lir_insn; mips_lir; mips_lir = NEXT_LIR(mips_lir)) {
+ mips_lir->offset = offset;
+ if (mips_lir->opcode >= 0) {
+ if (!mips_lir->flags.is_nop) {
+ offset += mips_lir->flags.size;
}
- } else if (mipsLIR->opcode == kPseudoPseudoAlign4) {
+ } else if (mips_lir->opcode == kPseudoPseudoAlign4) {
if (offset & 0x2) {
offset += 2;
- mipsLIR->operands[0] = 1;
+ mips_lir->operands[0] = 1;
} else {
- mipsLIR->operands[0] = 0;
+ mips_lir->operands[0] = 0;
}
}
/* Pseudo opcodes don't consume space */
diff --git a/src/compiler/codegen/mips/call_mips.cc b/src/compiler/codegen/mips/call_mips.cc
index 33a7aed..b25b7e6 100644
--- a/src/compiler/codegen/mips/call_mips.cc
+++ b/src/compiler/codegen/mips/call_mips.cc
@@ -23,8 +23,8 @@
namespace art {
-void GenSpecialCase(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
- SpecialCaseHandler specialCase)
+void GenSpecialCase(CompilationUnit* cu, BasicBlock* bb, MIR* mir,
+ SpecialCaseHandler special_case)
{
// TODO
}
@@ -42,176 +42,176 @@
*
* The test loop will look something like:
*
- * ori rEnd, r_ZERO, #tableSize ; size in bytes
+ * ori rEnd, r_ZERO, #table_size ; size in bytes
* jal BaseLabel ; stores "return address" (BaseLabel) in r_RA
* nop ; opportunistically fill
* BaseLabel:
* addiu rBase, r_RA, <table> - <BaseLabel> ; table relative to BaseLabel
addu rEnd, rEnd, rBase ; end of table
- * lw rVal, [rSP, vRegOff] ; Test Value
+ * lw r_val, [rSP, v_reg_off] ; Test Value
* loop:
* beq rBase, rEnd, done
- * lw rKey, 0(rBase)
+ * lw r_key, 0(rBase)
* addu rBase, 8
- * bne rVal, rKey, loop
- * lw rDisp, -4(rBase)
- * addu r_RA, rDisp
+ * bne r_val, r_key, loop
+ * lw r_disp, -4(rBase)
+ * addu r_RA, r_disp
* jr r_RA
* done:
*
*/
-void GenSparseSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
- RegLocation rlSrc)
+void GenSparseSwitch(CompilationUnit* cu, uint32_t table_offset,
+ RegLocation rl_src)
{
- const uint16_t* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
- if (cUnit->printMe) {
+ const uint16_t* table = cu->insns + cu->current_dalvik_offset + table_offset;
+ if (cu->verbose) {
DumpSparseSwitchTable(table);
}
// Add the table to the list - we'll process it later
- SwitchTable *tabRec =
- static_cast<SwitchTable*>(NewMem(cUnit, sizeof(SwitchTable), true, kAllocData));
- tabRec->table = table;
- tabRec->vaddr = cUnit->currentDalvikOffset;
+ SwitchTable *tab_rec =
+ static_cast<SwitchTable*>(NewMem(cu, sizeof(SwitchTable), true, kAllocData));
+ tab_rec->table = table;
+ tab_rec->vaddr = cu->current_dalvik_offset;
int elements = table[1];
- tabRec->targets =
- static_cast<LIR**>(NewMem(cUnit, elements * sizeof(LIR*), true, kAllocLIR));
- InsertGrowableList(cUnit, &cUnit->switchTables, reinterpret_cast<uintptr_t>(tabRec));
+ tab_rec->targets =
+ static_cast<LIR**>(NewMem(cu, elements * sizeof(LIR*), true, kAllocLIR));
+ InsertGrowableList(cu, &cu->switch_tables, reinterpret_cast<uintptr_t>(tab_rec));
// The table is composed of 8-byte key/disp pairs
- int byteSize = elements * 8;
+ int byte_size = elements * 8;
- int sizeHi = byteSize >> 16;
- int sizeLo = byteSize & 0xffff;
+ int size_hi = byte_size >> 16;
+ int size_lo = byte_size & 0xffff;
- int rEnd = AllocTemp(cUnit);
- if (sizeHi) {
- NewLIR2(cUnit, kMipsLui, rEnd, sizeHi);
+ int rEnd = AllocTemp(cu);
+ if (size_hi) {
+ NewLIR2(cu, kMipsLui, rEnd, size_hi);
}
// Must prevent code motion for the curr pc pair
- GenBarrier(cUnit); // Scheduling barrier
- NewLIR0(cUnit, kMipsCurrPC); // Really a jal to .+8
+ GenBarrier(cu); // Scheduling barrier
+ NewLIR0(cu, kMipsCurrPC); // Really a jal to .+8
// Now, fill the branch delay slot
- if (sizeHi) {
- NewLIR3(cUnit, kMipsOri, rEnd, rEnd, sizeLo);
+ if (size_hi) {
+ NewLIR3(cu, kMipsOri, rEnd, rEnd, size_lo);
} else {
- NewLIR3(cUnit, kMipsOri, rEnd, r_ZERO, sizeLo);
+ NewLIR3(cu, kMipsOri, rEnd, r_ZERO, size_lo);
}
- GenBarrier(cUnit); // Scheduling barrier
+ GenBarrier(cu); // Scheduling barrier
// Construct BaseLabel and set up table base register
- LIR* baseLabel = NewLIR0(cUnit, kPseudoTargetLabel);
+ LIR* base_label = NewLIR0(cu, kPseudoTargetLabel);
// Remember base label so offsets can be computed later
- tabRec->anchor = baseLabel;
- int rBase = AllocTemp(cUnit);
- NewLIR4(cUnit, kMipsDelta, rBase, 0, reinterpret_cast<uintptr_t>(baseLabel),
- reinterpret_cast<uintptr_t>(tabRec));
- OpRegRegReg(cUnit, kOpAdd, rEnd, rEnd, rBase);
+ tab_rec->anchor = base_label;
+ int rBase = AllocTemp(cu);
+ NewLIR4(cu, kMipsDelta, rBase, 0, reinterpret_cast<uintptr_t>(base_label),
+ reinterpret_cast<uintptr_t>(tab_rec));
+ OpRegRegReg(cu, kOpAdd, rEnd, rEnd, rBase);
// Grab switch test value
- rlSrc = LoadValue(cUnit, rlSrc, kCoreReg);
+ rl_src = LoadValue(cu, rl_src, kCoreReg);
// Test loop
- int rKey = AllocTemp(cUnit);
- LIR* loopLabel = NewLIR0(cUnit, kPseudoTargetLabel);
- LIR* exitBranch = OpCmpBranch(cUnit , kCondEq, rBase, rEnd, NULL);
- LoadWordDisp(cUnit, rBase, 0, rKey);
- OpRegImm(cUnit, kOpAdd, rBase, 8);
- OpCmpBranch(cUnit, kCondNe, rlSrc.lowReg, rKey, loopLabel);
- int rDisp = AllocTemp(cUnit);
- LoadWordDisp(cUnit, rBase, -4, rDisp);
- OpRegRegReg(cUnit, kOpAdd, r_RA, r_RA, rDisp);
- OpReg(cUnit, kOpBx, r_RA);
+ int r_key = AllocTemp(cu);
+ LIR* loop_label = NewLIR0(cu, kPseudoTargetLabel);
+ LIR* exit_branch = OpCmpBranch(cu , kCondEq, rBase, rEnd, NULL);
+ LoadWordDisp(cu, rBase, 0, r_key);
+ OpRegImm(cu, kOpAdd, rBase, 8);
+ OpCmpBranch(cu, kCondNe, rl_src.low_reg, r_key, loop_label);
+ int r_disp = AllocTemp(cu);
+ LoadWordDisp(cu, rBase, -4, r_disp);
+ OpRegRegReg(cu, kOpAdd, r_RA, r_RA, r_disp);
+ OpReg(cu, kOpBx, r_RA);
// Loop exit
- LIR* exitLabel = NewLIR0(cUnit, kPseudoTargetLabel);
- exitBranch->target = exitLabel;
+ LIR* exit_label = NewLIR0(cu, kPseudoTargetLabel);
+ exit_branch->target = exit_label;
}
/*
* Code pattern will look something like:
*
- * lw rVal
+ * lw r_val
* jal BaseLabel ; stores "return address" (BaseLabel) in r_RA
* nop ; opportunistically fill
- * [subiu rVal, bias] ; Remove bias if lowVal != 0
+ * [subiu r_val, bias] ; Remove bias if low_val != 0
* bound check -> done
- * lw rDisp, [r_RA, rVal]
- * addu r_RA, rDisp
+ * lw r_disp, [r_RA, r_val]
+ * addu r_RA, r_disp
* jr r_RA
* done:
*/
-void GenPackedSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
- RegLocation rlSrc)
+void GenPackedSwitch(CompilationUnit* cu, uint32_t table_offset,
+ RegLocation rl_src)
{
- const uint16_t* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
- if (cUnit->printMe) {
+ const uint16_t* table = cu->insns + cu->current_dalvik_offset + table_offset;
+ if (cu->verbose) {
DumpPackedSwitchTable(table);
}
// Add the table to the list - we'll process it later
- SwitchTable *tabRec =
- static_cast<SwitchTable*>(NewMem(cUnit, sizeof(SwitchTable), true, kAllocData));
- tabRec->table = table;
- tabRec->vaddr = cUnit->currentDalvikOffset;
+ SwitchTable *tab_rec =
+ static_cast<SwitchTable*>(NewMem(cu, sizeof(SwitchTable), true, kAllocData));
+ tab_rec->table = table;
+ tab_rec->vaddr = cu->current_dalvik_offset;
int size = table[1];
- tabRec->targets = static_cast<LIR**>(NewMem(cUnit, size * sizeof(LIR*), true, kAllocLIR));
- InsertGrowableList(cUnit, &cUnit->switchTables, reinterpret_cast<uintptr_t>(tabRec));
+ tab_rec->targets = static_cast<LIR**>(NewMem(cu, size * sizeof(LIR*), true, kAllocLIR));
+ InsertGrowableList(cu, &cu->switch_tables, reinterpret_cast<uintptr_t>(tab_rec));
// Get the switch value
- rlSrc = LoadValue(cUnit, rlSrc, kCoreReg);
+ rl_src = LoadValue(cu, rl_src, kCoreReg);
// Prepare the bias. If too big, handle 1st stage here
- int lowKey = s4FromSwitchData(&table[2]);
- bool largeBias = false;
- int rKey;
- if (lowKey == 0) {
- rKey = rlSrc.lowReg;
- } else if ((lowKey & 0xffff) != lowKey) {
- rKey = AllocTemp(cUnit);
- LoadConstant(cUnit, rKey, lowKey);
- largeBias = true;
+ int low_key = s4FromSwitchData(&table[2]);
+ bool large_bias = false;
+ int r_key;
+ if (low_key == 0) {
+ r_key = rl_src.low_reg;
+ } else if ((low_key & 0xffff) != low_key) {
+ r_key = AllocTemp(cu);
+ LoadConstant(cu, r_key, low_key);
+ large_bias = true;
} else {
- rKey = AllocTemp(cUnit);
+ r_key = AllocTemp(cu);
}
// Must prevent code motion for the curr pc pair
- GenBarrier(cUnit);
- NewLIR0(cUnit, kMipsCurrPC); // Really a jal to .+8
+ GenBarrier(cu);
+ NewLIR0(cu, kMipsCurrPC); // Really a jal to .+8
// Now, fill the branch delay slot with bias strip
- if (lowKey == 0) {
- NewLIR0(cUnit, kMipsNop);
+ if (low_key == 0) {
+ NewLIR0(cu, kMipsNop);
} else {
- if (largeBias) {
- OpRegRegReg(cUnit, kOpSub, rKey, rlSrc.lowReg, rKey);
+ if (large_bias) {
+ OpRegRegReg(cu, kOpSub, r_key, rl_src.low_reg, r_key);
} else {
- OpRegRegImm(cUnit, kOpSub, rKey, rlSrc.lowReg, lowKey);
+ OpRegRegImm(cu, kOpSub, r_key, rl_src.low_reg, low_key);
}
}
- GenBarrier(cUnit); // Scheduling barrier
+ GenBarrier(cu); // Scheduling barrier
// Construct BaseLabel and set up table base register
- LIR* baseLabel = NewLIR0(cUnit, kPseudoTargetLabel);
+ LIR* base_label = NewLIR0(cu, kPseudoTargetLabel);
// Remember base label so offsets can be computed later
- tabRec->anchor = baseLabel;
+ tab_rec->anchor = base_label;
// Bounds check - if < 0 or >= size continue following switch
- LIR* branchOver = OpCmpImmBranch(cUnit, kCondHi, rKey, size-1, NULL);
+ LIR* branch_over = OpCmpImmBranch(cu, kCondHi, r_key, size-1, NULL);
// Materialize the table base pointer
- int rBase = AllocTemp(cUnit);
- NewLIR4(cUnit, kMipsDelta, rBase, 0, reinterpret_cast<uintptr_t>(baseLabel),
- reinterpret_cast<uintptr_t>(tabRec));
+ int rBase = AllocTemp(cu);
+ NewLIR4(cu, kMipsDelta, rBase, 0, reinterpret_cast<uintptr_t>(base_label),
+ reinterpret_cast<uintptr_t>(tab_rec));
// Load the displacement from the switch table
- int rDisp = AllocTemp(cUnit);
- LoadBaseIndexed(cUnit, rBase, rKey, rDisp, 2, kWord);
+ int r_disp = AllocTemp(cu);
+ LoadBaseIndexed(cu, rBase, r_key, r_disp, 2, kWord);
// Add to r_AP and go
- OpRegRegReg(cUnit, kOpAdd, r_RA, r_RA, rDisp);
- OpReg(cUnit, kOpBx, r_RA);
+ OpRegRegReg(cu, kOpAdd, r_RA, r_RA, r_disp);
+ OpReg(cu, kOpBx, r_RA);
- /* branchOver target here */
- LIR* target = NewLIR0(cUnit, kPseudoTargetLabel);
- branchOver->target = target;
+ /* branch_over target here */
+ LIR* target = NewLIR0(cu, kPseudoTargetLabel);
+ branch_over->target = target;
}
/*
@@ -224,155 +224,155 @@
*
* Total size is 4+(width * size + 1)/2 16-bit code units.
*/
-void GenFillArrayData(CompilationUnit* cUnit, uint32_t tableOffset,
- RegLocation rlSrc)
+void GenFillArrayData(CompilationUnit* cu, uint32_t table_offset,
+ RegLocation rl_src)
{
- const uint16_t* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
+ const uint16_t* table = cu->insns + cu->current_dalvik_offset + table_offset;
// Add the table to the list - we'll process it later
- FillArrayData *tabRec =
- reinterpret_cast<FillArrayData*>(NewMem(cUnit, sizeof(FillArrayData), true, kAllocData));
- tabRec->table = table;
- tabRec->vaddr = cUnit->currentDalvikOffset;
- uint16_t width = tabRec->table[1];
- uint32_t size = tabRec->table[2] | ((static_cast<uint32_t>(tabRec->table[3])) << 16);
- tabRec->size = (size * width) + 8;
+ FillArrayData *tab_rec =
+ reinterpret_cast<FillArrayData*>(NewMem(cu, sizeof(FillArrayData), true, kAllocData));
+ tab_rec->table = table;
+ tab_rec->vaddr = cu->current_dalvik_offset;
+ uint16_t width = tab_rec->table[1];
+ uint32_t size = tab_rec->table[2] | ((static_cast<uint32_t>(tab_rec->table[3])) << 16);
+ tab_rec->size = (size * width) + 8;
- InsertGrowableList(cUnit, &cUnit->fillArrayData, reinterpret_cast<uintptr_t>(tabRec));
+ InsertGrowableList(cu, &cu->fill_array_data, reinterpret_cast<uintptr_t>(tab_rec));
// Making a call - use explicit registers
- FlushAllRegs(cUnit); /* Everything to home location */
- LockCallTemps(cUnit);
- LoadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0);
+ FlushAllRegs(cu); /* Everything to home location */
+ LockCallTemps(cu);
+ LoadValueDirectFixed(cu, rl_src, rMIPS_ARG0);
// Must prevent code motion for the curr pc pair
- GenBarrier(cUnit);
- NewLIR0(cUnit, kMipsCurrPC); // Really a jal to .+8
+ GenBarrier(cu);
+ NewLIR0(cu, kMipsCurrPC); // Really a jal to .+8
// Now, fill the branch delay slot with the helper load
- int rTgt = LoadHelper(cUnit, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode));
- GenBarrier(cUnit); // Scheduling barrier
+ int r_tgt = LoadHelper(cu, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode));
+ GenBarrier(cu); // Scheduling barrier
// Construct BaseLabel and set up table base register
- LIR* baseLabel = NewLIR0(cUnit, kPseudoTargetLabel);
+ LIR* base_label = NewLIR0(cu, kPseudoTargetLabel);
// Materialize a pointer to the fill data image
- NewLIR4(cUnit, kMipsDelta, rMIPS_ARG1, 0, reinterpret_cast<uintptr_t>(baseLabel),
- reinterpret_cast<uintptr_t>(tabRec));
+ NewLIR4(cu, kMipsDelta, rMIPS_ARG1, 0, reinterpret_cast<uintptr_t>(base_label),
+ reinterpret_cast<uintptr_t>(tab_rec));
// And go...
- ClobberCalleeSave(cUnit);
- LIR* callInst = OpReg(cUnit, kOpBlx, rTgt); // ( array*, fill_data* )
- MarkSafepointPC(cUnit, callInst);
+ ClobberCalleeSave(cu);
+ LIR* call_inst = OpReg(cu, kOpBlx, r_tgt); // ( array*, fill_data* )
+ MarkSafepointPC(cu, call_inst);
}
/*
* TODO: implement fast path to short-circuit thin-lock case
*/
-void GenMonitorEnter(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
+void GenMonitorEnter(CompilationUnit* cu, int opt_flags, RegLocation rl_src)
{
- FlushAllRegs(cUnit);
- LoadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0); // Get obj
- LockCallTemps(cUnit); // Prepare for explicit register usage
- GenNullCheck(cUnit, rlSrc.sRegLow, rMIPS_ARG0, optFlags);
+ FlushAllRegs(cu);
+ LoadValueDirectFixed(cu, rl_src, rMIPS_ARG0); // Get obj
+ LockCallTemps(cu); // Prepare for explicit register usage
+ GenNullCheck(cu, rl_src.s_reg_low, rMIPS_ARG0, opt_flags);
// Go expensive route - artLockObjectFromCode(self, obj);
- int rTgt = LoadHelper(cUnit, ENTRYPOINT_OFFSET(pLockObjectFromCode));
- ClobberCalleeSave(cUnit);
- LIR* callInst = OpReg(cUnit, kOpBlx, rTgt);
- MarkSafepointPC(cUnit, callInst);
+ int r_tgt = LoadHelper(cu, ENTRYPOINT_OFFSET(pLockObjectFromCode));
+ ClobberCalleeSave(cu);
+ LIR* call_inst = OpReg(cu, kOpBlx, r_tgt);
+ MarkSafepointPC(cu, call_inst);
}
/*
* TODO: implement fast path to short-circuit thin-lock case
*/
-void GenMonitorExit(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
+void GenMonitorExit(CompilationUnit* cu, int opt_flags, RegLocation rl_src)
{
- FlushAllRegs(cUnit);
- LoadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0); // Get obj
- LockCallTemps(cUnit); // Prepare for explicit register usage
- GenNullCheck(cUnit, rlSrc.sRegLow, rMIPS_ARG0, optFlags);
+ FlushAllRegs(cu);
+ LoadValueDirectFixed(cu, rl_src, rMIPS_ARG0); // Get obj
+ LockCallTemps(cu); // Prepare for explicit register usage
+ GenNullCheck(cu, rl_src.s_reg_low, rMIPS_ARG0, opt_flags);
// Go expensive route - UnlockObjectFromCode(obj);
- int rTgt = LoadHelper(cUnit, ENTRYPOINT_OFFSET(pUnlockObjectFromCode));
- ClobberCalleeSave(cUnit);
- LIR* callInst = OpReg(cUnit, kOpBlx, rTgt);
- MarkSafepointPC(cUnit, callInst);
+ int r_tgt = LoadHelper(cu, ENTRYPOINT_OFFSET(pUnlockObjectFromCode));
+ ClobberCalleeSave(cu);
+ LIR* call_inst = OpReg(cu, kOpBlx, r_tgt);
+ MarkSafepointPC(cu, call_inst);
}
/*
* Mark garbage collection card. Skip if the value we're storing is null.
*/
-void MarkGCCard(CompilationUnit* cUnit, int valReg, int tgtAddrReg)
+void MarkGCCard(CompilationUnit* cu, int val_reg, int tgt_addr_reg)
{
- int regCardBase = AllocTemp(cUnit);
- int regCardNo = AllocTemp(cUnit);
- LIR* branchOver = OpCmpImmBranch(cUnit, kCondEq, valReg, 0, NULL);
- LoadWordDisp(cUnit, rMIPS_SELF, Thread::CardTableOffset().Int32Value(), regCardBase);
- OpRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, CardTable::kCardShift);
- StoreBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
+ int reg_card_base = AllocTemp(cu);
+ int reg_card_no = AllocTemp(cu);
+ LIR* branch_over = OpCmpImmBranch(cu, kCondEq, val_reg, 0, NULL);
+ LoadWordDisp(cu, rMIPS_SELF, Thread::CardTableOffset().Int32Value(), reg_card_base);
+ OpRegRegImm(cu, kOpLsr, reg_card_no, tgt_addr_reg, CardTable::kCardShift);
+ StoreBaseIndexed(cu, reg_card_base, reg_card_no, reg_card_base, 0,
kUnsignedByte);
- LIR* target = NewLIR0(cUnit, kPseudoTargetLabel);
- branchOver->target = target;
- FreeTemp(cUnit, regCardBase);
- FreeTemp(cUnit, regCardNo);
+ LIR* target = NewLIR0(cu, kPseudoTargetLabel);
+ branch_over->target = target;
+ FreeTemp(cu, reg_card_base);
+ FreeTemp(cu, reg_card_no);
}
-void GenEntrySequence(CompilationUnit* cUnit, RegLocation* ArgLocs,
- RegLocation rlMethod)
+void GenEntrySequence(CompilationUnit* cu, RegLocation* ArgLocs,
+ RegLocation rl_method)
{
- int spillCount = cUnit->numCoreSpills + cUnit->numFPSpills;
+ int spill_count = cu->num_core_spills + cu->num_fp_spills;
/*
* On entry, rMIPS_ARG0, rMIPS_ARG1, rMIPS_ARG2 & rMIPS_ARG3 are live. Let the register
* allocation mechanism know so it doesn't try to use any of them when
* expanding the frame or flushing. This leaves the utility
* code with a single temp: r12. This should be enough.
*/
- LockTemp(cUnit, rMIPS_ARG0);
- LockTemp(cUnit, rMIPS_ARG1);
- LockTemp(cUnit, rMIPS_ARG2);
- LockTemp(cUnit, rMIPS_ARG3);
+ LockTemp(cu, rMIPS_ARG0);
+ LockTemp(cu, rMIPS_ARG1);
+ LockTemp(cu, rMIPS_ARG2);
+ LockTemp(cu, rMIPS_ARG3);
/*
* We can safely skip the stack overflow check if we're
* a leaf *and* our frame size < fudge factor.
*/
- bool skipOverflowCheck = ((cUnit->attrs & METHOD_IS_LEAF) &&
- (static_cast<size_t>(cUnit->frameSize) < Thread::kStackOverflowReservedBytes));
- NewLIR0(cUnit, kPseudoMethodEntry);
- int checkReg = AllocTemp(cUnit);
- int newSP = AllocTemp(cUnit);
- if (!skipOverflowCheck) {
+ bool skip_overflow_check = ((cu->attrs & METHOD_IS_LEAF) &&
+ (static_cast<size_t>(cu->frame_size) < Thread::kStackOverflowReservedBytes));
+ NewLIR0(cu, kPseudoMethodEntry);
+ int check_reg = AllocTemp(cu);
+ int new_sp = AllocTemp(cu);
+ if (!skip_overflow_check) {
/* Load stack limit */
- LoadWordDisp(cUnit, rMIPS_SELF, Thread::StackEndOffset().Int32Value(), checkReg);
+ LoadWordDisp(cu, rMIPS_SELF, Thread::StackEndOffset().Int32Value(), check_reg);
}
/* Spill core callee saves */
- SpillCoreRegs(cUnit);
+ SpillCoreRegs(cu);
/* NOTE: promotion of FP regs currently unsupported, thus no FP spill */
- DCHECK_EQ(cUnit->numFPSpills, 0);
- if (!skipOverflowCheck) {
- OpRegRegImm(cUnit, kOpSub, newSP, rMIPS_SP, cUnit->frameSize - (spillCount * 4));
- GenRegRegCheck(cUnit, kCondCc, newSP, checkReg, kThrowStackOverflow);
- OpRegCopy(cUnit, rMIPS_SP, newSP); // Establish stack
+ DCHECK_EQ(cu->num_fp_spills, 0);
+ if (!skip_overflow_check) {
+ OpRegRegImm(cu, kOpSub, new_sp, rMIPS_SP, cu->frame_size - (spill_count * 4));
+ GenRegRegCheck(cu, kCondCc, new_sp, check_reg, kThrowStackOverflow);
+ OpRegCopy(cu, rMIPS_SP, new_sp); // Establish stack
} else {
- OpRegImm(cUnit, kOpSub, rMIPS_SP, cUnit->frameSize - (spillCount * 4));
+ OpRegImm(cu, kOpSub, rMIPS_SP, cu->frame_size - (spill_count * 4));
}
- FlushIns(cUnit, ArgLocs, rlMethod);
+ FlushIns(cu, ArgLocs, rl_method);
- FreeTemp(cUnit, rMIPS_ARG0);
- FreeTemp(cUnit, rMIPS_ARG1);
- FreeTemp(cUnit, rMIPS_ARG2);
- FreeTemp(cUnit, rMIPS_ARG3);
+ FreeTemp(cu, rMIPS_ARG0);
+ FreeTemp(cu, rMIPS_ARG1);
+ FreeTemp(cu, rMIPS_ARG2);
+ FreeTemp(cu, rMIPS_ARG3);
}
-void GenExitSequence(CompilationUnit* cUnit)
+void GenExitSequence(CompilationUnit* cu)
{
/*
* In the exit path, rMIPS_RET0/rMIPS_RET1 are live - make sure they aren't
* allocated by the register utilities as temps.
*/
- LockTemp(cUnit, rMIPS_RET0);
- LockTemp(cUnit, rMIPS_RET1);
+ LockTemp(cu, rMIPS_RET0);
+ LockTemp(cu, rMIPS_RET1);
- NewLIR0(cUnit, kPseudoMethodExit);
- UnSpillCoreRegs(cUnit);
- OpReg(cUnit, kOpBx, r_RA);
+ NewLIR0(cu, kPseudoMethodExit);
+ UnSpillCoreRegs(cu);
+ OpReg(cu, kOpBx, r_RA);
}
} // namespace art
diff --git a/src/compiler/codegen/mips/fp_mips.cc b/src/compiler/codegen/mips/fp_mips.cc
index 942259d..8f33dfa 100644
--- a/src/compiler/codegen/mips/fp_mips.cc
+++ b/src/compiler/codegen/mips/fp_mips.cc
@@ -21,12 +21,12 @@
namespace art {
-bool GenArithOpFloat(CompilationUnit *cUnit, Instruction::Code opcode, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2)
+bool GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
+ RegLocation rl_src1, RegLocation rl_src2)
{
#ifdef __mips_hard_float
int op = kMipsNop;
- RegLocation rlResult;
+ RegLocation rl_result;
/*
* Don't attempt to optimize register usage since these opcodes call out to
@@ -52,29 +52,29 @@
case Instruction::REM_FLOAT_2ADDR:
case Instruction::REM_FLOAT:
case Instruction::NEG_FLOAT: {
- return GenArithOpFloatPortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
+ return GenArithOpFloatPortable(cu, opcode, rl_dest, rl_src1, rl_src2);
}
default:
return true;
}
- rlSrc1 = LoadValue(cUnit, rlSrc1, kFPReg);
- rlSrc2 = LoadValue(cUnit, rlSrc2, kFPReg);
- rlResult = EvalLoc(cUnit, rlDest, kFPReg, true);
- NewLIR3(cUnit, op, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
- StoreValue(cUnit, rlDest, rlResult);
+ rl_src1 = LoadValue(cu, rl_src1, kFPReg);
+ rl_src2 = LoadValue(cu, rl_src2, kFPReg);
+ rl_result = EvalLoc(cu, rl_dest, kFPReg, true);
+ NewLIR3(cu, op, rl_result.low_reg, rl_src1.low_reg, rl_src2.low_reg);
+ StoreValue(cu, rl_dest, rl_result);
return false;
#else
- return GenArithOpFloatPortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
+ return GenArithOpFloatPortable(cu, opcode, rl_dest, rl_src1, rl_src2);
#endif
}
-bool GenArithOpDouble(CompilationUnit *cUnit, Instruction::Code opcode,
- RegLocation rlDest, RegLocation rlSrc1, RegLocation rlSrc2)
+bool GenArithOpDouble(CompilationUnit *cu, Instruction::Code opcode,
+ RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
{
#ifdef __mips_hard_float
int op = kMipsNop;
- RegLocation rlResult;
+ RegLocation rl_result;
switch (opcode) {
case Instruction::ADD_DOUBLE_2ADDR:
@@ -96,34 +96,34 @@
case Instruction::REM_DOUBLE_2ADDR:
case Instruction::REM_DOUBLE:
case Instruction::NEG_DOUBLE: {
- return GenArithOpDoublePortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
+ return GenArithOpDoublePortable(cu, opcode, rl_dest, rl_src1, rl_src2);
}
default:
return true;
}
- rlSrc1 = LoadValueWide(cUnit, rlSrc1, kFPReg);
- DCHECK(rlSrc1.wide);
- rlSrc2 = LoadValueWide(cUnit, rlSrc2, kFPReg);
- DCHECK(rlSrc2.wide);
- rlResult = EvalLoc(cUnit, rlDest, kFPReg, true);
- DCHECK(rlDest.wide);
- DCHECK(rlResult.wide);
- NewLIR3(cUnit, op, S2d(rlResult.lowReg, rlResult.highReg), S2d(rlSrc1.lowReg, rlSrc1.highReg),
- S2d(rlSrc2.lowReg, rlSrc2.highReg));
- StoreValueWide(cUnit, rlDest, rlResult);
+ rl_src1 = LoadValueWide(cu, rl_src1, kFPReg);
+ DCHECK(rl_src1.wide);
+ rl_src2 = LoadValueWide(cu, rl_src2, kFPReg);
+ DCHECK(rl_src2.wide);
+ rl_result = EvalLoc(cu, rl_dest, kFPReg, true);
+ DCHECK(rl_dest.wide);
+ DCHECK(rl_result.wide);
+ NewLIR3(cu, op, S2d(rl_result.low_reg, rl_result.high_reg), S2d(rl_src1.low_reg, rl_src1.high_reg),
+ S2d(rl_src2.low_reg, rl_src2.high_reg));
+ StoreValueWide(cu, rl_dest, rl_result);
return false;
#else
- return GenArithOpDoublePortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
+ return GenArithOpDoublePortable(cu, opcode, rl_dest, rl_src1, rl_src2);
#endif
}
-bool GenConversion(CompilationUnit *cUnit, Instruction::Code opcode, RegLocation rlDest,
- RegLocation rlSrc)
+bool GenConversion(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
+ RegLocation rl_src)
{
#ifdef __mips_hard_float
int op = kMipsNop;
- int srcReg;
- RegLocation rlResult;
+ int src_reg;
+ RegLocation rl_result;
switch (opcode) {
case Instruction::INT_TO_FLOAT:
op = kMipsFcvtsw;
@@ -143,34 +143,34 @@
case Instruction::FLOAT_TO_LONG:
case Instruction::LONG_TO_FLOAT:
case Instruction::DOUBLE_TO_LONG:
- return GenConversionPortable(cUnit, opcode, rlDest, rlSrc);
+ return GenConversionPortable(cu, opcode, rl_dest, rl_src);
default:
return true;
}
- if (rlSrc.wide) {
- rlSrc = LoadValueWide(cUnit, rlSrc, kFPReg);
- srcReg = S2d(rlSrc.lowReg, rlSrc.highReg);
+ if (rl_src.wide) {
+ rl_src = LoadValueWide(cu, rl_src, kFPReg);
+ src_reg = S2d(rl_src.low_reg, rl_src.high_reg);
} else {
- rlSrc = LoadValue(cUnit, rlSrc, kFPReg);
- srcReg = rlSrc.lowReg;
+ rl_src = LoadValue(cu, rl_src, kFPReg);
+ src_reg = rl_src.low_reg;
}
- if (rlDest.wide) {
- rlResult = EvalLoc(cUnit, rlDest, kFPReg, true);
- NewLIR2(cUnit, op, S2d(rlResult.lowReg, rlResult.highReg), srcReg);
- StoreValueWide(cUnit, rlDest, rlResult);
+ if (rl_dest.wide) {
+ rl_result = EvalLoc(cu, rl_dest, kFPReg, true);
+ NewLIR2(cu, op, S2d(rl_result.low_reg, rl_result.high_reg), src_reg);
+ StoreValueWide(cu, rl_dest, rl_result);
} else {
- rlResult = EvalLoc(cUnit, rlDest, kFPReg, true);
- NewLIR2(cUnit, op, rlResult.lowReg, srcReg);
- StoreValue(cUnit, rlDest, rlResult);
+ rl_result = EvalLoc(cu, rl_dest, kFPReg, true);
+ NewLIR2(cu, op, rl_result.low_reg, src_reg);
+ StoreValue(cu, rl_dest, rl_result);
}
return false;
#else
- return GenConversionPortable(cUnit, opcode, rlDest, rlSrc);
+ return GenConversionPortable(cu, opcode, rl_dest, rl_src);
#endif
}
-bool GenCmpFP(CompilationUnit *cUnit, Instruction::Code opcode, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2)
+bool GenCmpFP(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
+ RegLocation rl_src1, RegLocation rl_src2)
{
bool wide = true;
int offset;
@@ -193,49 +193,49 @@
default:
return true;
}
- FlushAllRegs(cUnit);
- LockCallTemps(cUnit);
+ FlushAllRegs(cu);
+ LockCallTemps(cu);
if (wide) {
- LoadValueDirectWideFixed(cUnit, rlSrc1, rMIPS_FARG0, rMIPS_FARG1);
- LoadValueDirectWideFixed(cUnit, rlSrc2, rMIPS_FARG2, rMIPS_FARG3);
+ LoadValueDirectWideFixed(cu, rl_src1, rMIPS_FARG0, rMIPS_FARG1);
+ LoadValueDirectWideFixed(cu, rl_src2, rMIPS_FARG2, rMIPS_FARG3);
} else {
- LoadValueDirectFixed(cUnit, rlSrc1, rMIPS_FARG0);
- LoadValueDirectFixed(cUnit, rlSrc2, rMIPS_FARG2);
+ LoadValueDirectFixed(cu, rl_src1, rMIPS_FARG0);
+ LoadValueDirectFixed(cu, rl_src2, rMIPS_FARG2);
}
- int rTgt = LoadHelper(cUnit, offset);
+ int r_tgt = LoadHelper(cu, offset);
// NOTE: not a safepoint
- OpReg(cUnit, kOpBlx, rTgt);
- RegLocation rlResult = GetReturn(cUnit, false);
- StoreValue(cUnit, rlDest, rlResult);
+ OpReg(cu, kOpBlx, r_tgt);
+ RegLocation rl_result = GetReturn(cu, false);
+ StoreValue(cu, rl_dest, rl_result);
return false;
}
-void GenFusedFPCmpBranch(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
- bool gtBias, bool isDouble)
+void GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir,
+ bool gt_bias, bool is_double)
{
UNIMPLEMENTED(FATAL) << "Need codegen for fused fp cmp branch";
}
-void GenNegFloat(CompilationUnit *cUnit, RegLocation rlDest, RegLocation rlSrc)
+void GenNegFloat(CompilationUnit *cu, RegLocation rl_dest, RegLocation rl_src)
{
- RegLocation rlResult;
- rlSrc = LoadValue(cUnit, rlSrc, kCoreReg);
- rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
- OpRegRegImm(cUnit, kOpAdd, rlResult.lowReg, rlSrc.lowReg, 0x80000000);
- StoreValue(cUnit, rlDest, rlResult);
+ RegLocation rl_result;
+ rl_src = LoadValue(cu, rl_src, kCoreReg);
+ rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
+ OpRegRegImm(cu, kOpAdd, rl_result.low_reg, rl_src.low_reg, 0x80000000);
+ StoreValue(cu, rl_dest, rl_result);
}
-void GenNegDouble(CompilationUnit *cUnit, RegLocation rlDest, RegLocation rlSrc)
+void GenNegDouble(CompilationUnit *cu, RegLocation rl_dest, RegLocation rl_src)
{
- RegLocation rlResult;
- rlSrc = LoadValueWide(cUnit, rlSrc, kCoreReg);
- rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
- OpRegRegImm(cUnit, kOpAdd, rlResult.highReg, rlSrc.highReg, 0x80000000);
- OpRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
- StoreValueWide(cUnit, rlDest, rlResult);
+ RegLocation rl_result;
+ rl_src = LoadValueWide(cu, rl_src, kCoreReg);
+ rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
+ OpRegRegImm(cu, kOpAdd, rl_result.high_reg, rl_src.high_reg, 0x80000000);
+ OpRegCopy(cu, rl_result.low_reg, rl_src.low_reg);
+ StoreValueWide(cu, rl_dest, rl_result);
}
-bool GenInlinedMinMaxInt(CompilationUnit *cUnit, CallInfo* info, bool isMin)
+bool GenInlinedMinMaxInt(CompilationUnit *cu, CallInfo* info, bool is_min)
{
// TODO: need Mips implementation
return false;
diff --git a/src/compiler/codegen/mips/int_mips.cc b/src/compiler/codegen/mips/int_mips.cc
index 29b08ed..273e4bd 100644
--- a/src/compiler/codegen/mips/int_mips.cc
+++ b/src/compiler/codegen/mips/int_mips.cc
@@ -39,106 +39,106 @@
* finish:
*
*/
-void GenCmpLong(CompilationUnit* cUnit, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2)
+void GenCmpLong(CompilationUnit* cu, RegLocation rl_dest,
+ RegLocation rl_src1, RegLocation rl_src2)
{
- rlSrc1 = LoadValueWide(cUnit, rlSrc1, kCoreReg);
- rlSrc2 = LoadValueWide(cUnit, rlSrc2, kCoreReg);
- int t0 = AllocTemp(cUnit);
- int t1 = AllocTemp(cUnit);
- RegLocation rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
- NewLIR3(cUnit, kMipsSlt, t0, rlSrc1.highReg, rlSrc2.highReg);
- NewLIR3(cUnit, kMipsSlt, t1, rlSrc2.highReg, rlSrc1.highReg);
- NewLIR3(cUnit, kMipsSubu, rlResult.lowReg, t1, t0);
- LIR* branch = OpCmpImmBranch(cUnit, kCondNe, rlResult.lowReg, 0, NULL);
- NewLIR3(cUnit, kMipsSltu, t0, rlSrc1.lowReg, rlSrc2.lowReg);
- NewLIR3(cUnit, kMipsSltu, t1, rlSrc2.lowReg, rlSrc1.lowReg);
- NewLIR3(cUnit, kMipsSubu, rlResult.lowReg, t1, t0);
- FreeTemp(cUnit, t0);
- FreeTemp(cUnit, t1);
- LIR* target = NewLIR0(cUnit, kPseudoTargetLabel);
+ rl_src1 = LoadValueWide(cu, rl_src1, kCoreReg);
+ rl_src2 = LoadValueWide(cu, rl_src2, kCoreReg);
+ int t0 = AllocTemp(cu);
+ int t1 = AllocTemp(cu);
+ RegLocation rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
+ NewLIR3(cu, kMipsSlt, t0, rl_src1.high_reg, rl_src2.high_reg);
+ NewLIR3(cu, kMipsSlt, t1, rl_src2.high_reg, rl_src1.high_reg);
+ NewLIR3(cu, kMipsSubu, rl_result.low_reg, t1, t0);
+ LIR* branch = OpCmpImmBranch(cu, kCondNe, rl_result.low_reg, 0, NULL);
+ NewLIR3(cu, kMipsSltu, t0, rl_src1.low_reg, rl_src2.low_reg);
+ NewLIR3(cu, kMipsSltu, t1, rl_src2.low_reg, rl_src1.low_reg);
+ NewLIR3(cu, kMipsSubu, rl_result.low_reg, t1, t0);
+ FreeTemp(cu, t0);
+ FreeTemp(cu, t1);
+ LIR* target = NewLIR0(cu, kPseudoTargetLabel);
branch->target = target;
- StoreValue(cUnit, rlDest, rlResult);
+ StoreValue(cu, rl_dest, rl_result);
}
-LIR* OpCmpBranch(CompilationUnit* cUnit, ConditionCode cond, int src1,
+LIR* OpCmpBranch(CompilationUnit* cu, ConditionCode cond, int src1,
int src2, LIR* target)
{
LIR* branch;
- MipsOpCode sltOp;
- MipsOpCode brOp;
- bool cmpZero = false;
+ MipsOpCode slt_op;
+ MipsOpCode br_op;
+ bool cmp_zero = false;
bool swapped = false;
switch (cond) {
case kCondEq:
- brOp = kMipsBeq;
- cmpZero = true;
+ br_op = kMipsBeq;
+ cmp_zero = true;
break;
case kCondNe:
- brOp = kMipsBne;
- cmpZero = true;
+ br_op = kMipsBne;
+ cmp_zero = true;
break;
case kCondCc:
- sltOp = kMipsSltu;
- brOp = kMipsBnez;
+ slt_op = kMipsSltu;
+ br_op = kMipsBnez;
break;
case kCondCs:
- sltOp = kMipsSltu;
- brOp = kMipsBeqz;
+ slt_op = kMipsSltu;
+ br_op = kMipsBeqz;
break;
case kCondGe:
- sltOp = kMipsSlt;
- brOp = kMipsBeqz;
+ slt_op = kMipsSlt;
+ br_op = kMipsBeqz;
break;
case kCondGt:
- sltOp = kMipsSlt;
- brOp = kMipsBnez;
+ slt_op = kMipsSlt;
+ br_op = kMipsBnez;
swapped = true;
break;
case kCondLe:
- sltOp = kMipsSlt;
- brOp = kMipsBeqz;
+ slt_op = kMipsSlt;
+ br_op = kMipsBeqz;
swapped = true;
break;
case kCondLt:
- sltOp = kMipsSlt;
- brOp = kMipsBnez;
+ slt_op = kMipsSlt;
+ br_op = kMipsBnez;
break;
case kCondHi: // Gtu
- sltOp = kMipsSltu;
- brOp = kMipsBnez;
+ slt_op = kMipsSltu;
+ br_op = kMipsBnez;
swapped = true;
break;
default:
LOG(FATAL) << "No support for ConditionCode: " << cond;
return NULL;
}
- if (cmpZero) {
- branch = NewLIR2(cUnit, brOp, src1, src2);
+ if (cmp_zero) {
+ branch = NewLIR2(cu, br_op, src1, src2);
} else {
- int tReg = AllocTemp(cUnit);
+ int t_reg = AllocTemp(cu);
if (swapped) {
- NewLIR3(cUnit, sltOp, tReg, src2, src1);
+ NewLIR3(cu, slt_op, t_reg, src2, src1);
} else {
- NewLIR3(cUnit, sltOp, tReg, src1, src2);
+ NewLIR3(cu, slt_op, t_reg, src1, src2);
}
- branch = NewLIR1(cUnit, brOp, tReg);
- FreeTemp(cUnit, tReg);
+ branch = NewLIR1(cu, br_op, t_reg);
+ FreeTemp(cu, t_reg);
}
branch->target = target;
return branch;
}
-LIR* OpCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
- int checkValue, LIR* target)
+LIR* OpCmpImmBranch(CompilationUnit* cu, ConditionCode cond, int reg,
+ int check_value, LIR* target)
{
LIR* branch;
- if (checkValue != 0) {
+ if (check_value != 0) {
// TUNING: handle s16 & kCondLt/Mi case using slti
- int tReg = AllocTemp(cUnit);
- LoadConstant(cUnit, tReg, checkValue);
- branch = OpCmpBranch(cUnit, cond, reg, tReg, target);
- FreeTemp(cUnit, tReg);
+ int t_reg = AllocTemp(cu);
+ LoadConstant(cu, t_reg, check_value);
+ branch = OpCmpBranch(cu, cond, reg, t_reg, target);
+ FreeTemp(cu, t_reg);
return branch;
}
MipsOpCode opc;
@@ -152,211 +152,211 @@
case kCondNe: opc = kMipsBnez; break;
default:
// Tuning: use slti when applicable
- int tReg = AllocTemp(cUnit);
- LoadConstant(cUnit, tReg, checkValue);
- branch = OpCmpBranch(cUnit, cond, reg, tReg, target);
- FreeTemp(cUnit, tReg);
+ int t_reg = AllocTemp(cu);
+ LoadConstant(cu, t_reg, check_value);
+ branch = OpCmpBranch(cu, cond, reg, t_reg, target);
+ FreeTemp(cu, t_reg);
return branch;
}
- branch = NewLIR1(cUnit, opc, reg);
+ branch = NewLIR1(cu, opc, reg);
branch->target = target;
return branch;
}
-LIR* OpRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
+LIR* OpRegCopyNoInsert(CompilationUnit *cu, int r_dest, int r_src)
{
#ifdef __mips_hard_float
- if (MIPS_FPREG(rDest) || MIPS_FPREG(rSrc))
- return FpRegCopy(cUnit, rDest, rSrc);
+ if (MIPS_FPREG(r_dest) || MIPS_FPREG(r_src))
+ return FpRegCopy(cu, r_dest, r_src);
#endif
- LIR* res = RawLIR(cUnit, cUnit->currentDalvikOffset, kMipsMove,
- rDest, rSrc);
- if (!(cUnit->disableOpt & (1 << kSafeOptimizations)) && rDest == rSrc) {
- res->flags.isNop = true;
+ LIR* res = RawLIR(cu, cu->current_dalvik_offset, kMipsMove,
+ r_dest, r_src);
+ if (!(cu->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
+ res->flags.is_nop = true;
}
return res;
}
-LIR* OpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
+LIR* OpRegCopy(CompilationUnit *cu, int r_dest, int r_src)
{
- LIR *res = OpRegCopyNoInsert(cUnit, rDest, rSrc);
- AppendLIR(cUnit, res);
+ LIR *res = OpRegCopyNoInsert(cu, r_dest, r_src);
+ AppendLIR(cu, res);
return res;
}
-void OpRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
- int srcLo, int srcHi)
+void OpRegCopyWide(CompilationUnit *cu, int dest_lo, int dest_hi,
+ int src_lo, int src_hi)
{
#ifdef __mips_hard_float
- bool destFP = MIPS_FPREG(destLo) && MIPS_FPREG(destHi);
- bool srcFP = MIPS_FPREG(srcLo) && MIPS_FPREG(srcHi);
- assert(MIPS_FPREG(srcLo) == MIPS_FPREG(srcHi));
- assert(MIPS_FPREG(destLo) == MIPS_FPREG(destHi));
- if (destFP) {
- if (srcFP) {
- OpRegCopy(cUnit, S2d(destLo, destHi), S2d(srcLo, srcHi));
+ bool dest_fp = MIPS_FPREG(dest_lo) && MIPS_FPREG(dest_hi);
+ bool src_fp = MIPS_FPREG(src_lo) && MIPS_FPREG(src_hi);
+ assert(MIPS_FPREG(src_lo) == MIPS_FPREG(src_hi));
+ assert(MIPS_FPREG(dest_lo) == MIPS_FPREG(dest_hi));
+ if (dest_fp) {
+ if (src_fp) {
+ OpRegCopy(cu, S2d(dest_lo, dest_hi), S2d(src_lo, src_hi));
} else {
/* note the operands are swapped for the mtc1 instr */
- NewLIR2(cUnit, kMipsMtc1, srcLo, destLo);
- NewLIR2(cUnit, kMipsMtc1, srcHi, destHi);
+ NewLIR2(cu, kMipsMtc1, src_lo, dest_lo);
+ NewLIR2(cu, kMipsMtc1, src_hi, dest_hi);
}
} else {
- if (srcFP) {
- NewLIR2(cUnit, kMipsMfc1, destLo, srcLo);
- NewLIR2(cUnit, kMipsMfc1, destHi, srcHi);
+ if (src_fp) {
+ NewLIR2(cu, kMipsMfc1, dest_lo, src_lo);
+ NewLIR2(cu, kMipsMfc1, dest_hi, src_hi);
} else {
// Handle overlap
- if (srcHi == destLo) {
- OpRegCopy(cUnit, destHi, srcHi);
- OpRegCopy(cUnit, destLo, srcLo);
+ if (src_hi == dest_lo) {
+ OpRegCopy(cu, dest_hi, src_hi);
+ OpRegCopy(cu, dest_lo, src_lo);
} else {
- OpRegCopy(cUnit, destLo, srcLo);
- OpRegCopy(cUnit, destHi, srcHi);
+ OpRegCopy(cu, dest_lo, src_lo);
+ OpRegCopy(cu, dest_hi, src_hi);
}
}
}
#else
// Handle overlap
- if (srcHi == destLo) {
- OpRegCopy(cUnit, destHi, srcHi);
- OpRegCopy(cUnit, destLo, srcLo);
+ if (src_hi == dest_lo) {
+ OpRegCopy(cu, dest_hi, src_hi);
+ OpRegCopy(cu, dest_lo, src_lo);
} else {
- OpRegCopy(cUnit, destLo, srcLo);
- OpRegCopy(cUnit, destHi, srcHi);
+ OpRegCopy(cu, dest_lo, src_lo);
+ OpRegCopy(cu, dest_hi, src_hi);
}
#endif
}
-void GenFusedLongCmpBranch(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir)
+void GenFusedLongCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir)
{
UNIMPLEMENTED(FATAL) << "Need codegen for fused long cmp branch";
}
-LIR* GenRegMemCheck(CompilationUnit* cUnit, ConditionCode cCode,
+LIR* GenRegMemCheck(CompilationUnit* cu, ConditionCode c_code,
int reg1, int base, int offset, ThrowKind kind)
{
LOG(FATAL) << "Unexpected use of GenRegMemCheck for Arm";
return NULL;
}
-RegLocation GenDivRem(CompilationUnit* cUnit, RegLocation rlDest, int reg1, int reg2, bool isDiv)
+RegLocation GenDivRem(CompilationUnit* cu, RegLocation rl_dest, int reg1, int reg2, bool is_div)
{
- NewLIR4(cUnit, kMipsDiv, r_HI, r_LO, reg1, reg2);
- RegLocation rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
- if (isDiv) {
- NewLIR2(cUnit, kMipsMflo, rlResult.lowReg, r_LO);
+ NewLIR4(cu, kMipsDiv, r_HI, r_LO, reg1, reg2);
+ RegLocation rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
+ if (is_div) {
+ NewLIR2(cu, kMipsMflo, rl_result.low_reg, r_LO);
} else {
- NewLIR2(cUnit, kMipsMfhi, rlResult.lowReg, r_HI);
+ NewLIR2(cu, kMipsMfhi, rl_result.low_reg, r_HI);
}
- return rlResult;
+ return rl_result;
}
-RegLocation GenDivRemLit(CompilationUnit* cUnit, RegLocation rlDest, int reg1, int lit, bool isDiv)
+RegLocation GenDivRemLit(CompilationUnit* cu, RegLocation rl_dest, int reg1, int lit, bool is_div)
{
- int tReg = AllocTemp(cUnit);
- NewLIR3(cUnit, kMipsAddiu, tReg, r_ZERO, lit);
- NewLIR4(cUnit, kMipsDiv, r_HI, r_LO, reg1, tReg);
- RegLocation rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
- if (isDiv) {
- NewLIR2(cUnit, kMipsMflo, rlResult.lowReg, r_LO);
+ int t_reg = AllocTemp(cu);
+ NewLIR3(cu, kMipsAddiu, t_reg, r_ZERO, lit);
+ NewLIR4(cu, kMipsDiv, r_HI, r_LO, reg1, t_reg);
+ RegLocation rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
+ if (is_div) {
+ NewLIR2(cu, kMipsMflo, rl_result.low_reg, r_LO);
} else {
- NewLIR2(cUnit, kMipsMfhi, rlResult.lowReg, r_HI);
+ NewLIR2(cu, kMipsMfhi, rl_result.low_reg, r_HI);
}
- FreeTemp(cUnit, tReg);
- return rlResult;
+ FreeTemp(cu, t_reg);
+ return rl_result;
}
-void OpLea(CompilationUnit* cUnit, int rBase, int reg1, int reg2, int scale, int offset)
+void OpLea(CompilationUnit* cu, int rBase, int reg1, int reg2, int scale, int offset)
{
LOG(FATAL) << "Unexpected use of OpLea for Arm";
}
-void OpTlsCmp(CompilationUnit* cUnit, int offset, int val)
+void OpTlsCmp(CompilationUnit* cu, int offset, int val)
{
LOG(FATAL) << "Unexpected use of OpTlsCmp for Arm";
}
-bool GenInlinedCas32(CompilationUnit* cUnit, CallInfo* info, bool need_write_barrier) {
- DCHECK_NE(cUnit->instructionSet, kThumb2);
+bool GenInlinedCas32(CompilationUnit* cu, CallInfo* info, bool need_write_barrier) {
+ DCHECK_NE(cu->instruction_set, kThumb2);
return false;
}
-bool GenInlinedSqrt(CompilationUnit* cUnit, CallInfo* info) {
- DCHECK_NE(cUnit->instructionSet, kThumb2);
+bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info) {
+ DCHECK_NE(cu->instruction_set, kThumb2);
return false;
}
-LIR* OpPcRelLoad(CompilationUnit* cUnit, int reg, LIR* target) {
+LIR* OpPcRelLoad(CompilationUnit* cu, int reg, LIR* target) {
LOG(FATAL) << "Unexpected use of OpPcRelLoad for Mips";
return NULL;
}
-LIR* OpVldm(CompilationUnit* cUnit, int rBase, int count)
+LIR* OpVldm(CompilationUnit* cu, int rBase, int count)
{
LOG(FATAL) << "Unexpected use of OpVldm for Mips";
return NULL;
}
-LIR* OpVstm(CompilationUnit* cUnit, int rBase, int count)
+LIR* OpVstm(CompilationUnit* cu, int rBase, int count)
{
LOG(FATAL) << "Unexpected use of OpVstm for Mips";
return NULL;
}
-void GenMultiplyByTwoBitMultiplier(CompilationUnit* cUnit, RegLocation rlSrc,
- RegLocation rlResult, int lit,
- int firstBit, int secondBit)
+void GenMultiplyByTwoBitMultiplier(CompilationUnit* cu, RegLocation rl_src,
+ RegLocation rl_result, int lit,
+ int first_bit, int second_bit)
{
- int tReg = AllocTemp(cUnit);
- OpRegRegImm(cUnit, kOpLsl, tReg, rlSrc.lowReg, secondBit - firstBit);
- OpRegRegReg(cUnit, kOpAdd, rlResult.lowReg, rlSrc.lowReg, tReg);
- FreeTemp(cUnit, tReg);
- if (firstBit != 0) {
- OpRegRegImm(cUnit, kOpLsl, rlResult.lowReg, rlResult.lowReg, firstBit);
+ int t_reg = AllocTemp(cu);
+ OpRegRegImm(cu, kOpLsl, t_reg, rl_src.low_reg, second_bit - first_bit);
+ OpRegRegReg(cu, kOpAdd, rl_result.low_reg, rl_src.low_reg, t_reg);
+ FreeTemp(cu, t_reg);
+ if (first_bit != 0) {
+ OpRegRegImm(cu, kOpLsl, rl_result.low_reg, rl_result.low_reg, first_bit);
}
}
-void GenDivZeroCheck(CompilationUnit* cUnit, int regLo, int regHi)
+void GenDivZeroCheck(CompilationUnit* cu, int reg_lo, int reg_hi)
{
- int tReg = AllocTemp(cUnit);
- OpRegRegReg(cUnit, kOpOr, tReg, regLo, regHi);
- GenImmedCheck(cUnit, kCondEq, tReg, 0, kThrowDivZero);
- FreeTemp(cUnit, tReg);
+ int t_reg = AllocTemp(cu);
+ OpRegRegReg(cu, kOpOr, t_reg, reg_lo, reg_hi);
+ GenImmedCheck(cu, kCondEq, t_reg, 0, kThrowDivZero);
+ FreeTemp(cu, t_reg);
}
// Test suspend flag, return target of taken suspend branch
-LIR* OpTestSuspend(CompilationUnit* cUnit, LIR* target)
+LIR* OpTestSuspend(CompilationUnit* cu, LIR* target)
{
- OpRegImm(cUnit, kOpSub, rMIPS_SUSPEND, 1);
- return OpCmpImmBranch(cUnit, (target == NULL) ? kCondEq : kCondNe, rMIPS_SUSPEND, 0, target);
+ OpRegImm(cu, kOpSub, rMIPS_SUSPEND, 1);
+ return OpCmpImmBranch(cu, (target == NULL) ? kCondEq : kCondNe, rMIPS_SUSPEND, 0, target);
}
// Decrement register and branch on condition
-LIR* OpDecAndBranch(CompilationUnit* cUnit, ConditionCode cCode, int reg, LIR* target)
+LIR* OpDecAndBranch(CompilationUnit* cu, ConditionCode c_code, int reg, LIR* target)
{
- OpRegImm(cUnit, kOpSub, reg, 1);
- return OpCmpImmBranch(cUnit, cCode, reg, 0, target);
+ OpRegImm(cu, kOpSub, reg, 1);
+ return OpCmpImmBranch(cu, c_code, reg, 0, target);
}
-bool SmallLiteralDivide(CompilationUnit* cUnit, Instruction::Code dalvikOpcode,
- RegLocation rlSrc, RegLocation rlDest, int lit)
+bool SmallLiteralDivide(CompilationUnit* cu, Instruction::Code dalvik_opcode,
+ RegLocation rl_src, RegLocation rl_dest, int lit)
{
LOG(FATAL) << "Unexpected use of smallLiteralDive in Mips";
return false;
}
-LIR* OpIT(CompilationUnit* cUnit, ArmConditionCode cond, const char* guide)
+LIR* OpIT(CompilationUnit* cu, ArmConditionCode cond, const char* guide)
{
LOG(FATAL) << "Unexpected use of OpIT in Mips";
return NULL;
}
-bool GenAddLong(CompilationUnit* cUnit, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2)
+bool GenAddLong(CompilationUnit* cu, RegLocation rl_dest,
+ RegLocation rl_src1, RegLocation rl_src2)
{
- rlSrc1 = LoadValueWide(cUnit, rlSrc1, kCoreReg);
- rlSrc2 = LoadValueWide(cUnit, rlSrc2, kCoreReg);
- RegLocation rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
+ rl_src1 = LoadValueWide(cu, rl_src1, kCoreReg);
+ rl_src2 = LoadValueWide(cu, rl_src2, kCoreReg);
+ RegLocation rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
/*
* [v1 v0] = [a1 a0] + [a3 a2];
* addu v0,a2,a0
@@ -365,22 +365,22 @@
* addu v1,v1,t1
*/
- OpRegRegReg(cUnit, kOpAdd, rlResult.lowReg, rlSrc2.lowReg, rlSrc1.lowReg);
- int tReg = AllocTemp(cUnit);
- OpRegRegReg(cUnit, kOpAdd, tReg, rlSrc2.highReg, rlSrc1.highReg);
- NewLIR3(cUnit, kMipsSltu, rlResult.highReg, rlResult.lowReg, rlSrc2.lowReg);
- OpRegRegReg(cUnit, kOpAdd, rlResult.highReg, rlResult.highReg, tReg);
- FreeTemp(cUnit, tReg);
- StoreValueWide(cUnit, rlDest, rlResult);
+ OpRegRegReg(cu, kOpAdd, rl_result.low_reg, rl_src2.low_reg, rl_src1.low_reg);
+ int t_reg = AllocTemp(cu);
+ OpRegRegReg(cu, kOpAdd, t_reg, rl_src2.high_reg, rl_src1.high_reg);
+ NewLIR3(cu, kMipsSltu, rl_result.high_reg, rl_result.low_reg, rl_src2.low_reg);
+ OpRegRegReg(cu, kOpAdd, rl_result.high_reg, rl_result.high_reg, t_reg);
+ FreeTemp(cu, t_reg);
+ StoreValueWide(cu, rl_dest, rl_result);
return false;
}
-bool GenSubLong(CompilationUnit* cUnit, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2)
+bool GenSubLong(CompilationUnit* cu, RegLocation rl_dest,
+ RegLocation rl_src1, RegLocation rl_src2)
{
- rlSrc1 = LoadValueWide(cUnit, rlSrc1, kCoreReg);
- rlSrc2 = LoadValueWide(cUnit, rlSrc2, kCoreReg);
- RegLocation rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
+ rl_src1 = LoadValueWide(cu, rl_src1, kCoreReg);
+ rl_src2 = LoadValueWide(cu, rl_src2, kCoreReg);
+ RegLocation rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
/*
* [v1 v0] = [a1 a0] - [a3 a2];
* sltu t1,a0,a2
@@ -389,21 +389,21 @@
* subu v1,v1,t1
*/
- int tReg = AllocTemp(cUnit);
- NewLIR3(cUnit, kMipsSltu, tReg, rlSrc1.lowReg, rlSrc2.lowReg);
- OpRegRegReg(cUnit, kOpSub, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
- OpRegRegReg(cUnit, kOpSub, rlResult.highReg, rlSrc1.highReg, rlSrc2.highReg);
- OpRegRegReg(cUnit, kOpSub, rlResult.highReg, rlResult.highReg, tReg);
- FreeTemp(cUnit, tReg);
- StoreValueWide(cUnit, rlDest, rlResult);
+ int t_reg = AllocTemp(cu);
+ NewLIR3(cu, kMipsSltu, t_reg, rl_src1.low_reg, rl_src2.low_reg);
+ OpRegRegReg(cu, kOpSub, rl_result.low_reg, rl_src1.low_reg, rl_src2.low_reg);
+ OpRegRegReg(cu, kOpSub, rl_result.high_reg, rl_src1.high_reg, rl_src2.high_reg);
+ OpRegRegReg(cu, kOpSub, rl_result.high_reg, rl_result.high_reg, t_reg);
+ FreeTemp(cu, t_reg);
+ StoreValueWide(cu, rl_dest, rl_result);
return false;
}
-bool GenNegLong(CompilationUnit* cUnit, RegLocation rlDest,
- RegLocation rlSrc)
+bool GenNegLong(CompilationUnit* cu, RegLocation rl_dest,
+ RegLocation rl_src)
{
- rlSrc = LoadValueWide(cUnit, rlSrc, kCoreReg);
- RegLocation rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
+ rl_src = LoadValueWide(cu, rl_src, kCoreReg);
+ RegLocation rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
/*
* [v1 v0] = -[a1 a0]
* negu v0,a0
@@ -412,32 +412,32 @@
* subu v1,v1,t1
*/
- OpRegReg(cUnit, kOpNeg, rlResult.lowReg, rlSrc.lowReg);
- OpRegReg(cUnit, kOpNeg, rlResult.highReg, rlSrc.highReg);
- int tReg = AllocTemp(cUnit);
- NewLIR3(cUnit, kMipsSltu, tReg, r_ZERO, rlResult.lowReg);
- OpRegRegReg(cUnit, kOpSub, rlResult.highReg, rlResult.highReg, tReg);
- FreeTemp(cUnit, tReg);
- StoreValueWide(cUnit, rlDest, rlResult);
+ OpRegReg(cu, kOpNeg, rl_result.low_reg, rl_src.low_reg);
+ OpRegReg(cu, kOpNeg, rl_result.high_reg, rl_src.high_reg);
+ int t_reg = AllocTemp(cu);
+ NewLIR3(cu, kMipsSltu, t_reg, r_ZERO, rl_result.low_reg);
+ OpRegRegReg(cu, kOpSub, rl_result.high_reg, rl_result.high_reg, t_reg);
+ FreeTemp(cu, t_reg);
+ StoreValueWide(cu, rl_dest, rl_result);
return false;
}
-bool GenAndLong(CompilationUnit* cUnit, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2)
+bool GenAndLong(CompilationUnit* cu, RegLocation rl_dest,
+ RegLocation rl_src1, RegLocation rl_src2)
{
LOG(FATAL) << "Unexpected use of GenAndLong for Mips";
return false;
}
-bool GenOrLong(CompilationUnit* cUnit, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2)
+bool GenOrLong(CompilationUnit* cu, RegLocation rl_dest,
+ RegLocation rl_src1, RegLocation rl_src2)
{
LOG(FATAL) << "Unexpected use of GenOrLong for Mips";
return false;
}
-bool GenXorLong(CompilationUnit* cUnit, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2)
+bool GenXorLong(CompilationUnit* cu, RegLocation rl_dest,
+ RegLocation rl_src1, RegLocation rl_src2)
{
LOG(FATAL) << "Unexpected use of GenXorLong for Mips";
return false;
diff --git a/src/compiler/codegen/mips/mips_lir.h b/src/compiler/codegen/mips/mips_lir.h
index de39b7f..e3d9b62 100644
--- a/src/compiler/codegen/mips/mips_lir.h
+++ b/src/compiler/codegen/mips/mips_lir.h
@@ -82,7 +82,7 @@
* | OUT[outs-2] |
* | . |
* | OUT[0] |
- * | curMethod* | <<== sp w/ 16-byte alignment
+ * | cur_method* | <<== sp w/ 16-byte alignment
* +========================+
*/
@@ -406,7 +406,7 @@
};
/* Bit flags describing the behavior of each native opcode */
-/* Instruction assembly fieldLoc kind */
+/* Instruction assembly field_loc kind */
enum MipsEncodingKind {
kFmtUnused,
kFmtBitBlt, /* Bit string using end/start */
@@ -422,7 +422,7 @@
MipsEncodingKind kind;
int end; /* end for kFmtBitBlt, 1-bit slice end for FP regs */
int start; /* start for kFmtBitBlt, 4-bit slice end for FP regs */
- } fieldLoc[4];
+ } field_loc[4];
MipsOpCode opcode;
uint64_t flags;
const char *name;
diff --git a/src/compiler/codegen/mips/target_mips.cc b/src/compiler/codegen/mips/target_mips.cc
index d264343..b9159ed 100644
--- a/src/compiler/codegen/mips/target_mips.cc
+++ b/src/compiler/codegen/mips/target_mips.cc
@@ -23,19 +23,19 @@
namespace art {
-static int coreRegs[] = {r_ZERO, r_AT, r_V0, r_V1, r_A0, r_A1, r_A2, r_A3,
- r_T0, r_T1, r_T2, r_T3, r_T4, r_T5, r_T6, r_T7,
- r_S0, r_S1, r_S2, r_S3, r_S4, r_S5, r_S6, r_S7, r_T8,
- r_T9, r_K0, r_K1, r_GP, r_SP, r_FP, r_RA};
+static int core_regs[] = {r_ZERO, r_AT, r_V0, r_V1, r_A0, r_A1, r_A2, r_A3,
+ r_T0, r_T1, r_T2, r_T3, r_T4, r_T5, r_T6, r_T7,
+ r_S0, r_S1, r_S2, r_S3, r_S4, r_S5, r_S6, r_S7, r_T8,
+ r_T9, r_K0, r_K1, r_GP, r_SP, r_FP, r_RA};
static int ReservedRegs[] = {r_ZERO, r_AT, r_S0, r_S1, r_K0, r_K1, r_GP, r_SP,
r_RA};
-static int coreTemps[] = {r_V0, r_V1, r_A0, r_A1, r_A2, r_A3, r_T0, r_T1, r_T2,
- r_T3, r_T4, r_T5, r_T6, r_T7, r_T8};
+static int core_temps[] = {r_V0, r_V1, r_A0, r_A1, r_A2, r_A3, r_T0, r_T1, r_T2,
+ r_T3, r_T4, r_T5, r_T6, r_T7, r_T8};
#ifdef __mips_hard_float
static int FpRegs[] = {r_F0, r_F1, r_F2, r_F3, r_F4, r_F5, r_F6, r_F7,
r_F8, r_F9, r_F10, r_F11, r_F12, r_F13, r_F14, r_F15};
-static int fpTemps[] = {r_F0, r_F1, r_F2, r_F3, r_F4, r_F5, r_F6, r_F7,
- r_F8, r_F9, r_F10, r_F11, r_F12, r_F13, r_F14, r_F15};
+static int fp_temps[] = {r_F0, r_F1, r_F2, r_F3, r_F4, r_F5, r_F6, r_F7,
+ r_F8, r_F9, r_F10, r_F11, r_F12, r_F13, r_F14, r_F15};
#endif
RegLocation LocCReturn()
@@ -88,9 +88,9 @@
}
// Create a double from a pair of singles.
-int S2d(int lowReg, int highReg)
+int S2d(int low_reg, int high_reg)
{
- return MIPS_S2D(lowReg, highReg);
+ return MIPS_S2D(low_reg, high_reg);
}
// Is reg a single or double?
@@ -126,20 +126,20 @@
/*
* Decode the register id.
*/
-uint64_t GetRegMaskCommon(CompilationUnit* cUnit, int reg)
+uint64_t GetRegMaskCommon(CompilationUnit* cu, int reg)
{
uint64_t seed;
int shift;
- int regId;
+ int reg_id;
- regId = reg & 0x1f;
+ reg_id = reg & 0x1f;
/* Each double register is equal to a pair of single-precision FP registers */
seed = MIPS_DOUBLEREG(reg) ? 3 : 1;
/* FP register starts at bit position 16 */
shift = MIPS_FPREG(reg) ? kMipsFPReg0 : 0;
/* Expand the double register id into single offset */
- shift += regId;
+ shift += reg_id;
return (seed << shift);
}
@@ -149,29 +149,29 @@
}
-void SetupTargetResourceMasks(CompilationUnit* cUnit, LIR* lir)
+void SetupTargetResourceMasks(CompilationUnit* cu, LIR* lir)
{
- DCHECK_EQ(cUnit->instructionSet, kMips);
+ DCHECK_EQ(cu->instruction_set, kMips);
// Mips-specific resource map setup here.
uint64_t flags = EncodingMap[lir->opcode].flags;
if (flags & REG_DEF_SP) {
- lir->defMask |= ENCODE_MIPS_REG_SP;
+ lir->def_mask |= ENCODE_MIPS_REG_SP;
}
if (flags & REG_USE_SP) {
- lir->useMask |= ENCODE_MIPS_REG_SP;
+ lir->use_mask |= ENCODE_MIPS_REG_SP;
}
if (flags & REG_DEF_LR) {
- lir->defMask |= ENCODE_MIPS_REG_LR;
+ lir->def_mask |= ENCODE_MIPS_REG_LR;
}
}
/* For dumping instructions */
#define MIPS_REG_COUNT 32
-static const char *mipsRegName[MIPS_REG_COUNT] = {
+static const char *mips_reg_name[MIPS_REG_COUNT] = {
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
@@ -182,23 +182,23 @@
* Interpret a format string and build a string no longer than size
* See format key in Assemble.c.
*/
-std::string BuildInsnString(const char *fmt, LIR *lir, unsigned char* baseAddr)
+std::string BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr)
{
std::string buf;
int i;
- const char *fmtEnd = &fmt[strlen(fmt)];
+ const char *fmt_end = &fmt[strlen(fmt)];
char tbuf[256];
char nc;
- while (fmt < fmtEnd) {
+ while (fmt < fmt_end) {
int operand;
if (*fmt == '!') {
fmt++;
- DCHECK_LT(fmt, fmtEnd);
+ DCHECK_LT(fmt, fmt_end);
nc = *fmt++;
if (nc=='!') {
strcpy(tbuf, "!");
} else {
- DCHECK_LT(fmt, fmtEnd);
+ DCHECK_LT(fmt, fmt_end);
DCHECK_LT(static_cast<unsigned>(nc-'0'), 4u);
operand = lir->operands[nc-'0'];
switch (*fmt++) {
@@ -233,7 +233,7 @@
sprintf(tbuf,"%d", operand*2);
break;
case 't':
- sprintf(tbuf,"0x%08x (L%p)", reinterpret_cast<uintptr_t>(baseAddr) + lir->offset + 4 +
+ sprintf(tbuf,"0x%08x (L%p)", reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4 +
(operand << 2), lir->target);
break;
case 'T':
@@ -243,7 +243,7 @@
int offset_1 = lir->operands[0];
int offset_2 = NEXT_LIR(lir)->operands[0];
uintptr_t target =
- (((reinterpret_cast<uintptr_t>(baseAddr) + lir->offset + 4) & ~3) +
+ (((reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4) & ~3) +
(offset_1 << 21 >> 9) + (offset_2 << 1)) & 0xfffffffc;
sprintf(tbuf, "%p", reinterpret_cast<void*>(target));
break;
@@ -255,7 +255,7 @@
break;
case 'r':
DCHECK(operand >= 0 && operand < MIPS_REG_COUNT);
- strcpy(tbuf, mipsRegName[operand]);
+ strcpy(tbuf, mips_reg_name[operand]);
break;
case 'N':
// Placeholder for delay slot handling
@@ -275,7 +275,7 @@
}
// FIXME: need to redo resource maps for MIPS - fix this at that time
-void DumpResourceMask(LIR *mipsLIR, uint64_t mask, const char *prefix)
+void DumpResourceMask(LIR *mips_lir, uint64_t mask, const char *prefix)
{
char buf[256];
buf[0] = 0;
@@ -300,9 +300,9 @@
strcat(buf, "fpcc ");
}
/* Memory bits */
- if (mipsLIR && (mask & ENCODE_DALVIK_REG)) {
- sprintf(buf + strlen(buf), "dr%d%s", mipsLIR->aliasInfo & 0xffff,
- (mipsLIR->aliasInfo & 0x80000000) ? "(+1)" : "");
+ if (mips_lir && (mask & ENCODE_DALVIK_REG)) {
+ sprintf(buf + strlen(buf), "dr%d%s", mips_lir->alias_info & 0xffff,
+ (mips_lir->alias_info & 0x80000000) ? "(+1)" : "");
}
if (mask & ENCODE_LITERAL) {
strcat(buf, "lit ");
@@ -321,15 +321,15 @@
}
/*
- * TUNING: is leaf? Can't just use "hasInvoke" to determine as some
+ * TUNING: is leaf? Can't just use "has_invoke" to determine as some
* instructions might call out to C/assembly helper functions. Until
* machinery is in place, always spill lr.
*/
-void AdjustSpillMask(CompilationUnit* cUnit)
+void AdjustSpillMask(CompilationUnit* cu)
{
- cUnit->coreSpillMask |= (1 << r_RA);
- cUnit->numCoreSpills++;
+ cu->core_spill_mask |= (1 << r_RA);
+ cu->num_core_spills++;
}
/*
@@ -338,40 +338,40 @@
* include any holes in the mask. Associate holes with
* Dalvik register INVALID_VREG (0xFFFFU).
*/
-void MarkPreservedSingle(CompilationUnit* cUnit, int sReg, int reg)
+void MarkPreservedSingle(CompilationUnit* cu, int s_reg, int reg)
{
LOG(FATAL) << "No support yet for promoted FP regs";
}
-void FlushRegWide(CompilationUnit* cUnit, int reg1, int reg2)
+void FlushRegWide(CompilationUnit* cu, int reg1, int reg2)
{
- RegisterInfo* info1 = GetRegInfo(cUnit, reg1);
- RegisterInfo* info2 = GetRegInfo(cUnit, reg2);
+ RegisterInfo* info1 = GetRegInfo(cu, reg1);
+ RegisterInfo* info2 = GetRegInfo(cu, reg2);
DCHECK(info1 && info2 && info1->pair && info2->pair &&
(info1->partner == info2->reg) &&
(info2->partner == info1->reg));
if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) {
- if (!(info1->isTemp && info2->isTemp)) {
- /* Should not happen. If it does, there's a problem in evalLoc */
+ if (!(info1->is_temp && info2->is_temp)) {
+ /* Should not happen. If it does, there's a problem in eval_loc */
LOG(FATAL) << "Long half-temp, half-promoted";
}
info1->dirty = false;
info2->dirty = false;
- if (SRegToVReg(cUnit, info2->sReg) < SRegToVReg(cUnit, info1->sReg))
+ if (SRegToVReg(cu, info2->s_reg) < SRegToVReg(cu, info1->s_reg))
info1 = info2;
- int vReg = SRegToVReg(cUnit, info1->sReg);
- StoreBaseDispWide(cUnit, rMIPS_SP, VRegOffset(cUnit, vReg), info1->reg, info1->partner);
+ int v_reg = SRegToVReg(cu, info1->s_reg);
+ StoreBaseDispWide(cu, rMIPS_SP, VRegOffset(cu, v_reg), info1->reg, info1->partner);
}
}
-void FlushReg(CompilationUnit* cUnit, int reg)
+void FlushReg(CompilationUnit* cu, int reg)
{
- RegisterInfo* info = GetRegInfo(cUnit, reg);
+ RegisterInfo* info = GetRegInfo(cu, reg);
if (info->live && info->dirty) {
info->dirty = false;
- int vReg = SRegToVReg(cUnit, info->sReg);
- StoreBaseDisp(cUnit, rMIPS_SP, VRegOffset(cUnit, vReg), reg, kWord);
+ int v_reg = SRegToVReg(cu, info->s_reg);
+ StoreBaseDisp(cu, rMIPS_SP, VRegOffset(cu, v_reg), reg, kWord);
}
}
@@ -381,85 +381,85 @@
}
/* Clobber all regs that might be used by an external C call */
-void ClobberCalleeSave(CompilationUnit *cUnit)
+void ClobberCalleeSave(CompilationUnit *cu)
{
- Clobber(cUnit, r_ZERO);
- Clobber(cUnit, r_AT);
- Clobber(cUnit, r_V0);
- Clobber(cUnit, r_V1);
- Clobber(cUnit, r_A0);
- Clobber(cUnit, r_A1);
- Clobber(cUnit, r_A2);
- Clobber(cUnit, r_A3);
- Clobber(cUnit, r_T0);
- Clobber(cUnit, r_T1);
- Clobber(cUnit, r_T2);
- Clobber(cUnit, r_T3);
- Clobber(cUnit, r_T4);
- Clobber(cUnit, r_T5);
- Clobber(cUnit, r_T6);
- Clobber(cUnit, r_T7);
- Clobber(cUnit, r_T8);
- Clobber(cUnit, r_T9);
- Clobber(cUnit, r_K0);
- Clobber(cUnit, r_K1);
- Clobber(cUnit, r_GP);
- Clobber(cUnit, r_FP);
- Clobber(cUnit, r_RA);
- Clobber(cUnit, r_F0);
- Clobber(cUnit, r_F1);
- Clobber(cUnit, r_F2);
- Clobber(cUnit, r_F3);
- Clobber(cUnit, r_F4);
- Clobber(cUnit, r_F5);
- Clobber(cUnit, r_F6);
- Clobber(cUnit, r_F7);
- Clobber(cUnit, r_F8);
- Clobber(cUnit, r_F9);
- Clobber(cUnit, r_F10);
- Clobber(cUnit, r_F11);
- Clobber(cUnit, r_F12);
- Clobber(cUnit, r_F13);
- Clobber(cUnit, r_F14);
- Clobber(cUnit, r_F15);
+ Clobber(cu, r_ZERO);
+ Clobber(cu, r_AT);
+ Clobber(cu, r_V0);
+ Clobber(cu, r_V1);
+ Clobber(cu, r_A0);
+ Clobber(cu, r_A1);
+ Clobber(cu, r_A2);
+ Clobber(cu, r_A3);
+ Clobber(cu, r_T0);
+ Clobber(cu, r_T1);
+ Clobber(cu, r_T2);
+ Clobber(cu, r_T3);
+ Clobber(cu, r_T4);
+ Clobber(cu, r_T5);
+ Clobber(cu, r_T6);
+ Clobber(cu, r_T7);
+ Clobber(cu, r_T8);
+ Clobber(cu, r_T9);
+ Clobber(cu, r_K0);
+ Clobber(cu, r_K1);
+ Clobber(cu, r_GP);
+ Clobber(cu, r_FP);
+ Clobber(cu, r_RA);
+ Clobber(cu, r_F0);
+ Clobber(cu, r_F1);
+ Clobber(cu, r_F2);
+ Clobber(cu, r_F3);
+ Clobber(cu, r_F4);
+ Clobber(cu, r_F5);
+ Clobber(cu, r_F6);
+ Clobber(cu, r_F7);
+ Clobber(cu, r_F8);
+ Clobber(cu, r_F9);
+ Clobber(cu, r_F10);
+ Clobber(cu, r_F11);
+ Clobber(cu, r_F12);
+ Clobber(cu, r_F13);
+ Clobber(cu, r_F14);
+ Clobber(cu, r_F15);
}
-RegLocation GetReturnWideAlt(CompilationUnit* cUnit)
+RegLocation GetReturnWideAlt(CompilationUnit* cu)
{
UNIMPLEMENTED(FATAL) << "No GetReturnWideAlt for MIPS";
RegLocation res = LocCReturnWide();
return res;
}
-RegLocation GetReturnAlt(CompilationUnit* cUnit)
+RegLocation GetReturnAlt(CompilationUnit* cu)
{
UNIMPLEMENTED(FATAL) << "No GetReturnAlt for MIPS";
RegLocation res = LocCReturn();
return res;
}
-RegisterInfo* GetRegInfo(CompilationUnit* cUnit, int reg)
+RegisterInfo* GetRegInfo(CompilationUnit* cu, int reg)
{
- return MIPS_FPREG(reg) ? &cUnit->regPool->FPRegs[reg & MIPS_FP_REG_MASK]
- : &cUnit->regPool->coreRegs[reg];
+ return MIPS_FPREG(reg) ? &cu->reg_pool->FPRegs[reg & MIPS_FP_REG_MASK]
+ : &cu->reg_pool->core_regs[reg];
}
/* To be used when explicitly managing register use */
-void LockCallTemps(CompilationUnit* cUnit)
+void LockCallTemps(CompilationUnit* cu)
{
- LockTemp(cUnit, rMIPS_ARG0);
- LockTemp(cUnit, rMIPS_ARG1);
- LockTemp(cUnit, rMIPS_ARG2);
- LockTemp(cUnit, rMIPS_ARG3);
+ LockTemp(cu, rMIPS_ARG0);
+ LockTemp(cu, rMIPS_ARG1);
+ LockTemp(cu, rMIPS_ARG2);
+ LockTemp(cu, rMIPS_ARG3);
}
/* To be used when explicitly managing register use */
-void FreeCallTemps(CompilationUnit* cUnit)
+void FreeCallTemps(CompilationUnit* cu)
{
- FreeTemp(cUnit, rMIPS_ARG0);
- FreeTemp(cUnit, rMIPS_ARG1);
- FreeTemp(cUnit, rMIPS_ARG2);
- FreeTemp(cUnit, rMIPS_ARG3);
+ FreeTemp(cu, rMIPS_ARG0);
+ FreeTemp(cu, rMIPS_ARG1);
+ FreeTemp(cu, rMIPS_ARG2);
+ FreeTemp(cu, rMIPS_ARG3);
}
/* Architecture-specific initializations and checks go here */
@@ -468,10 +468,10 @@
return true;
}
-void GenMemBarrier(CompilationUnit *cUnit, MemBarrierKind barrierKind)
+void GenMemBarrier(CompilationUnit *cu, MemBarrierKind barrier_kind)
{
#if ANDROID_SMP != 0
- NewLIR1(cUnit, kMipsSync, 0 /* Only stype currently supported */);
+ NewLIR1(cu, kMipsSync, 0 /* Only stype currently supported */);
#endif
}
@@ -479,103 +479,103 @@
* Alloc a pair of core registers, or a double. Low reg in low byte,
* high reg in next byte.
*/
-int AllocTypedTempPair(CompilationUnit *cUnit, bool fpHint,
- int regClass)
+int AllocTypedTempPair(CompilationUnit *cu, bool fp_hint,
+ int reg_class)
{
- int highReg;
- int lowReg;
+ int high_reg;
+ int low_reg;
int res = 0;
#ifdef __mips_hard_float
- if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg)) {
- lowReg = AllocTempDouble(cUnit);
- highReg = lowReg + 1;
- res = (lowReg & 0xff) | ((highReg & 0xff) << 8);
+ if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
+ low_reg = AllocTempDouble(cu);
+ high_reg = low_reg + 1;
+ res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
return res;
}
#endif
- lowReg = AllocTemp(cUnit);
- highReg = AllocTemp(cUnit);
- res = (lowReg & 0xff) | ((highReg & 0xff) << 8);
+ low_reg = AllocTemp(cu);
+ high_reg = AllocTemp(cu);
+ res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
return res;
}
-int AllocTypedTemp(CompilationUnit *cUnit, bool fpHint, int regClass)
+int AllocTypedTemp(CompilationUnit *cu, bool fp_hint, int reg_class)
{
#ifdef __mips_hard_float
- if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg))
+ if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg))
{
- return AllocTempFloat(cUnit);
+ return AllocTempFloat(cu);
}
#endif
- return AllocTemp(cUnit);
+ return AllocTemp(cu);
}
-void CompilerInitializeRegAlloc(CompilationUnit* cUnit)
+void CompilerInitializeRegAlloc(CompilationUnit* cu)
{
- int numRegs = sizeof(coreRegs)/sizeof(*coreRegs);
- int numReserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs);
- int numTemps = sizeof(coreTemps)/sizeof(*coreTemps);
+ int num_regs = sizeof(core_regs)/sizeof(*core_regs);
+ int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs);
+ int num_temps = sizeof(core_temps)/sizeof(*core_temps);
#ifdef __mips_hard_float
- int numFPRegs = sizeof(FpRegs)/sizeof(*FpRegs);
- int numFPTemps = sizeof(fpTemps)/sizeof(*fpTemps);
+ int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs);
+ int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps);
#else
- int numFPRegs = 0;
- int numFPTemps = 0;
+ int num_fp_regs = 0;
+ int num_fp_temps = 0;
#endif
RegisterPool *pool =
- static_cast<RegisterPool*>(NewMem(cUnit, sizeof(*pool), true, kAllocRegAlloc));
- cUnit->regPool = pool;
- pool->numCoreRegs = numRegs;
- pool->coreRegs = static_cast<RegisterInfo*>
- (NewMem(cUnit, numRegs * sizeof(*cUnit->regPool->coreRegs), true, kAllocRegAlloc));
- pool->numFPRegs = numFPRegs;
+ static_cast<RegisterPool*>(NewMem(cu, sizeof(*pool), true, kAllocRegAlloc));
+ cu->reg_pool = pool;
+ pool->num_core_regs = num_regs;
+ pool->core_regs = static_cast<RegisterInfo*>
+ (NewMem(cu, num_regs * sizeof(*cu->reg_pool->core_regs), true, kAllocRegAlloc));
+ pool->num_fp_regs = num_fp_regs;
pool->FPRegs = static_cast<RegisterInfo*>
- (NewMem(cUnit, numFPRegs * sizeof(*cUnit->regPool->FPRegs), true, kAllocRegAlloc));
- CompilerInitPool(pool->coreRegs, coreRegs, pool->numCoreRegs);
- CompilerInitPool(pool->FPRegs, FpRegs, pool->numFPRegs);
+ (NewMem(cu, num_fp_regs * sizeof(*cu->reg_pool->FPRegs), true, kAllocRegAlloc));
+ CompilerInitPool(pool->core_regs, core_regs, pool->num_core_regs);
+ CompilerInitPool(pool->FPRegs, FpRegs, pool->num_fp_regs);
// Keep special registers from being allocated
- for (int i = 0; i < numReserved; i++) {
+ for (int i = 0; i < num_reserved; i++) {
if (NO_SUSPEND && (ReservedRegs[i] == rMIPS_SUSPEND)) {
//To measure cost of suspend check
continue;
}
- MarkInUse(cUnit, ReservedRegs[i]);
+ MarkInUse(cu, ReservedRegs[i]);
}
// Mark temp regs - all others not in use can be used for promotion
- for (int i = 0; i < numTemps; i++) {
- MarkTemp(cUnit, coreTemps[i]);
+ for (int i = 0; i < num_temps; i++) {
+ MarkTemp(cu, core_temps[i]);
}
- for (int i = 0; i < numFPTemps; i++) {
- MarkTemp(cUnit, fpTemps[i]);
+ for (int i = 0; i < num_fp_temps; i++) {
+ MarkTemp(cu, fp_temps[i]);
}
// Construct the alias map.
- cUnit->phiAliasMap = static_cast<int*>
- (NewMem(cUnit, cUnit->numSSARegs * sizeof(cUnit->phiAliasMap[0]), false, kAllocDFInfo));
- for (int i = 0; i < cUnit->numSSARegs; i++) {
- cUnit->phiAliasMap[i] = i;
+ cu->phi_alias_map = static_cast<int*>
+ (NewMem(cu, cu->num_ssa_regs * sizeof(cu->phi_alias_map[0]), false, kAllocDFInfo));
+ for (int i = 0; i < cu->num_ssa_regs; i++) {
+ cu->phi_alias_map[i] = i;
}
- for (MIR* phi = cUnit->phiList; phi; phi = phi->meta.phiNext) {
- int defReg = phi->ssaRep->defs[0];
- for (int i = 0; i < phi->ssaRep->numUses; i++) {
- for (int j = 0; j < cUnit->numSSARegs; j++) {
- if (cUnit->phiAliasMap[j] == phi->ssaRep->uses[i]) {
- cUnit->phiAliasMap[j] = defReg;
+ for (MIR* phi = cu->phi_list; phi; phi = phi->meta.phi_next) {
+ int def_reg = phi->ssa_rep->defs[0];
+ for (int i = 0; i < phi->ssa_rep->num_uses; i++) {
+ for (int j = 0; j < cu->num_ssa_regs; j++) {
+ if (cu->phi_alias_map[j] == phi->ssa_rep->uses[i]) {
+ cu->phi_alias_map[j] = def_reg;
}
}
}
}
}
-void FreeRegLocTemps(CompilationUnit* cUnit, RegLocation rlKeep,
- RegLocation rlFree)
+void FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep,
+ RegLocation rl_free)
{
- if ((rlFree.lowReg != rlKeep.lowReg) && (rlFree.lowReg != rlKeep.highReg) &&
- (rlFree.highReg != rlKeep.lowReg) && (rlFree.highReg != rlKeep.highReg)) {
+ if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) &&
+ (rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) {
// No overlap, free both
- FreeTemp(cUnit, rlFree.lowReg);
- FreeTemp(cUnit, rlFree.highReg);
+ FreeTemp(cu, rl_free.low_reg);
+ FreeTemp(cu, rl_free.high_reg);
}
}
/*
@@ -584,42 +584,42 @@
* ensure that all branch instructions can be restarted if
* there is a trap in the shadow. Allocate a temp register.
*/
-int LoadHelper(CompilationUnit* cUnit, int offset)
+int LoadHelper(CompilationUnit* cu, int offset)
{
- LoadWordDisp(cUnit, rMIPS_SELF, offset, r_T9);
+ LoadWordDisp(cu, rMIPS_SELF, offset, r_T9);
return r_T9;
}
-void SpillCoreRegs(CompilationUnit* cUnit)
+void SpillCoreRegs(CompilationUnit* cu)
{
- if (cUnit->numCoreSpills == 0) {
+ if (cu->num_core_spills == 0) {
return;
}
- uint32_t mask = cUnit->coreSpillMask;
- int offset = cUnit->numCoreSpills * 4;
- OpRegImm(cUnit, kOpSub, rMIPS_SP, offset);
+ uint32_t mask = cu->core_spill_mask;
+ int offset = cu->num_core_spills * 4;
+ OpRegImm(cu, kOpSub, rMIPS_SP, offset);
for (int reg = 0; mask; mask >>= 1, reg++) {
if (mask & 0x1) {
offset -= 4;
- StoreWordDisp(cUnit, rMIPS_SP, offset, reg);
+ StoreWordDisp(cu, rMIPS_SP, offset, reg);
}
}
}
-void UnSpillCoreRegs(CompilationUnit* cUnit)
+void UnSpillCoreRegs(CompilationUnit* cu)
{
- if (cUnit->numCoreSpills == 0) {
+ if (cu->num_core_spills == 0) {
return;
}
- uint32_t mask = cUnit->coreSpillMask;
- int offset = cUnit->frameSize;
+ uint32_t mask = cu->core_spill_mask;
+ int offset = cu->frame_size;
for (int reg = 0; mask; mask >>= 1, reg++) {
if (mask & 0x1) {
offset -= 4;
- LoadWordDisp(cUnit, rMIPS_SP, offset, reg);
+ LoadWordDisp(cu, rMIPS_SP, offset, reg);
}
}
- OpRegImm(cUnit, kOpAdd, rMIPS_SP, cUnit->frameSize);
+ OpRegImm(cu, kOpAdd, rMIPS_SP, cu->frame_size);
}
bool BranchUnconditional(LIR* lir)
diff --git a/src/compiler/codegen/mips/utility_mips.cc b/src/compiler/codegen/mips/utility_mips.cc
index 011fc34..168b462 100644
--- a/src/compiler/codegen/mips/utility_mips.cc
+++ b/src/compiler/codegen/mips/utility_mips.cc
@@ -22,41 +22,41 @@
/* This file contains codegen for the MIPS32 ISA. */
-void GenBarrier(CompilationUnit *cUnit);
-void LoadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg);
-LIR *LoadWordDisp(CompilationUnit *cUnit, int rBase, int displacement,
- int rDest);
-LIR *StoreWordDisp(CompilationUnit *cUnit, int rBase,
- int displacement, int rSrc);
-LIR *LoadConstant(CompilationUnit *cUnit, int rDest, int value);
+void GenBarrier(CompilationUnit *cu);
+void LoadPair(CompilationUnit *cu, int base, int low_reg, int high_reg);
+LIR *LoadWordDisp(CompilationUnit *cu, int rBase, int displacement,
+ int r_dest);
+LIR *StoreWordDisp(CompilationUnit *cu, int rBase,
+ int displacement, int r_src);
+LIR *LoadConstant(CompilationUnit *cu, int r_dest, int value);
#ifdef __mips_hard_float
-LIR *FpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
+LIR *FpRegCopy(CompilationUnit *cu, int r_dest, int r_src)
{
int opcode;
/* must be both DOUBLE or both not DOUBLE */
- DCHECK_EQ(MIPS_DOUBLEREG(rDest),MIPS_DOUBLEREG(rSrc));
- if (MIPS_DOUBLEREG(rDest)) {
+ DCHECK_EQ(MIPS_DOUBLEREG(r_dest),MIPS_DOUBLEREG(r_src));
+ if (MIPS_DOUBLEREG(r_dest)) {
opcode = kMipsFmovd;
} else {
- if (MIPS_SINGLEREG(rDest)) {
- if (MIPS_SINGLEREG(rSrc)) {
+ if (MIPS_SINGLEREG(r_dest)) {
+ if (MIPS_SINGLEREG(r_src)) {
opcode = kMipsFmovs;
} else {
/* note the operands are swapped for the mtc1 instr */
- int tOpnd = rSrc;
- rSrc = rDest;
- rDest = tOpnd;
+ int t_opnd = r_src;
+ r_src = r_dest;
+ r_dest = t_opnd;
opcode = kMipsMtc1;
}
} else {
- DCHECK(MIPS_SINGLEREG(rSrc));
+ DCHECK(MIPS_SINGLEREG(r_src));
opcode = kMipsMfc1;
}
}
- LIR* res = RawLIR(cUnit, cUnit->currentDalvikOffset, opcode, rSrc, rDest);
- if (!(cUnit->disableOpt & (1 << kSafeOptimizations)) && rDest == rSrc) {
- res->flags.isNop = true;
+ LIR* res = RawLIR(cu, cu->current_dalvik_offset, opcode, r_src, r_dest);
+ if (!(cu->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
+ res->flags.is_nop = true;
}
return res;
}
@@ -68,54 +68,54 @@
* a high register, build constant into a low register and copy.
*
* No additional register clobbering operation performed. Use this version when
- * 1) rDest is freshly returned from AllocTemp or
+ * 1) r_dest is freshly returned from AllocTemp or
* 2) The codegen is under fixed register usage
*/
-LIR *LoadConstantNoClobber(CompilationUnit *cUnit, int rDest, int value)
+LIR *LoadConstantNoClobber(CompilationUnit *cu, int r_dest, int value)
{
LIR *res;
#ifdef __mips_hard_float
- int rDestSave = rDest;
- int isFpReg = MIPS_FPREG(rDest);
- if (isFpReg) {
- DCHECK(MIPS_SINGLEREG(rDest));
- rDest = AllocTemp(cUnit);
+ int r_dest_save = r_dest;
+ int is_fp_reg = MIPS_FPREG(r_dest);
+ if (is_fp_reg) {
+ DCHECK(MIPS_SINGLEREG(r_dest));
+ r_dest = AllocTemp(cu);
}
#endif
/* See if the value can be constructed cheaply */
if (value == 0) {
- res = NewLIR2(cUnit, kMipsMove, rDest, r_ZERO);
+ res = NewLIR2(cu, kMipsMove, r_dest, r_ZERO);
} else if ((value > 0) && (value <= 65535)) {
- res = NewLIR3(cUnit, kMipsOri, rDest, r_ZERO, value);
+ res = NewLIR3(cu, kMipsOri, r_dest, r_ZERO, value);
} else if ((value < 0) && (value >= -32768)) {
- res = NewLIR3(cUnit, kMipsAddiu, rDest, r_ZERO, value);
+ res = NewLIR3(cu, kMipsAddiu, r_dest, r_ZERO, value);
} else {
- res = NewLIR2(cUnit, kMipsLui, rDest, value>>16);
+ res = NewLIR2(cu, kMipsLui, r_dest, value>>16);
if (value & 0xffff)
- NewLIR3(cUnit, kMipsOri, rDest, rDest, value);
+ NewLIR3(cu, kMipsOri, r_dest, r_dest, value);
}
#ifdef __mips_hard_float
- if (isFpReg) {
- NewLIR2(cUnit, kMipsMtc1, rDest, rDestSave);
- FreeTemp(cUnit, rDest);
+ if (is_fp_reg) {
+ NewLIR2(cu, kMipsMtc1, r_dest, r_dest_save);
+ FreeTemp(cu, r_dest);
}
#endif
return res;
}
-LIR *OpBranchUnconditional(CompilationUnit *cUnit, OpKind op)
+LIR *OpBranchUnconditional(CompilationUnit *cu, OpKind op)
{
DCHECK_EQ(op, kOpUncondBr);
- return NewLIR1(cUnit, kMipsB, 0 /* offset to be patched */ );
+ return NewLIR1(cu, kMipsB, 0 /* offset to be patched */ );
}
-LIR *LoadMultiple(CompilationUnit *cUnit, int rBase, int rMask);
+LIR *LoadMultiple(CompilationUnit *cu, int rBase, int r_mask);
-LIR *OpReg(CompilationUnit *cUnit, OpKind op, int rDestSrc)
+LIR *OpReg(CompilationUnit *cu, OpKind op, int r_dest_src)
{
MipsOpCode opcode = kMipsNop;
switch (op) {
@@ -123,50 +123,50 @@
opcode = kMipsJalr;
break;
case kOpBx:
- return NewLIR1(cUnit, kMipsJr, rDestSrc);
+ return NewLIR1(cu, kMipsJr, r_dest_src);
break;
default:
LOG(FATAL) << "Bad case in OpReg";
}
- return NewLIR2(cUnit, opcode, r_RA, rDestSrc);
+ return NewLIR2(cu, opcode, r_RA, r_dest_src);
}
-LIR *OpRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
- int rSrc1, int value);
-LIR *OpRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
+LIR *OpRegRegImm(CompilationUnit *cu, OpKind op, int r_dest,
+ int r_src1, int value);
+LIR *OpRegImm(CompilationUnit *cu, OpKind op, int r_dest_src1,
int value)
{
LIR *res;
bool neg = (value < 0);
- int absValue = (neg) ? -value : value;
- bool shortForm = (absValue & 0xff) == absValue;
+ int abs_value = (neg) ? -value : value;
+ bool short_form = (abs_value & 0xff) == abs_value;
MipsOpCode opcode = kMipsNop;
switch (op) {
case kOpAdd:
- return OpRegRegImm(cUnit, op, rDestSrc1, rDestSrc1, value);
+ return OpRegRegImm(cu, op, r_dest_src1, r_dest_src1, value);
break;
case kOpSub:
- return OpRegRegImm(cUnit, op, rDestSrc1, rDestSrc1, value);
+ return OpRegRegImm(cu, op, r_dest_src1, r_dest_src1, value);
break;
default:
LOG(FATAL) << "Bad case in OpRegImm";
break;
}
- if (shortForm)
- res = NewLIR2(cUnit, opcode, rDestSrc1, absValue);
+ if (short_form)
+ res = NewLIR2(cu, opcode, r_dest_src1, abs_value);
else {
- int rScratch = AllocTemp(cUnit);
- res = LoadConstant(cUnit, rScratch, value);
+ int r_scratch = AllocTemp(cu);
+ res = LoadConstant(cu, r_scratch, value);
if (op == kOpCmp)
- NewLIR2(cUnit, opcode, rDestSrc1, rScratch);
+ NewLIR2(cu, opcode, r_dest_src1, r_scratch);
else
- NewLIR3(cUnit, opcode, rDestSrc1, rDestSrc1, rScratch);
+ NewLIR3(cu, opcode, r_dest_src1, r_dest_src1, r_scratch);
}
return res;
}
-LIR *OpRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
- int rSrc1, int rSrc2)
+LIR *OpRegRegReg(CompilationUnit *cu, OpKind op, int r_dest,
+ int r_src1, int r_src2)
{
MipsOpCode opcode = kMipsNop;
switch (op) {
@@ -205,15 +205,15 @@
LOG(FATAL) << "bad case in OpRegRegReg";
break;
}
- return NewLIR3(cUnit, opcode, rDest, rSrc1, rSrc2);
+ return NewLIR3(cu, opcode, r_dest, r_src1, r_src2);
}
-LIR *OpRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
- int rSrc1, int value)
+LIR *OpRegRegImm(CompilationUnit *cu, OpKind op, int r_dest,
+ int r_src1, int value)
{
LIR *res;
MipsOpCode opcode = kMipsNop;
- bool shortForm = true;
+ bool short_form = true;
switch (op) {
case kOpAdd:
@@ -221,7 +221,7 @@
opcode = kMipsAddiu;
}
else {
- shortForm = false;
+ short_form = false;
opcode = kMipsAddu;
}
break;
@@ -231,7 +231,7 @@
opcode = kMipsAddiu;
}
else {
- shortForm = false;
+ short_form = false;
opcode = kMipsSubu;
}
break;
@@ -252,7 +252,7 @@
opcode = kMipsAndi;
}
else {
- shortForm = false;
+ short_form = false;
opcode = kMipsAnd;
}
break;
@@ -261,7 +261,7 @@
opcode = kMipsOri;
}
else {
- shortForm = false;
+ short_form = false;
opcode = kMipsOr;
}
break;
@@ -270,12 +270,12 @@
opcode = kMipsXori;
}
else {
- shortForm = false;
+ short_form = false;
opcode = kMipsXor;
}
break;
case kOpMul:
- shortForm = false;
+ short_form = false;
opcode = kMipsMul;
break;
default:
@@ -283,22 +283,22 @@
break;
}
- if (shortForm)
- res = NewLIR3(cUnit, opcode, rDest, rSrc1, value);
+ if (short_form)
+ res = NewLIR3(cu, opcode, r_dest, r_src1, value);
else {
- if (rDest != rSrc1) {
- res = LoadConstant(cUnit, rDest, value);
- NewLIR3(cUnit, opcode, rDest, rSrc1, rDest);
+ if (r_dest != r_src1) {
+ res = LoadConstant(cu, r_dest, value);
+ NewLIR3(cu, opcode, r_dest, r_src1, r_dest);
} else {
- int rScratch = AllocTemp(cUnit);
- res = LoadConstant(cUnit, rScratch, value);
- NewLIR3(cUnit, opcode, rDest, rSrc1, rScratch);
+ int r_scratch = AllocTemp(cu);
+ res = LoadConstant(cu, r_scratch, value);
+ NewLIR3(cu, opcode, r_dest, r_src1, r_scratch);
}
}
return res;
}
-LIR *OpRegReg(CompilationUnit *cUnit, OpKind op, int rDestSrc1, int rSrc2)
+LIR *OpRegReg(CompilationUnit *cu, OpKind op, int r_dest_src1, int r_src2)
{
MipsOpCode opcode = kMipsNop;
LIR *res;
@@ -307,62 +307,62 @@
opcode = kMipsMove;
break;
case kOpMvn:
- return NewLIR3(cUnit, kMipsNor, rDestSrc1, rSrc2, r_ZERO);
+ return NewLIR3(cu, kMipsNor, r_dest_src1, r_src2, r_ZERO);
case kOpNeg:
- return NewLIR3(cUnit, kMipsSubu, rDestSrc1, r_ZERO, rSrc2);
+ return NewLIR3(cu, kMipsSubu, r_dest_src1, r_ZERO, r_src2);
case kOpAdd:
case kOpAnd:
case kOpMul:
case kOpOr:
case kOpSub:
case kOpXor:
- return OpRegRegReg(cUnit, op, rDestSrc1, rDestSrc1, rSrc2);
+ return OpRegRegReg(cu, op, r_dest_src1, r_dest_src1, r_src2);
case kOp2Byte:
#if __mips_isa_rev>=2
- res = NewLIR2(cUnit, kMipsSeb, rDestSrc1, rSrc2);
+ res = NewLIR2(cu, kMipsSeb, r_dest_src1, r_src2);
#else
- res = OpRegRegImm(cUnit, kOpLsl, rDestSrc1, rSrc2, 24);
- OpRegRegImm(cUnit, kOpAsr, rDestSrc1, rDestSrc1, 24);
+ res = OpRegRegImm(cu, kOpLsl, r_dest_src1, r_src2, 24);
+ OpRegRegImm(cu, kOpAsr, r_dest_src1, r_dest_src1, 24);
#endif
return res;
case kOp2Short:
#if __mips_isa_rev>=2
- res = NewLIR2(cUnit, kMipsSeh, rDestSrc1, rSrc2);
+ res = NewLIR2(cu, kMipsSeh, r_dest_src1, r_src2);
#else
- res = OpRegRegImm(cUnit, kOpLsl, rDestSrc1, rSrc2, 16);
- OpRegRegImm(cUnit, kOpAsr, rDestSrc1, rDestSrc1, 16);
+ res = OpRegRegImm(cu, kOpLsl, r_dest_src1, r_src2, 16);
+ OpRegRegImm(cu, kOpAsr, r_dest_src1, r_dest_src1, 16);
#endif
return res;
case kOp2Char:
- return NewLIR3(cUnit, kMipsAndi, rDestSrc1, rSrc2, 0xFFFF);
+ return NewLIR3(cu, kMipsAndi, r_dest_src1, r_src2, 0xFFFF);
default:
LOG(FATAL) << "Bad case in OpRegReg";
break;
}
- return NewLIR2(cUnit, opcode, rDestSrc1, rSrc2);
+ return NewLIR2(cu, opcode, r_dest_src1, r_src2);
}
-LIR *LoadConstantValueWide(CompilationUnit *cUnit, int rDestLo,
- int rDestHi, int valLo, int valHi)
+LIR *LoadConstantValueWide(CompilationUnit *cu, int r_dest_lo,
+ int r_dest_hi, int val_lo, int val_hi)
{
LIR *res;
- res = LoadConstantNoClobber(cUnit, rDestLo, valLo);
- LoadConstantNoClobber(cUnit, rDestHi, valHi);
+ res = LoadConstantNoClobber(cu, r_dest_lo, val_lo);
+ LoadConstantNoClobber(cu, r_dest_hi, val_hi);
return res;
}
/* Load value from base + scaled index. */
-LIR *LoadBaseIndexed(CompilationUnit *cUnit, int rBase,
- int rIndex, int rDest, int scale, OpSize size)
+LIR *LoadBaseIndexed(CompilationUnit *cu, int rBase,
+ int r_index, int r_dest, int scale, OpSize size)
{
LIR *first = NULL;
LIR *res;
MipsOpCode opcode = kMipsNop;
- int tReg = AllocTemp(cUnit);
+ int t_reg = AllocTemp(cu);
#ifdef __mips_hard_float
- if (MIPS_FPREG(rDest)) {
- DCHECK(MIPS_SINGLEREG(rDest));
+ if (MIPS_FPREG(r_dest)) {
+ DCHECK(MIPS_SINGLEREG(r_dest));
DCHECK((size == kWord) || (size == kSingle));
size = kSingle;
} else {
@@ -372,10 +372,10 @@
#endif
if (!scale) {
- first = NewLIR3(cUnit, kMipsAddu, tReg , rBase, rIndex);
+ first = NewLIR3(cu, kMipsAddu, t_reg , rBase, r_index);
} else {
- first = OpRegRegImm(cUnit, kOpLsl, tReg, rIndex, scale);
- NewLIR3(cUnit, kMipsAddu, tReg , rBase, tReg);
+ first = OpRegRegImm(cu, kOpLsl, t_reg, r_index, scale);
+ NewLIR3(cu, kMipsAddu, t_reg , rBase, t_reg);
}
switch (size) {
@@ -403,23 +403,23 @@
LOG(FATAL) << "Bad case in LoadBaseIndexed";
}
- res = NewLIR3(cUnit, opcode, rDest, 0, tReg);
- FreeTemp(cUnit, tReg);
+ res = NewLIR3(cu, opcode, r_dest, 0, t_reg);
+ FreeTemp(cu, t_reg);
return (first) ? first : res;
}
/* store value base base + scaled index. */
-LIR *StoreBaseIndexed(CompilationUnit *cUnit, int rBase,
- int rIndex, int rSrc, int scale, OpSize size)
+LIR *StoreBaseIndexed(CompilationUnit *cu, int rBase,
+ int r_index, int r_src, int scale, OpSize size)
{
LIR *first = NULL;
MipsOpCode opcode = kMipsNop;
- int rNewIndex = rIndex;
- int tReg = AllocTemp(cUnit);
+ int r_new_index = r_index;
+ int t_reg = AllocTemp(cu);
#ifdef __mips_hard_float
- if (MIPS_FPREG(rSrc)) {
- DCHECK(MIPS_SINGLEREG(rSrc));
+ if (MIPS_FPREG(r_src)) {
+ DCHECK(MIPS_SINGLEREG(r_src));
DCHECK((size == kWord) || (size == kSingle));
size = kSingle;
} else {
@@ -429,10 +429,10 @@
#endif
if (!scale) {
- first = NewLIR3(cUnit, kMipsAddu, tReg , rBase, rIndex);
+ first = NewLIR3(cu, kMipsAddu, t_reg , rBase, r_index);
} else {
- first = OpRegRegImm(cUnit, kOpLsl, tReg, rIndex, scale);
- NewLIR3(cUnit, kMipsAddu, tReg , rBase, tReg);
+ first = OpRegRegImm(cu, kOpLsl, t_reg, r_index, scale);
+ NewLIR3(cu, kMipsAddu, t_reg , rBase, t_reg);
}
switch (size) {
@@ -455,61 +455,61 @@
default:
LOG(FATAL) << "Bad case in StoreBaseIndexed";
}
- NewLIR3(cUnit, opcode, rSrc, 0, tReg);
- FreeTemp(cUnit, rNewIndex);
+ NewLIR3(cu, opcode, r_src, 0, t_reg);
+ FreeTemp(cu, r_new_index);
return first;
}
-LIR *LoadMultiple(CompilationUnit *cUnit, int rBase, int rMask)
+LIR *LoadMultiple(CompilationUnit *cu, int rBase, int r_mask)
{
int i;
- int loadCnt = 0;
+ int load_cnt = 0;
LIR *res = NULL ;
- GenBarrier(cUnit);
+ GenBarrier(cu);
- for (i = 0; i < 8; i++, rMask >>= 1) {
- if (rMask & 0x1) { /* map r0 to MIPS r_A0 */
- NewLIR3(cUnit, kMipsLw, i+r_A0, loadCnt*4, rBase);
- loadCnt++;
+ for (i = 0; i < 8; i++, r_mask >>= 1) {
+ if (r_mask & 0x1) { /* map r0 to MIPS r_A0 */
+ NewLIR3(cu, kMipsLw, i+r_A0, load_cnt*4, rBase);
+ load_cnt++;
}
}
- if (loadCnt) {/* increment after */
- NewLIR3(cUnit, kMipsAddiu, rBase, rBase, loadCnt*4);
+ if (load_cnt) {/* increment after */
+ NewLIR3(cu, kMipsAddiu, rBase, rBase, load_cnt*4);
}
- GenBarrier(cUnit);
+ GenBarrier(cu);
return res; /* NULL always returned which should be ok since no callers use it */
}
-LIR *StoreMultiple(CompilationUnit *cUnit, int rBase, int rMask)
+LIR *StoreMultiple(CompilationUnit *cu, int rBase, int r_mask)
{
int i;
- int storeCnt = 0;
+ int store_cnt = 0;
LIR *res = NULL ;
- GenBarrier(cUnit);
+ GenBarrier(cu);
- for (i = 0; i < 8; i++, rMask >>= 1) {
- if (rMask & 0x1) { /* map r0 to MIPS r_A0 */
- NewLIR3(cUnit, kMipsSw, i+r_A0, storeCnt*4, rBase);
- storeCnt++;
+ for (i = 0; i < 8; i++, r_mask >>= 1) {
+ if (r_mask & 0x1) { /* map r0 to MIPS r_A0 */
+ NewLIR3(cu, kMipsSw, i+r_A0, store_cnt*4, rBase);
+ store_cnt++;
}
}
- if (storeCnt) { /* increment after */
- NewLIR3(cUnit, kMipsAddiu, rBase, rBase, storeCnt*4);
+ if (store_cnt) { /* increment after */
+ NewLIR3(cu, kMipsAddiu, rBase, rBase, store_cnt*4);
}
- GenBarrier(cUnit);
+ GenBarrier(cu);
return res; /* NULL always returned which should be ok since no callers use it */
}
-LIR *LoadBaseDispBody(CompilationUnit *cUnit, int rBase,
- int displacement, int rDest, int rDestHi,
- OpSize size, int sReg)
+LIR *LoadBaseDispBody(CompilationUnit *cu, int rBase,
+ int displacement, int r_dest, int r_dest_hi,
+ OpSize size, int s_reg)
/*
* Load value from base + displacement. Optionally perform null check
- * on base (which must have an associated sReg and MIR). If not
+ * on base (which must have an associated s_reg and MIR). If not
* performing null check, incoming MIR can be null. IMPORTANT: this
* code must not allocate any new temps. If a new register is needed
* and base and dest are the same, spill some other register to
@@ -520,7 +520,7 @@
LIR *load = NULL;
LIR *load2 = NULL;
MipsOpCode opcode = kMipsNop;
- bool shortForm = IS_SIMM16(displacement);
+ bool short_form = IS_SIMM16(displacement);
bool pair = false;
switch (size) {
@@ -529,27 +529,27 @@
pair = true;
opcode = kMipsLw;
#ifdef __mips_hard_float
- if (MIPS_FPREG(rDest)) {
+ if (MIPS_FPREG(r_dest)) {
opcode = kMipsFlwc1;
- if (MIPS_DOUBLEREG(rDest)) {
- rDest = rDest - MIPS_FP_DOUBLE;
+ if (MIPS_DOUBLEREG(r_dest)) {
+ r_dest = r_dest - MIPS_FP_DOUBLE;
} else {
- DCHECK(MIPS_FPREG(rDestHi));
- DCHECK(rDest == (rDestHi - 1));
+ DCHECK(MIPS_FPREG(r_dest_hi));
+ DCHECK(r_dest == (r_dest_hi - 1));
}
- rDestHi = rDest + 1;
+ r_dest_hi = r_dest + 1;
}
#endif
- shortForm = IS_SIMM16_2WORD(displacement);
+ short_form = IS_SIMM16_2WORD(displacement);
DCHECK_EQ((displacement & 0x3), 0);
break;
case kWord:
case kSingle:
opcode = kMipsLw;
#ifdef __mips_hard_float
- if (MIPS_FPREG(rDest)) {
+ if (MIPS_FPREG(r_dest)) {
opcode = kMipsFlwc1;
- DCHECK(MIPS_SINGLEREG(rDest));
+ DCHECK(MIPS_SINGLEREG(r_dest));
}
#endif
DCHECK_EQ((displacement & 0x3), 0);
@@ -572,65 +572,65 @@
LOG(FATAL) << "Bad case in LoadBaseIndexedBody";
}
- if (shortForm) {
+ if (short_form) {
if (!pair) {
- load = res = NewLIR3(cUnit, opcode, rDest, displacement, rBase);
+ load = res = NewLIR3(cu, opcode, r_dest, displacement, rBase);
} else {
- load = res = NewLIR3(cUnit, opcode, rDest,
+ load = res = NewLIR3(cu, opcode, r_dest,
displacement + LOWORD_OFFSET, rBase);
- load2 = NewLIR3(cUnit, opcode, rDestHi,
+ load2 = NewLIR3(cu, opcode, r_dest_hi,
displacement + HIWORD_OFFSET, rBase);
}
} else {
if (pair) {
- int rTmp = AllocFreeTemp(cUnit);
- res = OpRegRegImm(cUnit, kOpAdd, rTmp, rBase, displacement);
- load = NewLIR3(cUnit, opcode, rDest, LOWORD_OFFSET, rTmp);
- load2 = NewLIR3(cUnit, opcode, rDestHi, HIWORD_OFFSET, rTmp);
- FreeTemp(cUnit, rTmp);
+ int r_tmp = AllocFreeTemp(cu);
+ res = OpRegRegImm(cu, kOpAdd, r_tmp, rBase, displacement);
+ load = NewLIR3(cu, opcode, r_dest, LOWORD_OFFSET, r_tmp);
+ load2 = NewLIR3(cu, opcode, r_dest_hi, HIWORD_OFFSET, r_tmp);
+ FreeTemp(cu, r_tmp);
} else {
- int rTmp = (rBase == rDest) ? AllocFreeTemp(cUnit) : rDest;
- res = OpRegRegImm(cUnit, kOpAdd, rTmp, rBase, displacement);
- load = NewLIR3(cUnit, opcode, rDest, 0, rTmp);
- if (rTmp != rDest)
- FreeTemp(cUnit, rTmp);
+ int r_tmp = (rBase == r_dest) ? AllocFreeTemp(cu) : r_dest;
+ res = OpRegRegImm(cu, kOpAdd, r_tmp, rBase, displacement);
+ load = NewLIR3(cu, opcode, r_dest, 0, r_tmp);
+ if (r_tmp != r_dest)
+ FreeTemp(cu, r_tmp);
}
}
if (rBase == rMIPS_SP) {
AnnotateDalvikRegAccess(load,
(displacement + (pair ? LOWORD_OFFSET : 0)) >> 2,
- true /* isLoad */, pair /* is64bit */);
+ true /* is_load */, pair /* is64bit */);
if (pair) {
AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2,
- true /* isLoad */, pair /* is64bit */);
+ true /* is_load */, pair /* is64bit */);
}
}
return load;
}
-LIR *LoadBaseDisp(CompilationUnit *cUnit, int rBase,
- int displacement, int rDest, OpSize size, int sReg)
+LIR *LoadBaseDisp(CompilationUnit *cu, int rBase,
+ int displacement, int r_dest, OpSize size, int s_reg)
{
- return LoadBaseDispBody(cUnit, rBase, displacement, rDest, -1,
- size, sReg);
+ return LoadBaseDispBody(cu, rBase, displacement, r_dest, -1,
+ size, s_reg);
}
-LIR *LoadBaseDispWide(CompilationUnit *cUnit, int rBase,
- int displacement, int rDestLo, int rDestHi, int sReg)
+LIR *LoadBaseDispWide(CompilationUnit *cu, int rBase,
+ int displacement, int r_dest_lo, int r_dest_hi, int s_reg)
{
- return LoadBaseDispBody(cUnit, rBase, displacement, rDestLo, rDestHi,
- kLong, sReg);
+ return LoadBaseDispBody(cu, rBase, displacement, r_dest_lo, r_dest_hi,
+ kLong, s_reg);
}
-LIR *StoreBaseDispBody(CompilationUnit *cUnit, int rBase,
- int displacement, int rSrc, int rSrcHi, OpSize size)
+LIR *StoreBaseDispBody(CompilationUnit *cu, int rBase,
+ int displacement, int r_src, int r_src_hi, OpSize size)
{
LIR *res;
LIR *store = NULL;
LIR *store2 = NULL;
MipsOpCode opcode = kMipsNop;
- bool shortForm = IS_SIMM16(displacement);
+ bool short_form = IS_SIMM16(displacement);
bool pair = false;
switch (size) {
@@ -639,27 +639,27 @@
pair = true;
opcode = kMipsSw;
#ifdef __mips_hard_float
- if (MIPS_FPREG(rSrc)) {
+ if (MIPS_FPREG(r_src)) {
opcode = kMipsFswc1;
- if (MIPS_DOUBLEREG(rSrc)) {
- rSrc = rSrc - MIPS_FP_DOUBLE;
+ if (MIPS_DOUBLEREG(r_src)) {
+ r_src = r_src - MIPS_FP_DOUBLE;
} else {
- DCHECK(MIPS_FPREG(rSrcHi));
- DCHECK_EQ(rSrc, (rSrcHi - 1));
+ DCHECK(MIPS_FPREG(r_src_hi));
+ DCHECK_EQ(r_src, (r_src_hi - 1));
}
- rSrcHi = rSrc + 1;
+ r_src_hi = r_src + 1;
}
#endif
- shortForm = IS_SIMM16_2WORD(displacement);
+ short_form = IS_SIMM16_2WORD(displacement);
DCHECK_EQ((displacement & 0x3), 0);
break;
case kWord:
case kSingle:
opcode = kMipsSw;
#ifdef __mips_hard_float
- if (MIPS_FPREG(rSrc)) {
+ if (MIPS_FPREG(r_src)) {
opcode = kMipsFswc1;
- DCHECK(MIPS_SINGLEREG(rSrc));
+ DCHECK(MIPS_SINGLEREG(r_src));
}
#endif
DCHECK_EQ((displacement & 0x3), 0);
@@ -677,95 +677,95 @@
LOG(FATAL) << "Bad case in StoreBaseIndexedBody";
}
- if (shortForm) {
+ if (short_form) {
if (!pair) {
- store = res = NewLIR3(cUnit, opcode, rSrc, displacement, rBase);
+ store = res = NewLIR3(cu, opcode, r_src, displacement, rBase);
} else {
- store = res = NewLIR3(cUnit, opcode, rSrc, displacement + LOWORD_OFFSET,
+ store = res = NewLIR3(cu, opcode, r_src, displacement + LOWORD_OFFSET,
rBase);
- store2 = NewLIR3(cUnit, opcode, rSrcHi, displacement + HIWORD_OFFSET,
+ store2 = NewLIR3(cu, opcode, r_src_hi, displacement + HIWORD_OFFSET,
rBase);
}
} else {
- int rScratch = AllocTemp(cUnit);
- res = OpRegRegImm(cUnit, kOpAdd, rScratch, rBase, displacement);
+ int r_scratch = AllocTemp(cu);
+ res = OpRegRegImm(cu, kOpAdd, r_scratch, rBase, displacement);
if (!pair) {
- store = NewLIR3(cUnit, opcode, rSrc, 0, rScratch);
+ store = NewLIR3(cu, opcode, r_src, 0, r_scratch);
} else {
- store = NewLIR3(cUnit, opcode, rSrc, LOWORD_OFFSET, rScratch);
- store2 = NewLIR3(cUnit, opcode, rSrcHi, HIWORD_OFFSET, rScratch);
+ store = NewLIR3(cu, opcode, r_src, LOWORD_OFFSET, r_scratch);
+ store2 = NewLIR3(cu, opcode, r_src_hi, HIWORD_OFFSET, r_scratch);
}
- FreeTemp(cUnit, rScratch);
+ FreeTemp(cu, r_scratch);
}
if (rBase == rMIPS_SP) {
AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0))
- >> 2, false /* isLoad */, pair /* is64bit */);
+ >> 2, false /* is_load */, pair /* is64bit */);
if (pair) {
AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2,
- false /* isLoad */, pair /* is64bit */);
+ false /* is_load */, pair /* is64bit */);
}
}
return res;
}
-LIR *StoreBaseDisp(CompilationUnit *cUnit, int rBase,
- int displacement, int rSrc, OpSize size)
+LIR *StoreBaseDisp(CompilationUnit *cu, int rBase,
+ int displacement, int r_src, OpSize size)
{
- return StoreBaseDispBody(cUnit, rBase, displacement, rSrc, -1, size);
+ return StoreBaseDispBody(cu, rBase, displacement, r_src, -1, size);
}
-LIR *StoreBaseDispWide(CompilationUnit *cUnit, int rBase,
- int displacement, int rSrcLo, int rSrcHi)
+LIR *StoreBaseDispWide(CompilationUnit *cu, int rBase,
+ int displacement, int r_src_lo, int r_src_hi)
{
- return StoreBaseDispBody(cUnit, rBase, displacement, rSrcLo, rSrcHi, kLong);
+ return StoreBaseDispBody(cu, rBase, displacement, r_src_lo, r_src_hi, kLong);
}
-void LoadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg)
+void LoadPair(CompilationUnit *cu, int base, int low_reg, int high_reg)
{
- LoadWordDisp(cUnit, base, LOWORD_OFFSET , lowReg);
- LoadWordDisp(cUnit, base, HIWORD_OFFSET , highReg);
+ LoadWordDisp(cu, base, LOWORD_OFFSET , low_reg);
+ LoadWordDisp(cu, base, HIWORD_OFFSET , high_reg);
}
-LIR* OpThreadMem(CompilationUnit* cUnit, OpKind op, int threadOffset)
+LIR* OpThreadMem(CompilationUnit* cu, OpKind op, int thread_offset)
{
LOG(FATAL) << "Unexpected use of OpThreadMem for MIPS";
return NULL;
}
-LIR* OpMem(CompilationUnit* cUnit, OpKind op, int rBase, int disp)
+LIR* OpMem(CompilationUnit* cu, OpKind op, int rBase, int disp)
{
LOG(FATAL) << "Unexpected use of OpMem for MIPS";
return NULL;
}
-LIR* StoreBaseIndexedDisp(CompilationUnit *cUnit,
- int rBase, int rIndex, int scale, int displacement,
- int rSrc, int rSrcHi,
- OpSize size, int sReg)
+LIR* StoreBaseIndexedDisp(CompilationUnit *cu,
+ int rBase, int r_index, int scale, int displacement,
+ int r_src, int r_src_hi,
+ OpSize size, int s_reg)
{
LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for MIPS";
return NULL;
}
-LIR* OpRegMem(CompilationUnit *cUnit, OpKind op, int rDest, int rBase,
+LIR* OpRegMem(CompilationUnit *cu, OpKind op, int r_dest, int rBase,
int offset)
{
LOG(FATAL) << "Unexpected use of OpRegMem for MIPS";
return NULL;
}
-LIR* LoadBaseIndexedDisp(CompilationUnit *cUnit,
- int rBase, int rIndex, int scale, int displacement,
- int rDest, int rDestHi,
- OpSize size, int sReg)
+LIR* LoadBaseIndexedDisp(CompilationUnit *cu,
+ int rBase, int r_index, int scale, int displacement,
+ int r_dest, int r_dest_hi,
+ OpSize size, int s_reg)
{
LOG(FATAL) << "Unexpected use of LoadBaseIndexedDisp for MIPS";
return NULL;
}
-LIR* OpCondBranch(CompilationUnit* cUnit, ConditionCode cc, LIR* target)
+LIR* OpCondBranch(CompilationUnit* cu, ConditionCode cc, LIR* target)
{
LOG(FATAL) << "Unexpected use of OpCondBranch for MIPS";
return NULL;