Redo x86 int arithmetic
Make Mir2Lir::GenArithOpInt virtual, and implement an x86 version of it
to allow use of memory operands and knowledge of the fact that x86 has
(mostly) two operand instructions. Remove x86 specific code from the
generic version.
Add StoreFinalValue (matches StoreFinalValueWide) to handle the non-wide
cases. Add some x86 helper routines to simplify generation.
Change-Id: I6c13689c6da981f2570ab5af7a97f9816108b7ae
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
diff --git a/compiler/dex/quick/x86/assemble_x86.cc b/compiler/dex/quick/x86/assemble_x86.cc
index c29d6c4..916bc7a 100644
--- a/compiler/dex/quick/x86/assemble_x86.cc
+++ b/compiler/dex/quick/x86/assemble_x86.cc
@@ -863,6 +863,20 @@
DCHECK_EQ(0, entry->skeleton.immediate_bytes);
}
+void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base,
+ int displacement, uint8_t cl) {
+ DCHECK_EQ(cl, static_cast<uint8_t>(rCX));
+ EmitPrefix(entry);
+ code_buffer_.push_back(entry->skeleton.opcode);
+ DCHECK_NE(0x0F, entry->skeleton.opcode);
+ DCHECK_EQ(0, entry->skeleton.extra_opcode1);
+ DCHECK_EQ(0, entry->skeleton.extra_opcode2);
+ DCHECK_LT(base, 8);
+ EmitModrmDisp(entry->skeleton.modrm_opcode, base, displacement);
+ DCHECK_EQ(0, entry->skeleton.ax_opcode);
+ DCHECK_EQ(0, entry->skeleton.immediate_bytes);
+}
+
void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) {
if (entry->skeleton.prefix1 != 0) {
code_buffer_.push_back(entry->skeleton.prefix1);
@@ -1230,6 +1244,9 @@
case kShiftRegCl: // lir operands - 0: reg, 1: cl
EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);
break;
+ case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl
+ EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
+ break;
case kRegCond: // lir operands - 0: reg, 1: condition
EmitRegCond(entry, lir->operands[0], lir->operands[1]);
break;
diff --git a/compiler/dex/quick/x86/codegen_x86.h b/compiler/dex/quick/x86/codegen_x86.h
index f054d82..a864117 100644
--- a/compiler/dex/quick/x86/codegen_x86.h
+++ b/compiler/dex/quick/x86/codegen_x86.h
@@ -204,6 +204,8 @@
LIR* OpRegCopyNoInsert(int r_dest, int r_src);
LIR* OpRegImm(OpKind op, int r_dest_src1, int value);
LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset);
+ LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value);
+ LIR* OpRegMem(OpKind op, int r_dest, RegLocation value);
LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2);
LIR* OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src);
LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value);
@@ -231,6 +233,16 @@
int AllocTempDouble();
void ResetDefLocWide(RegLocation rl);
+ /*
+ * @brief x86 specific codegen for int operations.
+ * @param opcode Operation to perform.
+ * @param rl_dest Destination for the result.
+ * @param rl_lhs Left hand operand.
+ * @param rl_rhs Right hand operand.
+ */
+ void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest,
+ RegLocation rl_lhs, RegLocation rl_rhs);
+
private:
void EmitPrefix(const X86EncodingMap* entry);
void EmitOpcode(const X86EncodingMap* entry);
@@ -260,6 +272,7 @@
void EmitThreadImm(const X86EncodingMap* entry, int disp, int imm);
void EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
void EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
+ void EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base, int displacement, uint8_t cl);
void EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl);
void EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition);
@@ -366,6 +379,7 @@
* @param val Constant multiplier.
*/
void GenImulRegImm(int dest, int src, int val);
+
/*
* Generate an imul of a memory location by a constant or a better sequence.
* @param dest Destination Register.
@@ -386,6 +400,13 @@
*/
LIR* OpCmpMemImmBranch(ConditionCode cond, int temp_reg, int base_reg,
int offset, int check_value, LIR* target);
+ /*
+ * Can this operation be using core registers without temporaries?
+ * @param rl_lhs Left hand operand.
+ * @param rl_rhs Right hand operand.
+ * @returns 'true' if the operation can proceed without needing temporary regs.
+ */
+ bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs);
};
} // namespace art
diff --git a/compiler/dex/quick/x86/int_x86.cc b/compiler/dex/quick/x86/int_x86.cc
index e458e5f..a567a8a 100644
--- a/compiler/dex/quick/x86/int_x86.cc
+++ b/compiler/dex/quick/x86/int_x86.cc
@@ -1717,4 +1717,234 @@
StoreValue(rl_dest, rl_result);
}
+void X86Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest,
+ RegLocation rl_lhs, RegLocation rl_rhs) {
+ OpKind op = kOpBkpt;
+ bool is_div_rem = false;
+ bool unary = false;
+ bool shift_op = false;
+ bool is_two_addr = false;
+ RegLocation rl_result;
+ switch (opcode) {
+ case Instruction::NEG_INT:
+ op = kOpNeg;
+ unary = true;
+ break;
+ case Instruction::NOT_INT:
+ op = kOpMvn;
+ unary = true;
+ break;
+ case Instruction::ADD_INT_2ADDR:
+ is_two_addr = true;
+ // Fallthrough
+ case Instruction::ADD_INT:
+ op = kOpAdd;
+ break;
+ case Instruction::SUB_INT_2ADDR:
+ is_two_addr = true;
+ // Fallthrough
+ case Instruction::SUB_INT:
+ op = kOpSub;
+ break;
+ case Instruction::MUL_INT_2ADDR:
+ is_two_addr = true;
+ // Fallthrough
+ case Instruction::MUL_INT:
+ op = kOpMul;
+ break;
+ case Instruction::DIV_INT_2ADDR:
+ is_two_addr = true;
+ // Fallthrough
+ case Instruction::DIV_INT:
+ op = kOpDiv;
+ is_div_rem = true;
+ break;
+ /* NOTE: returns in kArg1 */
+ case Instruction::REM_INT_2ADDR:
+ is_two_addr = true;
+ // Fallthrough
+ case Instruction::REM_INT:
+ op = kOpRem;
+ is_div_rem = true;
+ break;
+ case Instruction::AND_INT_2ADDR:
+ is_two_addr = true;
+ // Fallthrough
+ case Instruction::AND_INT:
+ op = kOpAnd;
+ break;
+ case Instruction::OR_INT_2ADDR:
+ is_two_addr = true;
+ // Fallthrough
+ case Instruction::OR_INT:
+ op = kOpOr;
+ break;
+ case Instruction::XOR_INT_2ADDR:
+ is_two_addr = true;
+ // Fallthrough
+ case Instruction::XOR_INT:
+ op = kOpXor;
+ break;
+ case Instruction::SHL_INT_2ADDR:
+ is_two_addr = true;
+ // Fallthrough
+ case Instruction::SHL_INT:
+ shift_op = true;
+ op = kOpLsl;
+ break;
+ case Instruction::SHR_INT_2ADDR:
+ is_two_addr = true;
+ // Fallthrough
+ case Instruction::SHR_INT:
+ shift_op = true;
+ op = kOpAsr;
+ break;
+ case Instruction::USHR_INT_2ADDR:
+ is_two_addr = true;
+ // Fallthrough
+ case Instruction::USHR_INT:
+ shift_op = true;
+ op = kOpLsr;
+ break;
+ default:
+ LOG(FATAL) << "Invalid word arith op: " << opcode;
+ }
+
+ // Can we convert to a two address instruction?
+ if (!is_two_addr &&
+ (mir_graph_->SRegToVReg(rl_dest.s_reg_low) ==
+ mir_graph_->SRegToVReg(rl_lhs.s_reg_low))) {
+ is_two_addr = true;
+ }
+
+ // Get the div/rem stuff out of the way.
+ if (is_div_rem) {
+ rl_result = GenDivRem(rl_dest, rl_lhs, rl_rhs, op == kOpDiv, true);
+ StoreValue(rl_dest, rl_result);
+ return;
+ }
+
+ if (unary) {
+ rl_lhs = LoadValue(rl_lhs, kCoreReg);
+ rl_result = UpdateLoc(rl_dest);
+ rl_result = EvalLoc(rl_dest, kCoreReg, true);
+ OpRegReg(op, rl_result.low_reg, rl_lhs.low_reg);
+ } else {
+ if (shift_op) {
+ // X86 doesn't require masking and must use ECX.
+ int t_reg = TargetReg(kCount); // rCX
+ LoadValueDirectFixed(rl_rhs, t_reg);
+ if (is_two_addr) {
+ // Can we do this directly into memory?
+ rl_result = UpdateLoc(rl_dest);
+ rl_rhs = LoadValue(rl_rhs, kCoreReg);
+ if (rl_result.location != kLocPhysReg) {
+ // Okay, we can do this into memory
+ OpMemReg(op, rl_result, t_reg);
+ FreeTemp(t_reg);
+ return;
+ } else if (!IsFpReg(rl_result.low_reg)) {
+ // Can do this directly into the result register
+ OpRegReg(op, rl_result.low_reg, t_reg);
+ FreeTemp(t_reg);
+ StoreFinalValue(rl_dest, rl_result);
+ return;
+ }
+ }
+ // Three address form, or we can't do directly.
+ rl_lhs = LoadValue(rl_lhs, kCoreReg);
+ rl_result = EvalLoc(rl_dest, kCoreReg, true);
+ OpRegRegReg(op, rl_result.low_reg, rl_lhs.low_reg, t_reg);
+ FreeTemp(t_reg);
+ } else {
+ // Multiply is 3 operand only (sort of).
+ if (is_two_addr && op != kOpMul) {
+ // Can we do this directly into memory?
+ rl_result = UpdateLoc(rl_dest);
+ if (rl_result.location == kLocPhysReg) {
+ // Can we do this from memory directly?
+ rl_rhs = UpdateLoc(rl_rhs);
+ if (rl_rhs.location != kLocPhysReg) {
+ OpRegMem(op, rl_result.low_reg, rl_rhs);
+ StoreFinalValue(rl_dest, rl_result);
+ return;
+ } else if (!IsFpReg(rl_rhs.low_reg)) {
+ OpRegReg(op, rl_result.low_reg, rl_rhs.low_reg);
+ StoreFinalValue(rl_dest, rl_result);
+ return;
+ }
+ }
+ rl_rhs = LoadValue(rl_rhs, kCoreReg);
+ if (rl_result.location != kLocPhysReg) {
+ // Okay, we can do this into memory.
+ OpMemReg(op, rl_result, rl_rhs.low_reg);
+ return;
+ } else if (!IsFpReg(rl_result.low_reg)) {
+ // Can do this directly into the result register.
+ OpRegReg(op, rl_result.low_reg, rl_rhs.low_reg);
+ StoreFinalValue(rl_dest, rl_result);
+ return;
+ } else {
+ rl_lhs = LoadValue(rl_lhs, kCoreReg);
+ rl_result = EvalLoc(rl_dest, kCoreReg, true);
+ OpRegRegReg(op, rl_result.low_reg, rl_lhs.low_reg, rl_rhs.low_reg);
+ }
+ } else {
+ // Try to use reg/memory instructions.
+ rl_lhs = UpdateLoc(rl_lhs);
+ rl_rhs = UpdateLoc(rl_rhs);
+ // We can't optimize with FP registers.
+ if (!IsOperationSafeWithoutTemps(rl_lhs, rl_rhs)) {
+ // Something is difficult, so fall back to the standard case.
+ rl_lhs = LoadValue(rl_lhs, kCoreReg);
+ rl_rhs = LoadValue(rl_rhs, kCoreReg);
+ rl_result = EvalLoc(rl_dest, kCoreReg, true);
+ OpRegRegReg(op, rl_result.low_reg, rl_lhs.low_reg, rl_rhs.low_reg);
+ } else {
+ // We can optimize by moving to result and using memory operands.
+ if (rl_rhs.location != kLocPhysReg) {
+ // Force LHS into result.
+ rl_result = EvalLoc(rl_dest, kCoreReg, true);
+ LoadValueDirect(rl_lhs, rl_result.low_reg);
+ OpRegMem(op, rl_result.low_reg, rl_rhs);
+ } else if (rl_lhs.location != kLocPhysReg) {
+ // RHS is in a register; LHS is in memory.
+ if (op != kOpSub) {
+ // Force RHS into result and operate on memory.
+ rl_result = EvalLoc(rl_dest, kCoreReg, true);
+ OpRegCopy(rl_result.low_reg, rl_rhs.low_reg);
+ OpRegMem(op, rl_result.low_reg, rl_lhs);
+ } else {
+ // Subtraction isn't commutative.
+ rl_lhs = LoadValue(rl_lhs, kCoreReg);
+ rl_rhs = LoadValue(rl_rhs, kCoreReg);
+ rl_result = EvalLoc(rl_dest, kCoreReg, true);
+ OpRegRegReg(op, rl_result.low_reg, rl_lhs.low_reg, rl_rhs.low_reg);
+ }
+ } else {
+ // Both are in registers.
+ rl_lhs = LoadValue(rl_lhs, kCoreReg);
+ rl_rhs = LoadValue(rl_rhs, kCoreReg);
+ rl_result = EvalLoc(rl_dest, kCoreReg, true);
+ OpRegRegReg(op, rl_result.low_reg, rl_lhs.low_reg, rl_rhs.low_reg);
+ }
+ }
+ }
+ }
+ }
+ StoreValue(rl_dest, rl_result);
+}
+
+bool X86Mir2Lir::IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs) {
+ // If we have non-core registers, then we can't do good things.
+ if (rl_lhs.location == kLocPhysReg && IsFpReg(rl_lhs.low_reg)) {
+ return false;
+ }
+ if (rl_rhs.location == kLocPhysReg && IsFpReg(rl_rhs.low_reg)) {
+ return false;
+ }
+
+ // Everything will be fine :-).
+ return true;
+}
} // namespace art
diff --git a/compiler/dex/quick/x86/utility_x86.cc b/compiler/dex/quick/x86/utility_x86.cc
index bd38c03..a77e921 100644
--- a/compiler/dex/quick/x86/utility_x86.cc
+++ b/compiler/dex/quick/x86/utility_x86.cc
@@ -236,7 +236,57 @@
LOG(FATAL) << "Bad case in OpRegMem " << op;
break;
}
- return NewLIR3(opcode, r_dest, rBase, offset);
+ LIR *l = NewLIR3(opcode, r_dest, rBase, offset);
+ if (rBase == rX86_SP) {
+ AnnotateDalvikRegAccess(l, offset >> 2, true /* is_load */, false /* is_64bit */);
+ }
+ return l;
+}
+
+LIR* X86Mir2Lir::OpMemReg(OpKind op, RegLocation rl_dest, int r_value) {
+ DCHECK_NE(rl_dest.location, kLocPhysReg);
+ int displacement = SRegOffset(rl_dest.s_reg_low);
+ X86OpCode opcode = kX86Nop;
+ switch (op) {
+ case kOpSub: opcode = kX86Sub32MR; break;
+ case kOpMov: opcode = kX86Mov32MR; break;
+ case kOpCmp: opcode = kX86Cmp32MR; break;
+ case kOpAdd: opcode = kX86Add32MR; break;
+ case kOpAnd: opcode = kX86And32MR; break;
+ case kOpOr: opcode = kX86Or32MR; break;
+ case kOpXor: opcode = kX86Xor32MR; break;
+ case kOpLsl: opcode = kX86Sal32MC; break;
+ case kOpLsr: opcode = kX86Shr32MC; break;
+ case kOpAsr: opcode = kX86Sar32MC; break;
+ default:
+ LOG(FATAL) << "Bad case in OpMemReg " << op;
+ break;
+ }
+ LIR *l = NewLIR3(opcode, rX86_SP, displacement, r_value);
+ AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, false /* is_64bit */);
+ return l;
+}
+
+LIR* X86Mir2Lir::OpRegMem(OpKind op, int r_dest, RegLocation rl_value) {
+ DCHECK_NE(rl_value.location, kLocPhysReg);
+ int displacement = SRegOffset(rl_value.s_reg_low);
+ X86OpCode opcode = kX86Nop;
+ switch (op) {
+ case kOpSub: opcode = kX86Sub32RM; break;
+ case kOpMov: opcode = kX86Mov32RM; break;
+ case kOpCmp: opcode = kX86Cmp32RM; break;
+ case kOpAdd: opcode = kX86Add32RM; break;
+ case kOpAnd: opcode = kX86And32RM; break;
+ case kOpOr: opcode = kX86Or32RM; break;
+ case kOpXor: opcode = kX86Xor32RM; break;
+ case kOpMul: opcode = kX86Imul32RM; break;
+ default:
+ LOG(FATAL) << "Bad case in OpRegMem " << op;
+ break;
+ }
+ LIR *l = NewLIR3(opcode, r_dest, rX86_SP, displacement);
+ AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, false /* is_64bit */);
+ return l;
}
LIR* X86Mir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1,