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review.blissroms.org / platform_art / 2af52e76dc76b41969b6147d7bd6925d0f61e932 / . / src / compiler / dex / quick / codegen.h
blob: 21290caed04f2e71e53161ff289696350e8cc994 [file] [log] [blame]
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]1/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
buzbee395116c2013-02-27 14:30:25 -0800[diff] [blame]17#ifndef ART_SRC_COMPILER_DEX_QUICK_CODEGEN_H_
18#define ART_SRC_COMPILER_DEX_QUICK_CODEGEN_H_
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]19
Brian Carlstrom265091e2013-01-30 14:08:26 -0800[diff] [blame]20#include "invoke_type.h"
21#include "compiler/dex/compiler_enums.h"
buzbee395116c2013-02-27 14:30:25 -0800[diff] [blame]22#include "compiler/dex/compiler_ir.h"
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]23
24namespace art {
25
26// Set to 1 to measure cost of suspend check.
27#define NO_SUSPEND 0
28
29#define IS_BINARY_OP (1ULL << kIsBinaryOp)
30#define IS_BRANCH (1ULL << kIsBranch)
31#define IS_IT (1ULL << kIsIT)
32#define IS_LOAD (1ULL << kMemLoad)
33#define IS_QUAD_OP (1ULL << kIsQuadOp)
34#define IS_QUIN_OP (1ULL << kIsQuinOp)
35#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp)
36#define IS_STORE (1ULL << kMemStore)
37#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp)
38#define IS_UNARY_OP (1ULL << kIsUnaryOp)
39#define NEEDS_FIXUP (1ULL << kPCRelFixup)
40#define NO_OPERAND (1ULL << kNoOperand)
41#define REG_DEF0 (1ULL << kRegDef0)
42#define REG_DEF1 (1ULL << kRegDef1)
43#define REG_DEFA (1ULL << kRegDefA)
44#define REG_DEFD (1ULL << kRegDefD)
45#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0)
46#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2)
47#define REG_DEF_LIST0 (1ULL << kRegDefList0)
48#define REG_DEF_LIST1 (1ULL << kRegDefList1)
49#define REG_DEF_LR (1ULL << kRegDefLR)
50#define REG_DEF_SP (1ULL << kRegDefSP)
51#define REG_USE0 (1ULL << kRegUse0)
52#define REG_USE1 (1ULL << kRegUse1)
53#define REG_USE2 (1ULL << kRegUse2)
54#define REG_USE3 (1ULL << kRegUse3)
55#define REG_USE4 (1ULL << kRegUse4)
56#define REG_USEA (1ULL << kRegUseA)
57#define REG_USEC (1ULL << kRegUseC)
58#define REG_USED (1ULL << kRegUseD)
59#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0)
60#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2)
61#define REG_USE_LIST0 (1ULL << kRegUseList0)
62#define REG_USE_LIST1 (1ULL << kRegUseList1)
63#define REG_USE_LR (1ULL << kRegUseLR)
64#define REG_USE_PC (1ULL << kRegUsePC)
65#define REG_USE_SP (1ULL << kRegUseSP)
66#define SETS_CCODES (1ULL << kSetsCCodes)
67#define USES_CCODES (1ULL << kUsesCCodes)
68
69// Common combo register usage patterns.
70#define REG_DEF01 (REG_DEF0 | REG_DEF1)
71#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
72#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01)
73#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0)
74#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12)
75#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1)
76#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2)
77#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED)
78#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD)
79#define REG_DEFA_USEA (REG_DEFA | REG_USEA)
80#define REG_USE012 (REG_USE01 | REG_USE2)
81#define REG_USE014 (REG_USE01 | REG_USE4)
82#define REG_USE01 (REG_USE0 | REG_USE1)
83#define REG_USE02 (REG_USE0 | REG_USE2)
84#define REG_USE12 (REG_USE1 | REG_USE2)
85#define REG_USE23 (REG_USE2 | REG_USE3)
86
Brian Carlstrom265091e2013-01-30 14:08:26 -0800[diff] [blame]87struct BasicBlock;
88struct CallInfo;
89struct CompilationUnit;
90struct LIR;
91struct MIR;
92struct RegLocation;
93struct RegisterInfo;
94
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]95typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, uint32_t dex_idx,
96 uint32_t method_idx, uintptr_t direct_code,
97 uintptr_t direct_method, InvokeType type);
98
99// Target-specific initialization.
100bool InitArmCodegen(CompilationUnit* cu);
101bool InitMipsCodegen(CompilationUnit* cu);
102bool InitX86Codegen(CompilationUnit* cu);
103
104class Codegen {
105
106 public:
107
108 virtual ~Codegen(){};
109
110 // Shared by all targets - implemented in gen_common.cc.
111 void HandleSuspendLaunchPads(CompilationUnit *cu);
112 void HandleIntrinsicLaunchPads(CompilationUnit *cu);
113 void HandleThrowLaunchPads(CompilationUnit *cu);
114 void GenBarrier(CompilationUnit* cu);
115 LIR* GenCheck(CompilationUnit* cu, ConditionCode c_code, ThrowKind kind);
116 LIR* GenImmedCheck(CompilationUnit* cu, ConditionCode c_code, int reg, int imm_val,
117 ThrowKind kind);
118 LIR* GenNullCheck(CompilationUnit* cu, int s_reg, int m_reg, int opt_flags);
119 LIR* GenRegRegCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int reg2,
120 ThrowKind kind);
121 void GenCompareAndBranch(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_src1,
122 RegLocation rl_src2, LIR* taken, LIR* fall_through);
123 void GenCompareZeroAndBranch(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_src,
124 LIR* taken, LIR* fall_through);
125 void GenIntToLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
126 void GenIntNarrowing(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
127 RegLocation rl_src);
128 void GenNewArray(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_dest,
129 RegLocation rl_src);
130 void GenFilledNewArray(CompilationUnit* cu, CallInfo* info);
131 void GenSput(CompilationUnit* cu, uint32_t field_idx, RegLocation rl_src,
132 bool is_long_or_double, bool is_object);
133 void GenSget(CompilationUnit* cu, uint32_t field_idx, RegLocation rl_dest,
134 bool is_long_or_double, bool is_object);
135 void GenShowTarget(CompilationUnit* cu);
136 void GenIGet(CompilationUnit* cu, uint32_t field_idx, int opt_flags, OpSize size,
137 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object);
138 void GenIPut(CompilationUnit* cu, uint32_t field_idx, int opt_flags, OpSize size,
139 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object);
140 void GenConstClass(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_dest);
141 void GenConstString(CompilationUnit* cu, uint32_t string_idx, RegLocation rl_dest);
142 void GenNewInstance(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_dest);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]143 void GenThrow(CompilationUnit* cu, RegLocation rl_src);
144 void GenInstanceof(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_dest,
145 RegLocation rl_src);
146 void GenCheckCast(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_src);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]147 void GenLong3Addr(CompilationUnit* cu, OpKind first_op, OpKind second_op, RegLocation rl_dest,
148 RegLocation rl_src1, RegLocation rl_src2);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]149 void GenShiftOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]150 RegLocation rl_src1, RegLocation rl_shift);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]151 void GenArithOpInt(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]152 RegLocation rl_src1, RegLocation rl_src2);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]153 void GenArithOpIntLit(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]154 RegLocation rl_src, int lit);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]155 void GenArithOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]156 RegLocation rl_src1, RegLocation rl_src2);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]157 void GenConversionCall(CompilationUnit* cu, int func_offset, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]158 RegLocation rl_src);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]159 void GenSuspendTest(CompilationUnit* cu, int opt_flags);
160 void GenSuspendTestAndBranch(CompilationUnit* cu, int opt_flags, LIR* target);
161
162 // Shared by all targets - implemented in gen_invoke.cc.
163 int CallHelperSetup(CompilationUnit* cu, int helper_offset);
164 LIR* CallHelper(CompilationUnit* cu, int r_tgt, int helper_offset, bool safepoint_pc);
165 void CallRuntimeHelperImm(CompilationUnit* cu, int helper_offset, int arg0, bool safepoint_pc);
166 void CallRuntimeHelperReg(CompilationUnit* cu, int helper_offset, int arg0, bool safepoint_pc);
167 void CallRuntimeHelperRegLocation(CompilationUnit* cu, int helper_offset, RegLocation arg0,
168 bool safepoint_pc);
169 void CallRuntimeHelperImmImm(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
170 bool safepoint_pc);
171 void CallRuntimeHelperImmRegLocation(CompilationUnit* cu, int helper_offset, int arg0,
172 RegLocation arg1, bool safepoint_pc);
173 void CallRuntimeHelperRegLocationImm(CompilationUnit* cu, int helper_offset, RegLocation arg0,
174 int arg1, bool safepoint_pc);
175 void CallRuntimeHelperImmReg(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
176 bool safepoint_pc);
177 void CallRuntimeHelperRegImm(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
178 bool safepoint_pc);
179 void CallRuntimeHelperImmMethod(CompilationUnit* cu, int helper_offset, int arg0,
180 bool safepoint_pc);
181 void CallRuntimeHelperRegLocationRegLocation(CompilationUnit* cu, int helper_offset,
182 RegLocation arg0, RegLocation arg1,
183 bool safepoint_pc);
184 void CallRuntimeHelperRegReg(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
185 bool safepoint_pc);
186 void CallRuntimeHelperRegRegImm(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
187 int arg2, bool safepoint_pc);
188 void CallRuntimeHelperImmMethodRegLocation(CompilationUnit* cu, int helper_offset, int arg0,
189 RegLocation arg2, bool safepoint_pc);
190 void CallRuntimeHelperImmMethodImm(CompilationUnit* cu, int helper_offset, int arg0, int arg2,
191 bool safepoint_pc);
192 void CallRuntimeHelperImmRegLocationRegLocation(CompilationUnit* cu, int helper_offset,
193 int arg0, RegLocation arg1, RegLocation arg2,
194 bool safepoint_pc);
195 void GenInvoke(CompilationUnit* cu, CallInfo* info);
196 void FlushIns(CompilationUnit* cu, RegLocation* ArgLocs, RegLocation rl_method);
197 int GenDalvikArgsNoRange(CompilationUnit* cu, CallInfo* info, int call_state, LIR** pcrLabel,
198 NextCallInsn next_call_insn, uint32_t dex_idx, uint32_t method_idx,
199 uintptr_t direct_code, uintptr_t direct_method, InvokeType type,
200 bool skip_this);
201 int GenDalvikArgsRange(CompilationUnit* cu, CallInfo* info, int call_state, LIR** pcrLabel,
202 NextCallInsn next_call_insn, uint32_t dex_idx, uint32_t method_idx,
203 uintptr_t direct_code, uintptr_t direct_method, InvokeType type,
204 bool skip_this);
205 RegLocation InlineTarget(CompilationUnit* cu, CallInfo* info);
206 RegLocation InlineTargetWide(CompilationUnit* cu, CallInfo* info);
207 CallInfo* NewMemCallInfo(CompilationUnit* cu, BasicBlock* bb, MIR* mir, InvokeType type,
208 bool is_range);
209 bool GenInlinedCharAt(CompilationUnit* cu, CallInfo* info);
210 bool GenInlinedStringIsEmptyOrLength(CompilationUnit* cu, CallInfo* info, bool is_empty);
211 bool GenInlinedAbsInt(CompilationUnit *cu, CallInfo* info);
212 bool GenInlinedAbsLong(CompilationUnit *cu, CallInfo* info);
213 bool GenInlinedFloatCvt(CompilationUnit *cu, CallInfo* info);
214 bool GenInlinedDoubleCvt(CompilationUnit *cu, CallInfo* info);
215 bool GenInlinedIndexOf(CompilationUnit* cu, CallInfo* info, bool zero_based);
216 bool GenInlinedStringCompareTo(CompilationUnit* cu, CallInfo* info);
Ian Rogers07ec8e12012-12-01 01:26:51 -0800[diff] [blame]217 bool GenInlinedCurrentThread(CompilationUnit* cu, CallInfo* info);
Jeff Hao5a70fe82013-02-07 15:02:10 -0800[diff] [blame]218 bool GenInlinedUnsafeGet(CompilationUnit* cu, CallInfo* info, bool is_long, bool is_volatile);
219 bool GenInlinedUnsafePut(CompilationUnit* cu, CallInfo* info, bool is_long, bool is_object,
220 bool is_volatile, bool is_ordered);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]221 bool GenIntrinsic(CompilationUnit* cu, CallInfo* info);
222
223 // Shared by all targets - implemented in gen_loadstore.cc.
224 RegLocation LoadCurrMethod(CompilationUnit *cu);
225 void LoadCurrMethodDirect(CompilationUnit *cu, int r_tgt);
226 LIR* LoadConstant(CompilationUnit* cu, int r_dest, int value);
227 LIR* LoadWordDisp(CompilationUnit* cu, int rBase, int displacement, int r_dest);
228 RegLocation LoadValue(CompilationUnit* cu, RegLocation rl_src, RegisterClass op_kind);
229 RegLocation LoadValueWide(CompilationUnit* cu, RegLocation rl_src, RegisterClass op_kind);
230 void LoadValueDirect(CompilationUnit* cu, RegLocation rl_src, int r_dest);
231 void LoadValueDirectFixed(CompilationUnit* cu, RegLocation rl_src, int r_dest);
232 void LoadValueDirectWide(CompilationUnit* cu, RegLocation rl_src, int reg_lo, int reg_hi);
233 void LoadValueDirectWideFixed(CompilationUnit* cu, RegLocation rl_src, int reg_lo, int reg_hi);
234 LIR* StoreWordDisp(CompilationUnit* cu, int rBase, int displacement, int r_src);
235 void StoreValue(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
236 void StoreValueWide(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
237
238 // Required for target - codegen helpers.
239 virtual bool SmallLiteralDivide(CompilationUnit* cu, Instruction::Code dalvik_opcode,
240 RegLocation rl_src, RegLocation rl_dest, int lit) = 0;
241 virtual int LoadHelper(CompilationUnit* cu, int offset) = 0;
242 virtual LIR* LoadBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_dest,
243 OpSize size, int s_reg) = 0;
244 virtual LIR* LoadBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_dest_lo,
245 int r_dest_hi, int s_reg) = 0;
246 virtual LIR* LoadBaseIndexed(CompilationUnit* cu, int rBase, int r_index, int r_dest, int scale,
247 OpSize size) = 0;
248 virtual LIR* LoadBaseIndexedDisp(CompilationUnit *cu, int rBase, int r_index, int scale,
249 int displacement, int r_dest, int r_dest_hi, OpSize size,
250 int s_reg) = 0;
251 virtual LIR* LoadConstantNoClobber(CompilationUnit* cu, int r_dest, int value) = 0;
buzbee4ef3e452012-12-14 13:35:28 -0800[diff] [blame]252 virtual LIR* LoadConstantWide(CompilationUnit* cu, int r_dest_lo, int r_dest_hi,
253 int64_t value) = 0;
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]254 virtual LIR* StoreBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_src,
255 OpSize size) = 0;
256 virtual LIR* StoreBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_src_lo,
257 int r_src_hi) = 0;
258 virtual LIR* StoreBaseIndexed(CompilationUnit* cu, int rBase, int r_index, int r_src, int scale,
259 OpSize size) = 0;
260 virtual LIR* StoreBaseIndexedDisp(CompilationUnit *cu, int rBase, int r_index, int scale,
261 int displacement, int r_src, int r_src_hi, OpSize size,
262 int s_reg) = 0;
263 virtual void MarkGCCard(CompilationUnit* cu, int val_reg, int tgt_addr_reg) = 0;
264
265 // Required for target - register utilities.
266 virtual bool IsFpReg(int reg) = 0;
267 virtual bool SameRegType(int reg1, int reg2) = 0;
268 virtual int AllocTypedTemp(CompilationUnit* cu, bool fp_hint, int reg_class) = 0;
269 virtual int AllocTypedTempPair(CompilationUnit* cu, bool fp_hint, int reg_class) = 0;
270 virtual int S2d(int low_reg, int high_reg) = 0;
271 virtual int TargetReg(SpecialTargetRegister reg) = 0;
272 virtual RegisterInfo* GetRegInfo(CompilationUnit* cu, int reg) = 0;
273 virtual RegLocation GetReturnAlt(CompilationUnit* cu) = 0;
274 virtual RegLocation GetReturnWideAlt(CompilationUnit* cu) = 0;
275 virtual RegLocation LocCReturn() = 0;
276 virtual RegLocation LocCReturnDouble() = 0;
277 virtual RegLocation LocCReturnFloat() = 0;
278 virtual RegLocation LocCReturnWide() = 0;
279 virtual uint32_t FpRegMask() = 0;
280 virtual uint64_t GetRegMaskCommon(CompilationUnit* cu, int reg) = 0;
281 virtual void AdjustSpillMask(CompilationUnit* cu) = 0;
282 virtual void ClobberCalleeSave(CompilationUnit *cu) = 0;
283 virtual void FlushReg(CompilationUnit* cu, int reg) = 0;
284 virtual void FlushRegWide(CompilationUnit* cu, int reg1, int reg2) = 0;
285 virtual void FreeCallTemps(CompilationUnit* cu) = 0;
286 virtual void FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep, RegLocation rl_free) = 0;
287 virtual void LockCallTemps(CompilationUnit* cu) = 0;
288 virtual void MarkPreservedSingle(CompilationUnit* cu, int v_reg, int reg) = 0;
289 virtual void CompilerInitializeRegAlloc(CompilationUnit* cu) = 0;
290
291 // Required for target - miscellaneous.
292 virtual AssemblerStatus AssembleInstructions(CompilationUnit* cu, uintptr_t start_addr) = 0;
293 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0;
294 virtual void SetupTargetResourceMasks(CompilationUnit* cu, LIR* lir) = 0;
295 virtual const char* GetTargetInstFmt(int opcode) = 0;
296 virtual const char* GetTargetInstName(int opcode) = 0;
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]297 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0;
298 virtual uint64_t GetPCUseDefEncoding() = 0;
299 virtual uint64_t GetTargetInstFlags(int opcode) = 0;
300 virtual int GetInsnSize(LIR* lir) = 0;
301 virtual bool IsUnconditionalBranch(LIR* lir) = 0;
302
303 // Required for target - Dalvik-level generators.
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]304 virtual void GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee4ef3e452012-12-14 13:35:28 -0800[diff] [blame]305 RegLocation rl_src1, RegLocation rl_src2) = 0;
306 virtual void GenMulLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
307 RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]308 virtual void GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]309 RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]310 virtual void GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]311 RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]312 virtual void GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]313 RegLocation rl_dest, RegLocation rl_src1,
314 RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]315 virtual void GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]316 RegLocation rl_src1, RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]317 virtual void GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]318 RegLocation rl_src1, RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]319 virtual void GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]320 RegLocation rl_src) = 0;
321 virtual bool GenInlinedCas32(CompilationUnit* cu, CallInfo* info, bool need_write_barrier) = 0;
322 virtual bool GenInlinedMinMaxInt(CompilationUnit *cu, CallInfo* info, bool is_min) = 0;
323 virtual bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]324 virtual void GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src) = 0;
325 virtual void GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]326 RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]327 virtual void GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]328 RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]329 virtual void GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]330 RegLocation rl_src2) = 0;
331 virtual LIR* GenRegMemCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int base,
332 int offset, ThrowKind kind) = 0;
333 virtual RegLocation GenDivRem(CompilationUnit* cu, RegLocation rl_dest, int reg_lo, int reg_hi,
334 bool is_div) = 0;
335 virtual RegLocation GenDivRemLit(CompilationUnit* cu, RegLocation rl_dest, int reg_lo, int lit,
336 bool is_div) = 0;
337 virtual void GenCmpLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
338 RegLocation rl_src2) = 0;
339 virtual void GenDivZeroCheck(CompilationUnit* cu, int reg_lo, int reg_hi) = 0;
340 virtual void GenEntrySequence(CompilationUnit* cu, RegLocation* ArgLocs,
341 RegLocation rl_method) = 0;
342 virtual void GenExitSequence(CompilationUnit* cu) = 0;
343 virtual void GenFillArrayData(CompilationUnit* cu, uint32_t table_offset,
344 RegLocation rl_src) = 0;
345 virtual void GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir, bool gt_bias,
346 bool is_double) = 0;
347 virtual void GenFusedLongCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir) = 0;
buzbeef662a7c2013-02-12 16:19:43 -0800[diff] [blame]348 virtual void GenSelect(CompilationUnit* cu, BasicBlock* bb, MIR* mir) = 0;
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]349 virtual void GenMemBarrier(CompilationUnit* cu, MemBarrierKind barrier_kind) = 0;
350 virtual void GenMonitorEnter(CompilationUnit* cu, int opt_flags, RegLocation rl_src) = 0;
351 virtual void GenMonitorExit(CompilationUnit* cu, int opt_flags, RegLocation rl_src) = 0;
jeffhao1eab9582013-01-22 13:33:52 -0800[diff] [blame]352 virtual void GenMoveException(CompilationUnit* cu, RegLocation rl_dest) = 0;
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]353 virtual void GenMultiplyByTwoBitMultiplier(CompilationUnit* cu, RegLocation rl_src,
354 RegLocation rl_result, int lit, int first_bit,
355 int second_bit) = 0;
356 virtual void GenNegDouble(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src) = 0;
357 virtual void GenNegFloat(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src) = 0;
358 virtual void GenPackedSwitch(CompilationUnit* cu, uint32_t table_offset,
359 RegLocation rl_src) = 0;
360 virtual void GenSparseSwitch(CompilationUnit* cu, uint32_t table_offset,
361 RegLocation rl_src) = 0;
362 virtual void GenSpecialCase(CompilationUnit* cu, BasicBlock* bb, MIR* mir,
363 SpecialCaseHandler special_case) = 0;
buzbeee6285f92012-12-06 15:57:46 -0800[diff] [blame]364 virtual void GenArrayObjPut(CompilationUnit* cu, int opt_flags, RegLocation rl_array,
365 RegLocation rl_index, RegLocation rl_src, int scale) = 0;
366 virtual void GenArrayGet(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
367 RegLocation rl_index, RegLocation rl_dest, int scale) = 0;
368 virtual void GenArrayPut(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
369 RegLocation rl_index, RegLocation rl_src, int scale) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]370 virtual void GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
buzbee4ef3e452012-12-14 13:35:28 -0800[diff] [blame]371 RegLocation rl_dest, RegLocation rl_src1,
372 RegLocation rl_shift) = 0;
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]373
374 // Required for target - single operation generators.
375 virtual LIR* OpUnconditionalBranch(CompilationUnit* cu, LIR* target) = 0;
376 virtual LIR* OpCmpBranch(CompilationUnit* cu, ConditionCode cond, int src1, int src2,
377 LIR* target) = 0;
378 virtual LIR* OpCmpImmBranch(CompilationUnit* cu, ConditionCode cond, int reg, int check_value,
379 LIR* target) = 0;
380 virtual LIR* OpCondBranch(CompilationUnit* cu, ConditionCode cc, LIR* target) = 0;
381 virtual LIR* OpDecAndBranch(CompilationUnit* cu, ConditionCode c_code, int reg,
382 LIR* target) = 0;
383 virtual LIR* OpFpRegCopy(CompilationUnit* cu, int r_dest, int r_src) = 0;
384 virtual LIR* OpIT(CompilationUnit* cu, ConditionCode cond, const char* guide) = 0;
385 virtual LIR* OpMem(CompilationUnit* cu, OpKind op, int rBase, int disp) = 0;
386 virtual LIR* OpPcRelLoad(CompilationUnit* cu, int reg, LIR* target) = 0;
387 virtual LIR* OpReg(CompilationUnit* cu, OpKind op, int r_dest_src) = 0;
388 virtual LIR* OpRegCopy(CompilationUnit* cu, int r_dest, int r_src) = 0;
389 virtual LIR* OpRegCopyNoInsert(CompilationUnit* cu, int r_dest, int r_src) = 0;
390 virtual LIR* OpRegImm(CompilationUnit* cu, OpKind op, int r_dest_src1, int value) = 0;
391 virtual LIR* OpRegMem(CompilationUnit* cu, OpKind op, int r_dest, int rBase, int offset) = 0;
392 virtual LIR* OpRegReg(CompilationUnit* cu, OpKind op, int r_dest_src1, int r_src2) = 0;
393 virtual LIR* OpRegRegImm(CompilationUnit* cu, OpKind op, int r_dest, int r_src1, int value) = 0;
394 virtual LIR* OpRegRegReg(CompilationUnit* cu, OpKind op, int r_dest, int r_src1,
395 int r_src2) = 0;
396 virtual LIR* OpTestSuspend(CompilationUnit* cu, LIR* target) = 0;
397 virtual LIR* OpThreadMem(CompilationUnit* cu, OpKind op, int thread_offset) = 0;
398 virtual LIR* OpVldm(CompilationUnit* cu, int rBase, int count) = 0;
399 virtual LIR* OpVstm(CompilationUnit* cu, int rBase, int count) = 0;
400 virtual void OpLea(CompilationUnit* cu, int rBase, int reg1, int reg2, int scale,
401 int offset) = 0;
402 virtual void OpRegCopyWide(CompilationUnit* cu, int dest_lo, int dest_hi, int src_lo,
403 int src_hi) = 0;
404 virtual void OpTlsCmp(CompilationUnit* cu, int offset, int val) = 0;
buzbee4ef3e452012-12-14 13:35:28 -0800[diff] [blame]405 virtual bool InexpensiveConstantInt(int32_t value) = 0;
406 virtual bool InexpensiveConstantFloat(int32_t value) = 0;
407 virtual bool InexpensiveConstantLong(int64_t value) = 0;
408 virtual bool InexpensiveConstantDouble(int64_t value) = 0;
buzbee5f61f672012-11-28 17:22:17 -0800[diff] [blame]409
410 // Temp workaround
411 void Workaround7250540(CompilationUnit* cu, RegLocation rl_dest, int value);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]412 }; // Class Codegen
413
414} // namespace art
415
buzbee395116c2013-02-27 14:30:25 -0800[diff] [blame]416#endif // ART_SRC_COMPILER_DEX_QUICK_CODEGEN_H_