Blame - compiler/dex/quick/arm64/codegen_arm64.h - platform_art

Matteo Franchin

43ec873

2014-03-31 15:00:14 +0100

[diff] [blame]

/*

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* Licensed under the Apache License, Version 2.0 (the "License");

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* you may not use this file except in compliance with the License.

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* You may obtain a copy of the License at

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*

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* http://www.apache.org/licenses/LICENSE-2.0

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*

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* Unless required by applicable law or agreed to in writing, software

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* distributed under the License is distributed on an "AS IS" BASIS,

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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

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* See the License for the specific language governing permissions and

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* limitations under the License.

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*/

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#ifndef ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_

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#define ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_

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#include "arm64_lir.h"

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#include "dex/compiler_internals.h"

namespace art {

class Arm64Mir2Lir FINAL : public Mir2Lir {

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public:

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Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);

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// Required for target - codegen helpers.

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bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,

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RegLocation rl_dest, int lit);

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bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE;

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LIR* CheckSuspendUsingLoad() OVERRIDE;

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RegStorage LoadHelper(ThreadOffset<4> offset);

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LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,

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int s_reg);

Matteo Franchin

43ec873

2014-03-31 15:00:14 +0100

[diff] [blame]

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LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,

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OpSize size);

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LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,

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RegStorage r_dest, OpSize size, int s_reg);

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LIR* LoadConstantNoClobber(RegStorage r_dest, int value);

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LIR* LoadConstantWide(RegStorage r_dest, int64_t value);

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LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size);

Matteo Franchin

43ec873

2014-03-31 15:00:14 +0100

[diff] [blame]

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LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,

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OpSize size);

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LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,

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RegStorage r_src, OpSize size, int s_reg);

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void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg);

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// Required for target - register utilities.

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RegStorage AllocTypedTemp(bool fp_hint, int reg_class);

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RegStorage AllocTypedTempWide(bool fp_hint, int reg_class);

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RegStorage TargetReg(SpecialTargetRegister reg);

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RegStorage GetArgMappingToPhysicalReg(int arg_num);

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RegLocation GetReturnAlt();

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RegLocation GetReturnWideAlt();

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RegLocation LocCReturn();

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RegLocation LocCReturnDouble();

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RegLocation LocCReturnFloat();

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RegLocation LocCReturnWide();

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uint64_t GetRegMaskCommon(RegStorage reg);

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void AdjustSpillMask();

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void ClobberCallerSave();

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void FreeCallTemps();

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void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free);

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void LockCallTemps();

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void MarkPreservedSingle(int v_reg, RegStorage reg);

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void MarkPreservedDouble(int v_reg, RegStorage reg);

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void CompilerInitializeRegAlloc();

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RegStorage AllocPreservedDouble(int s_reg);

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// Required for target - miscellaneous.

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void AssembleLIR();

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uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset);

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int AssignInsnOffsets();

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void AssignOffsets();

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static uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir);

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void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);

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void SetupTargetResourceMasks(LIR* lir, uint64_t flags);

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const char* GetTargetInstFmt(int opcode);

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const char* GetTargetInstName(int opcode);

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std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);

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uint64_t GetPCUseDefEncoding();

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uint64_t GetTargetInstFlags(int opcode);

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int GetInsnSize(LIR* lir);

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bool IsUnconditionalBranch(LIR* lir);

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// Required for target - Dalvik-level generators.

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void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,

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RegLocation rl_src1, RegLocation rl_src2);

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void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,

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RegLocation rl_index, RegLocation rl_dest, int scale);

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void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,

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RegLocation rl_src, int scale, bool card_mark);

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void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,

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RegLocation rl_src1, RegLocation rl_shift);

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void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,

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RegLocation rl_src2);

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void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,

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RegLocation rl_src2);

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void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,

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RegLocation rl_src2);

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void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,

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RegLocation rl_src2);

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void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,

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RegLocation rl_src2);

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void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,

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RegLocation rl_src2);

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void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);

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bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object);

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bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);

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bool GenInlinedSqrt(CallInfo* info);

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bool GenInlinedPeek(CallInfo* info, OpSize size);

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bool GenInlinedPoke(CallInfo* info, OpSize size);

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void GenNegLong(RegLocation rl_dest, RegLocation rl_src);

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void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,

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RegLocation rl_src2);

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void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,

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RegLocation rl_src2);

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void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,

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RegLocation rl_src2);

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RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div);

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RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div);

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void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);

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void GenDivZeroCheckWide(RegStorage reg);

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void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);

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void GenExitSequence();

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void GenSpecialExitSequence();

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void GenFillArrayData(DexOffset table_offset, RegLocation rl_src);

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void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);

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void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);

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void GenSelect(BasicBlock* bb, MIR* mir);

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void GenMemBarrier(MemBarrierKind barrier_kind);

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void GenMonitorEnter(int opt_flags, RegLocation rl_src);

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void GenMonitorExit(int opt_flags, RegLocation rl_src);

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void GenMoveException(RegLocation rl_dest);

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void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,

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int first_bit, int second_bit);

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void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);

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void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);

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void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);

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void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);

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// Required for target - single operation generators.

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LIR* OpUnconditionalBranch(LIR* target);

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LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);

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LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);

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LIR* OpCondBranch(ConditionCode cc, LIR* target);

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LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);

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LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);

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LIR* OpIT(ConditionCode cond, const char* guide);

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void OpEndIT(LIR* it);

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LIR* OpMem(OpKind op, RegStorage r_base, int disp);

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LIR* OpPcRelLoad(RegStorage reg, LIR* target);

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LIR* OpReg(OpKind op, RegStorage r_dest_src);

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void OpRegCopy(RegStorage r_dest, RegStorage r_src);

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LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);

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LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);

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LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset);

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LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);

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LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);

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LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);

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LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);

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LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);

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LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);

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LIR* OpTestSuspend(LIR* target);

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LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset);

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LIR* OpVldm(RegStorage r_base, int count);

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LIR* OpVstm(RegStorage r_base, int count);

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void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset);

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void OpRegCopyWide(RegStorage dest, RegStorage src);

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void OpTlsCmp(ThreadOffset<4> offset, int val);

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LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,

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int s_reg);

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LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size);

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LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2,

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int shift);

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LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift);

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static const ArmEncodingMap EncodingMap[kArmLast];

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int EncodeShift(int code, int amount);

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int ModifiedImmediate(uint32_t value);

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ArmConditionCode ArmConditionEncoding(ConditionCode code);

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bool InexpensiveConstantInt(int32_t value);

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bool InexpensiveConstantFloat(int32_t value);

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bool InexpensiveConstantLong(int64_t value);

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bool InexpensiveConstantDouble(int64_t value);

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private:

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void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, int64_t val,

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ConditionCode ccode);

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LIR* LoadFPConstantValue(int r_dest, int value);

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void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);

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void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);

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void AssignDataOffsets();

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RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,

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bool is_div, bool check_zero);

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RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div);

typedef struct {

OpKind op;

uint32_t shift;

} EasyMultiplyOp;

bool GetEasyMultiplyOp(int lit, EasyMultiplyOp* op);

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bool GetEasyMultiplyTwoOps(int lit, EasyMultiplyOp* ops);

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void GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops);

};

} // namespace art

#endif // ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_