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review.blissroms.org / platform_art / f84f99fe3a944310fdfb6f17836079ac5c48c799 / . / src / compiler / codegen / codegen.h
blob: 03ecb431714697bc55e47f7506c0b10797759cf5 [file] [log] [blame]
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]1/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_SRC_COMPILER_CODEGEN_CODEGEN_H_
18#define ART_SRC_COMPILER_CODEGEN_CODEGEN_H_
19
Brian Carlstrom641ce032013-01-31 15:21:37 -0800[diff] [blame]20#include "compiler/compiler_ir.h"
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]21
22namespace art {
23
24// Set to 1 to measure cost of suspend check.
25#define NO_SUSPEND 0
26
27#define IS_BINARY_OP (1ULL << kIsBinaryOp)
28#define IS_BRANCH (1ULL << kIsBranch)
29#define IS_IT (1ULL << kIsIT)
30#define IS_LOAD (1ULL << kMemLoad)
31#define IS_QUAD_OP (1ULL << kIsQuadOp)
32#define IS_QUIN_OP (1ULL << kIsQuinOp)
33#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp)
34#define IS_STORE (1ULL << kMemStore)
35#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp)
36#define IS_UNARY_OP (1ULL << kIsUnaryOp)
37#define NEEDS_FIXUP (1ULL << kPCRelFixup)
38#define NO_OPERAND (1ULL << kNoOperand)
39#define REG_DEF0 (1ULL << kRegDef0)
40#define REG_DEF1 (1ULL << kRegDef1)
41#define REG_DEFA (1ULL << kRegDefA)
42#define REG_DEFD (1ULL << kRegDefD)
43#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0)
44#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2)
45#define REG_DEF_LIST0 (1ULL << kRegDefList0)
46#define REG_DEF_LIST1 (1ULL << kRegDefList1)
47#define REG_DEF_LR (1ULL << kRegDefLR)
48#define REG_DEF_SP (1ULL << kRegDefSP)
49#define REG_USE0 (1ULL << kRegUse0)
50#define REG_USE1 (1ULL << kRegUse1)
51#define REG_USE2 (1ULL << kRegUse2)
52#define REG_USE3 (1ULL << kRegUse3)
53#define REG_USE4 (1ULL << kRegUse4)
54#define REG_USEA (1ULL << kRegUseA)
55#define REG_USEC (1ULL << kRegUseC)
56#define REG_USED (1ULL << kRegUseD)
57#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0)
58#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2)
59#define REG_USE_LIST0 (1ULL << kRegUseList0)
60#define REG_USE_LIST1 (1ULL << kRegUseList1)
61#define REG_USE_LR (1ULL << kRegUseLR)
62#define REG_USE_PC (1ULL << kRegUsePC)
63#define REG_USE_SP (1ULL << kRegUseSP)
64#define SETS_CCODES (1ULL << kSetsCCodes)
65#define USES_CCODES (1ULL << kUsesCCodes)
66
67// Common combo register usage patterns.
68#define REG_DEF01 (REG_DEF0 | REG_DEF1)
69#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
70#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01)
71#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0)
72#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12)
73#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1)
74#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2)
75#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED)
76#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD)
77#define REG_DEFA_USEA (REG_DEFA | REG_USEA)
78#define REG_USE012 (REG_USE01 | REG_USE2)
79#define REG_USE014 (REG_USE01 | REG_USE4)
80#define REG_USE01 (REG_USE0 | REG_USE1)
81#define REG_USE02 (REG_USE0 | REG_USE2)
82#define REG_USE12 (REG_USE1 | REG_USE2)
83#define REG_USE23 (REG_USE2 | REG_USE3)
84
85typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, uint32_t dex_idx,
86 uint32_t method_idx, uintptr_t direct_code,
87 uintptr_t direct_method, InvokeType type);
88
89// Target-specific initialization.
90bool InitArmCodegen(CompilationUnit* cu);
91bool InitMipsCodegen(CompilationUnit* cu);
92bool InitX86Codegen(CompilationUnit* cu);
93
94class Codegen {
95
96 public:
97
98 virtual ~Codegen(){};
99
100 // Shared by all targets - implemented in gen_common.cc.
101 void HandleSuspendLaunchPads(CompilationUnit *cu);
102 void HandleIntrinsicLaunchPads(CompilationUnit *cu);
103 void HandleThrowLaunchPads(CompilationUnit *cu);
104 void GenBarrier(CompilationUnit* cu);
105 LIR* GenCheck(CompilationUnit* cu, ConditionCode c_code, ThrowKind kind);
106 LIR* GenImmedCheck(CompilationUnit* cu, ConditionCode c_code, int reg, int imm_val,
107 ThrowKind kind);
108 LIR* GenNullCheck(CompilationUnit* cu, int s_reg, int m_reg, int opt_flags);
109 LIR* GenRegRegCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int reg2,
110 ThrowKind kind);
111 void GenCompareAndBranch(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_src1,
112 RegLocation rl_src2, LIR* taken, LIR* fall_through);
113 void GenCompareZeroAndBranch(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_src,
114 LIR* taken, LIR* fall_through);
115 void GenIntToLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
116 void GenIntNarrowing(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
117 RegLocation rl_src);
118 void GenNewArray(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_dest,
119 RegLocation rl_src);
120 void GenFilledNewArray(CompilationUnit* cu, CallInfo* info);
121 void GenSput(CompilationUnit* cu, uint32_t field_idx, RegLocation rl_src,
122 bool is_long_or_double, bool is_object);
123 void GenSget(CompilationUnit* cu, uint32_t field_idx, RegLocation rl_dest,
124 bool is_long_or_double, bool is_object);
125 void GenShowTarget(CompilationUnit* cu);
126 void GenIGet(CompilationUnit* cu, uint32_t field_idx, int opt_flags, OpSize size,
127 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object);
128 void GenIPut(CompilationUnit* cu, uint32_t field_idx, int opt_flags, OpSize size,
129 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object);
130 void GenConstClass(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_dest);
131 void GenConstString(CompilationUnit* cu, uint32_t string_idx, RegLocation rl_dest);
132 void GenNewInstance(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_dest);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]133 void GenThrow(CompilationUnit* cu, RegLocation rl_src);
134 void GenInstanceof(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_dest,
135 RegLocation rl_src);
136 void GenCheckCast(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_src);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]137 void GenLong3Addr(CompilationUnit* cu, OpKind first_op, OpKind second_op, RegLocation rl_dest,
138 RegLocation rl_src1, RegLocation rl_src2);
139 bool GenShiftOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
140 RegLocation rl_src1, RegLocation rl_shift);
141 bool GenArithOpInt(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
142 RegLocation rl_src1, RegLocation rl_src2);
143 bool GenArithOpIntLit(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
144 RegLocation rl_src, int lit);
145 bool GenArithOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
146 RegLocation rl_src1, RegLocation rl_src2);
147 bool GenConversionCall(CompilationUnit* cu, int func_offset, RegLocation rl_dest,
148 RegLocation rl_src);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]149 void GenSuspendTest(CompilationUnit* cu, int opt_flags);
150 void GenSuspendTestAndBranch(CompilationUnit* cu, int opt_flags, LIR* target);
151
152 // Shared by all targets - implemented in gen_invoke.cc.
153 int CallHelperSetup(CompilationUnit* cu, int helper_offset);
154 LIR* CallHelper(CompilationUnit* cu, int r_tgt, int helper_offset, bool safepoint_pc);
155 void CallRuntimeHelperImm(CompilationUnit* cu, int helper_offset, int arg0, bool safepoint_pc);
156 void CallRuntimeHelperReg(CompilationUnit* cu, int helper_offset, int arg0, bool safepoint_pc);
157 void CallRuntimeHelperRegLocation(CompilationUnit* cu, int helper_offset, RegLocation arg0,
158 bool safepoint_pc);
159 void CallRuntimeHelperImmImm(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
160 bool safepoint_pc);
161 void CallRuntimeHelperImmRegLocation(CompilationUnit* cu, int helper_offset, int arg0,
162 RegLocation arg1, bool safepoint_pc);
163 void CallRuntimeHelperRegLocationImm(CompilationUnit* cu, int helper_offset, RegLocation arg0,
164 int arg1, bool safepoint_pc);
165 void CallRuntimeHelperImmReg(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
166 bool safepoint_pc);
167 void CallRuntimeHelperRegImm(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
168 bool safepoint_pc);
169 void CallRuntimeHelperImmMethod(CompilationUnit* cu, int helper_offset, int arg0,
170 bool safepoint_pc);
171 void CallRuntimeHelperRegLocationRegLocation(CompilationUnit* cu, int helper_offset,
172 RegLocation arg0, RegLocation arg1,
173 bool safepoint_pc);
174 void CallRuntimeHelperRegReg(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
175 bool safepoint_pc);
176 void CallRuntimeHelperRegRegImm(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
177 int arg2, bool safepoint_pc);
178 void CallRuntimeHelperImmMethodRegLocation(CompilationUnit* cu, int helper_offset, int arg0,
179 RegLocation arg2, bool safepoint_pc);
180 void CallRuntimeHelperImmMethodImm(CompilationUnit* cu, int helper_offset, int arg0, int arg2,
181 bool safepoint_pc);
182 void CallRuntimeHelperImmRegLocationRegLocation(CompilationUnit* cu, int helper_offset,
183 int arg0, RegLocation arg1, RegLocation arg2,
184 bool safepoint_pc);
185 void GenInvoke(CompilationUnit* cu, CallInfo* info);
186 void FlushIns(CompilationUnit* cu, RegLocation* ArgLocs, RegLocation rl_method);
187 int GenDalvikArgsNoRange(CompilationUnit* cu, CallInfo* info, int call_state, LIR** pcrLabel,
188 NextCallInsn next_call_insn, uint32_t dex_idx, uint32_t method_idx,
189 uintptr_t direct_code, uintptr_t direct_method, InvokeType type,
190 bool skip_this);
191 int GenDalvikArgsRange(CompilationUnit* cu, CallInfo* info, int call_state, LIR** pcrLabel,
192 NextCallInsn next_call_insn, uint32_t dex_idx, uint32_t method_idx,
193 uintptr_t direct_code, uintptr_t direct_method, InvokeType type,
194 bool skip_this);
195 RegLocation InlineTarget(CompilationUnit* cu, CallInfo* info);
196 RegLocation InlineTargetWide(CompilationUnit* cu, CallInfo* info);
197 CallInfo* NewMemCallInfo(CompilationUnit* cu, BasicBlock* bb, MIR* mir, InvokeType type,
198 bool is_range);
199 bool GenInlinedCharAt(CompilationUnit* cu, CallInfo* info);
200 bool GenInlinedStringIsEmptyOrLength(CompilationUnit* cu, CallInfo* info, bool is_empty);
201 bool GenInlinedAbsInt(CompilationUnit *cu, CallInfo* info);
202 bool GenInlinedAbsLong(CompilationUnit *cu, CallInfo* info);
203 bool GenInlinedFloatCvt(CompilationUnit *cu, CallInfo* info);
204 bool GenInlinedDoubleCvt(CompilationUnit *cu, CallInfo* info);
205 bool GenInlinedIndexOf(CompilationUnit* cu, CallInfo* info, bool zero_based);
206 bool GenInlinedStringCompareTo(CompilationUnit* cu, CallInfo* info);
Ian Rogers07ec8e12012-12-01 01:26:51 -0800[diff] [blame]207 bool GenInlinedCurrentThread(CompilationUnit* cu, CallInfo* info);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]208 bool GenIntrinsic(CompilationUnit* cu, CallInfo* info);
209
210 // Shared by all targets - implemented in gen_loadstore.cc.
211 RegLocation LoadCurrMethod(CompilationUnit *cu);
212 void LoadCurrMethodDirect(CompilationUnit *cu, int r_tgt);
213 LIR* LoadConstant(CompilationUnit* cu, int r_dest, int value);
214 LIR* LoadWordDisp(CompilationUnit* cu, int rBase, int displacement, int r_dest);
215 RegLocation LoadValue(CompilationUnit* cu, RegLocation rl_src, RegisterClass op_kind);
216 RegLocation LoadValueWide(CompilationUnit* cu, RegLocation rl_src, RegisterClass op_kind);
217 void LoadValueDirect(CompilationUnit* cu, RegLocation rl_src, int r_dest);
218 void LoadValueDirectFixed(CompilationUnit* cu, RegLocation rl_src, int r_dest);
219 void LoadValueDirectWide(CompilationUnit* cu, RegLocation rl_src, int reg_lo, int reg_hi);
220 void LoadValueDirectWideFixed(CompilationUnit* cu, RegLocation rl_src, int reg_lo, int reg_hi);
221 LIR* StoreWordDisp(CompilationUnit* cu, int rBase, int displacement, int r_src);
222 void StoreValue(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
223 void StoreValueWide(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
224
225 // Required for target - codegen helpers.
226 virtual bool SmallLiteralDivide(CompilationUnit* cu, Instruction::Code dalvik_opcode,
227 RegLocation rl_src, RegLocation rl_dest, int lit) = 0;
228 virtual int LoadHelper(CompilationUnit* cu, int offset) = 0;
229 virtual LIR* LoadBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_dest,
230 OpSize size, int s_reg) = 0;
231 virtual LIR* LoadBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_dest_lo,
232 int r_dest_hi, int s_reg) = 0;
233 virtual LIR* LoadBaseIndexed(CompilationUnit* cu, int rBase, int r_index, int r_dest, int scale,
234 OpSize size) = 0;
235 virtual LIR* LoadBaseIndexedDisp(CompilationUnit *cu, int rBase, int r_index, int scale,
236 int displacement, int r_dest, int r_dest_hi, OpSize size,
237 int s_reg) = 0;
238 virtual LIR* LoadConstantNoClobber(CompilationUnit* cu, int r_dest, int value) = 0;
239 virtual LIR* LoadConstantValueWide(CompilationUnit* cu, int r_dest_lo, int r_dest_hi,
240 int val_lo, int val_hi) = 0;
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]241 virtual LIR* StoreBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_src,
242 OpSize size) = 0;
243 virtual LIR* StoreBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_src_lo,
244 int r_src_hi) = 0;
245 virtual LIR* StoreBaseIndexed(CompilationUnit* cu, int rBase, int r_index, int r_src, int scale,
246 OpSize size) = 0;
247 virtual LIR* StoreBaseIndexedDisp(CompilationUnit *cu, int rBase, int r_index, int scale,
248 int displacement, int r_src, int r_src_hi, OpSize size,
249 int s_reg) = 0;
250 virtual void MarkGCCard(CompilationUnit* cu, int val_reg, int tgt_addr_reg) = 0;
251
252 // Required for target - register utilities.
253 virtual bool IsFpReg(int reg) = 0;
254 virtual bool SameRegType(int reg1, int reg2) = 0;
255 virtual int AllocTypedTemp(CompilationUnit* cu, bool fp_hint, int reg_class) = 0;
256 virtual int AllocTypedTempPair(CompilationUnit* cu, bool fp_hint, int reg_class) = 0;
257 virtual int S2d(int low_reg, int high_reg) = 0;
258 virtual int TargetReg(SpecialTargetRegister reg) = 0;
259 virtual RegisterInfo* GetRegInfo(CompilationUnit* cu, int reg) = 0;
260 virtual RegLocation GetReturnAlt(CompilationUnit* cu) = 0;
261 virtual RegLocation GetReturnWideAlt(CompilationUnit* cu) = 0;
262 virtual RegLocation LocCReturn() = 0;
263 virtual RegLocation LocCReturnDouble() = 0;
264 virtual RegLocation LocCReturnFloat() = 0;
265 virtual RegLocation LocCReturnWide() = 0;
266 virtual uint32_t FpRegMask() = 0;
267 virtual uint64_t GetRegMaskCommon(CompilationUnit* cu, int reg) = 0;
268 virtual void AdjustSpillMask(CompilationUnit* cu) = 0;
269 virtual void ClobberCalleeSave(CompilationUnit *cu) = 0;
270 virtual void FlushReg(CompilationUnit* cu, int reg) = 0;
271 virtual void FlushRegWide(CompilationUnit* cu, int reg1, int reg2) = 0;
272 virtual void FreeCallTemps(CompilationUnit* cu) = 0;
273 virtual void FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep, RegLocation rl_free) = 0;
274 virtual void LockCallTemps(CompilationUnit* cu) = 0;
275 virtual void MarkPreservedSingle(CompilationUnit* cu, int v_reg, int reg) = 0;
276 virtual void CompilerInitializeRegAlloc(CompilationUnit* cu) = 0;
277
278 // Required for target - miscellaneous.
279 virtual AssemblerStatus AssembleInstructions(CompilationUnit* cu, uintptr_t start_addr) = 0;
280 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0;
281 virtual void SetupTargetResourceMasks(CompilationUnit* cu, LIR* lir) = 0;
282 virtual const char* GetTargetInstFmt(int opcode) = 0;
283 virtual const char* GetTargetInstName(int opcode) = 0;
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]284 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0;
285 virtual uint64_t GetPCUseDefEncoding() = 0;
286 virtual uint64_t GetTargetInstFlags(int opcode) = 0;
287 virtual int GetInsnSize(LIR* lir) = 0;
288 virtual bool IsUnconditionalBranch(LIR* lir) = 0;
289
290 // Required for target - Dalvik-level generators.
291 virtual bool GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
292 RegLocation rl_src2) = 0;
293 virtual bool GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
294 RegLocation rl_src2) = 0;
295 virtual bool GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
296 RegLocation rl_dest, RegLocation rl_src1,
297 RegLocation rl_src2) = 0;
298 virtual bool GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
299 RegLocation rl_src1, RegLocation rl_src2) = 0;
300 virtual bool GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
301 RegLocation rl_src1, RegLocation rl_src2) = 0;
302 virtual bool GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
303 RegLocation rl_src) = 0;
304 virtual bool GenInlinedCas32(CompilationUnit* cu, CallInfo* info, bool need_write_barrier) = 0;
305 virtual bool GenInlinedMinMaxInt(CompilationUnit *cu, CallInfo* info, bool is_min) = 0;
306 virtual bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info) = 0;
307 virtual bool GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src) = 0;
308 virtual bool GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
309 RegLocation rl_src2) = 0;
310 virtual bool GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
311 RegLocation rl_src2) = 0;
312 virtual bool GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
313 RegLocation rl_src2) = 0;
314 virtual LIR* GenRegMemCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int base,
315 int offset, ThrowKind kind) = 0;
316 virtual RegLocation GenDivRem(CompilationUnit* cu, RegLocation rl_dest, int reg_lo, int reg_hi,
317 bool is_div) = 0;
318 virtual RegLocation GenDivRemLit(CompilationUnit* cu, RegLocation rl_dest, int reg_lo, int lit,
319 bool is_div) = 0;
320 virtual void GenCmpLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
321 RegLocation rl_src2) = 0;
322 virtual void GenDivZeroCheck(CompilationUnit* cu, int reg_lo, int reg_hi) = 0;
323 virtual void GenEntrySequence(CompilationUnit* cu, RegLocation* ArgLocs,
324 RegLocation rl_method) = 0;
325 virtual void GenExitSequence(CompilationUnit* cu) = 0;
326 virtual void GenFillArrayData(CompilationUnit* cu, uint32_t table_offset,
327 RegLocation rl_src) = 0;
328 virtual void GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir, bool gt_bias,
329 bool is_double) = 0;
330 virtual void GenFusedLongCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir) = 0;
331 virtual void GenMemBarrier(CompilationUnit* cu, MemBarrierKind barrier_kind) = 0;
332 virtual void GenMonitorEnter(CompilationUnit* cu, int opt_flags, RegLocation rl_src) = 0;
333 virtual void GenMonitorExit(CompilationUnit* cu, int opt_flags, RegLocation rl_src) = 0;
jeffhao1eab9582013-01-22 13:33:52 -0800[diff] [blame]334 virtual void GenMoveException(CompilationUnit* cu, RegLocation rl_dest) = 0;
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]335 virtual void GenMultiplyByTwoBitMultiplier(CompilationUnit* cu, RegLocation rl_src,
336 RegLocation rl_result, int lit, int first_bit,
337 int second_bit) = 0;
338 virtual void GenNegDouble(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src) = 0;
339 virtual void GenNegFloat(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src) = 0;
340 virtual void GenPackedSwitch(CompilationUnit* cu, uint32_t table_offset,
341 RegLocation rl_src) = 0;
342 virtual void GenSparseSwitch(CompilationUnit* cu, uint32_t table_offset,
343 RegLocation rl_src) = 0;
344 virtual void GenSpecialCase(CompilationUnit* cu, BasicBlock* bb, MIR* mir,
345 SpecialCaseHandler special_case) = 0;
buzbeee6285f92012-12-06 15:57:46 -0800[diff] [blame]346 virtual void GenArrayObjPut(CompilationUnit* cu, int opt_flags, RegLocation rl_array,
347 RegLocation rl_index, RegLocation rl_src, int scale) = 0;
348 virtual void GenArrayGet(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
349 RegLocation rl_index, RegLocation rl_dest, int scale) = 0;
350 virtual void GenArrayPut(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
351 RegLocation rl_index, RegLocation rl_src, int scale) = 0;
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]352
353 // Required for target - single operation generators.
354 virtual LIR* OpUnconditionalBranch(CompilationUnit* cu, LIR* target) = 0;
355 virtual LIR* OpCmpBranch(CompilationUnit* cu, ConditionCode cond, int src1, int src2,
356 LIR* target) = 0;
357 virtual LIR* OpCmpImmBranch(CompilationUnit* cu, ConditionCode cond, int reg, int check_value,
358 LIR* target) = 0;
359 virtual LIR* OpCondBranch(CompilationUnit* cu, ConditionCode cc, LIR* target) = 0;
360 virtual LIR* OpDecAndBranch(CompilationUnit* cu, ConditionCode c_code, int reg,
361 LIR* target) = 0;
362 virtual LIR* OpFpRegCopy(CompilationUnit* cu, int r_dest, int r_src) = 0;
363 virtual LIR* OpIT(CompilationUnit* cu, ConditionCode cond, const char* guide) = 0;
364 virtual LIR* OpMem(CompilationUnit* cu, OpKind op, int rBase, int disp) = 0;
365 virtual LIR* OpPcRelLoad(CompilationUnit* cu, int reg, LIR* target) = 0;
366 virtual LIR* OpReg(CompilationUnit* cu, OpKind op, int r_dest_src) = 0;
367 virtual LIR* OpRegCopy(CompilationUnit* cu, int r_dest, int r_src) = 0;
368 virtual LIR* OpRegCopyNoInsert(CompilationUnit* cu, int r_dest, int r_src) = 0;
369 virtual LIR* OpRegImm(CompilationUnit* cu, OpKind op, int r_dest_src1, int value) = 0;
370 virtual LIR* OpRegMem(CompilationUnit* cu, OpKind op, int r_dest, int rBase, int offset) = 0;
371 virtual LIR* OpRegReg(CompilationUnit* cu, OpKind op, int r_dest_src1, int r_src2) = 0;
372 virtual LIR* OpRegRegImm(CompilationUnit* cu, OpKind op, int r_dest, int r_src1, int value) = 0;
373 virtual LIR* OpRegRegReg(CompilationUnit* cu, OpKind op, int r_dest, int r_src1,
374 int r_src2) = 0;
375 virtual LIR* OpTestSuspend(CompilationUnit* cu, LIR* target) = 0;
376 virtual LIR* OpThreadMem(CompilationUnit* cu, OpKind op, int thread_offset) = 0;
377 virtual LIR* OpVldm(CompilationUnit* cu, int rBase, int count) = 0;
378 virtual LIR* OpVstm(CompilationUnit* cu, int rBase, int count) = 0;
379 virtual void OpLea(CompilationUnit* cu, int rBase, int reg1, int reg2, int scale,
380 int offset) = 0;
381 virtual void OpRegCopyWide(CompilationUnit* cu, int dest_lo, int dest_hi, int src_lo,
382 int src_hi) = 0;
383 virtual void OpTlsCmp(CompilationUnit* cu, int offset, int val) = 0;
buzbeee6285f92012-12-06 15:57:46 -0800[diff] [blame]384 virtual bool InexpensiveConstant(int reg, int value) = 0;
buzbee5f61f672012-11-28 17:22:17 -0800[diff] [blame]385
386 // Temp workaround
387 void Workaround7250540(CompilationUnit* cu, RegLocation rl_dest, int value);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]388 }; // Class Codegen
389
390} // namespace art
391
392#endif // ART_SRC_COMPILER_CODEGEN_CODEGEN_H_